Parallel parasitic conductance in narrow-width MOSFETs

Solid-State ElectronicsVol. 34, No. 12, pp. 1381-1386,1991 Printed in Great Britain.All rights reserved

PARALLEL

0038-1101/91 $3.00+ 0.00 Copyright ~ 1991PergamonPress pk

PARASITIC

CONDUCTANCE

NARROW-WIDTH

IN

MOSFETs

Z. P. Zuo and M. J. DEENt School of Engineering Science, Simon Fraser University, Burnaby, BC, Canada V5A IS6 (Received 15 March 1991; in revised form 10 June 1991)

Al~ernet--One of the edge effects of narrow-width MOSFETs can be expressed as a parallel parasitic conductance Gp. Gp And the width reduction AW were determined from the variation of device's conductance GTvs mask gate width WMat different effective gate biases Vos - VT. The intersection point of these GT vs WMfor different Vos - VTbiases occurs at Gp and AW. A series of experiments in which external conductances were placed in parallel with the MOS transistor were performed, and the results verified the concept of the parallel parasitic conductance, and the algorithm for extracting both Gp and AW.

NOTATION Cox (7,=

GTp Im L,e Lma Rp

gate oxide capacitance per unit area (F cm -2) external conductance placed in parallel with the MOSFET (S) intrinsic conductance of the MOSFET (S) total parallel parasitic conductance of a MOS transistor (S) total conductance (S), (GT = Gi-4-GI,without any external conductance), (GT= Gi + Gp + Gat with an external conductance) total extrinisic conductance [GTp= Gp + G,~t (S)] total drain current in the MOSFET (A) effectivechannel length (/~m) drawn (mask) gate length (/~m) total parasitic resistance in series with the intrinsic

Vm

drain--source voltage (V)

Vos

gate-source voltage (V)

Vr W,e WM AW /~

threshold voltage (V) effectivechannel width (/~m) drawn (mask) gate width (/~m) channel width reduction lAW = Wma- We~(#m)] low-fieldmobility (cm2 V-I s -1)

Gi

Gp GT

MOS device (f~)

1. INTRODUCTION As the dimensions of the MOSFETs are shrunk to smaller values in the sub-micron range, second-order effects describing the device's behavior become increasingly important. Some basic second-order effects, e.g. channel length reduction AL and part of parasitic series resistance Rp, occur in the edge regions BL along the length direction, while others, e.g. channel width reduction A W occur in the edges Bw along the width direction, as shown in Fig. 1. These second-order effects of the MOSFETs play very important roles in enabling us to a~urately predict their terminal ~ t - v o l t a g e characteristics for use in VLSI circuits such as DRAMs etc. Such predictions, whether by simulations or by calculations, are now increasingly important since they tTo whom all correspondence should be addressed.

must be done before the expense of fabricating the devices are incurred. Previously, most researchers[I-7] concentrated their efforts in developing accurate techniques for determining the second-order effects AL and RF in short-channel MOSFETs. In contrast, fewer researchers[7-10] have studied how to determine the parasitic effects associated with narrow.width MOSFETs. The basic assumption of Ma and WanglS] was that all the lines corresponding to different gate voltages in a plot of GT vs WMintercepted the abscissa at the same point. Their GT vs WM plots were at a low VDsbias for a linear mode of operation, and high Vos biases so that they could neglect the effect of varying VT with channel width. However, a detailed examination of the variation of GT vs WM shows that the intersection point of the different Vos lines is not exactly on the WM axis, but is rather below it in the fourth quadrant, as shown in Fig. 2. This means that the edge effects along the width direction should be expressed as a pair of parameters: accompanying the traditional parameter A W, there should be a new parameter Gp. Gp Is a "negative" parasitic conductance in parallel with intrinsic MOSFETs. The negative value of Gp does not mean that there is a real negative conductance within MOSFET devices, it is only an equivalent conductance that is obtained from a I-D model of the current-voltage description of narrow-width. In [9], it was stated that when the value of (Vos-VT) was small enough, for example when V o s - Vr = 0.3 V, the series parasitic resistance RF could be neglected. Although this assumption of neglecting Rp at low effective gate bias voltages is correct, Gp must be taken into account in the parameter extraction procedure. We note that in both these publications[8,9], that assumptions were made to minimize the effects of either Gp or Rp in determining the effective channel width. Also, only techniques for determining only A W were described.

1381

1382

Z.P. Zuo and M. J.

!

(e) d e v i c e

edge region in length direction

e d g e region in width direction

channel

cross-section

~ B.

<~] / I;> ~T..~CX,~XX X ~(xx X ~ x • ~,

aw

~,,

7,

"~ c co .r.~

~

--

~

channel

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~

~-)(xxxxxxxxxxx)

E (D O -0 ~;'~

.~

E

~'~ "0 ~ (b) t o p v i e w for the g a t e

~) ~-

Fig. 1. (a) Cross-sectional view ofa MOSFET. (b) Top view of the channel region showing the edge regions in both the length and the width directions. In [11], a new I-D model that describes the edge effects in narrow-width MOSFETs was proposed. The proposed model was also used to study the variation of the parameters describing the edge effects with the effective gate biases. Here, we present exper0.25

a4.8

v= ~

V ~

Ca)

+ 4.e

0.20

v

V~ ~ = 5 . 4 V

0.15 O~ • 5.= ~I I= O

V~f4.6V

0.05 O.OG~ '-"~"

Fig. 2 b

-0.05 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

~4.0 4.5

M a s k G a t e W i d t h W,,, (jam) 0.10

(b) v

0.05 0,00

;_oo5 -o.10

I= O

-0,15

U

2. BASIC MODEL AND ALGORITHM

Gp

=1

-0.20 OA.

imental proof of the concept of a negative parallel parasitic conductance, and the algorithm for extracting both A W and Gp. The MOSFETs used in this study had a channel doping of ~ 2 × 10~6 crn -3, an oxide thickness of 250~, and source and drain junction depth of ~0.28 #m. The devices were isolated by a standard LOCOS process in which the field oxide thickness was ~7000.~. The MOS devices had a common mask channel length 12 #m, and varying mask widths 1.8, 2.4, 3.0, 3.6 and 4.2 #m. These devices were from two groups, a PMOS transistor group, and an NMOS transistor group. All the devices in the same group were made by the same fabrication process, and they had identical geometries except for their mask widths. In our experiments the linear lvs vs Vos measurements were made with Vve -- 0.1 V, Vsa ffi 0 V and Vos = 0-8 V. The experimental data were acquired from an automated lip 4145 A Semiconductor Parameter Analyzer. An IBM PC/AT computer was used for data acquisition and for extracting the parameter values from the acquired data.

0.5

O.B

0.7

O,B

Mask G a t e W i d t h W , n (jam) Fig. 2. (a) The proposed method to extract A W and Gp. The values of V o s - VT were 4.6, 4.8, 5, 5.2, 5.4V, Vvs •0.1V and Vss -- 0 V. (b) The enlarged area around the intersection point of Fig. 2a.

In [11], the model shown in Fig. 3a was used investigate the dependence of the edge effects in the width direction on the effective gate biasing voltages. There, we described in detail new techniques for extracting both Gr and Rp from the experimental data. Two very important conclusions from [11] were: 1. The value of Gp is negative and its absolute value increases with the gate bias.

Parasitic conductance in MOSFETs V

°'

....... i

2. The absolute value of Gp is large compared to the experimental error associated with the total conductance GT. This means that Vos biases should not be very low. 3. G~ does not vary much with Vos. A small range of Vos biases, e.g. Vos + 0.4 V, was chosen for the results described later.

::i ......

/

i=11,, ,1o

1383

Go ,,v',,,

Using the above criteria for the P M O S group of devices the region of V o s - VT = 4.6-5.4 V was selected. With this choice of Vos - VT, the above three conditions can be quantitatively restated as:

W=We,, /

1. (Re/IDs)/VDS < 5%. This means that the error resulting from neglecting Re would not be more than 5%. 2. Ge ,~ 1 × 10 -6 S compared with the experimental error in GT which was less than 3 x 10-sS. 3. The variation of Gp was less then 5% when V o s - VT biases were varied from 4.6 to 5.4 V. A larger range of V o s - VT values would result in larger variations in Gp, while a smaller range results in larger errors determining Ge and A W.

Vs V D

(b) I

...................

',,ll=l,,i W

=

Go

,,v,~

When above conditions are satisfied, Fig. 3b can be used as a good approximation for Fig. 3a. We can now write the IDs--Vos relation for a M O S F E T in its linear mode of operation as:

[DS----//CoxL-~-~-ff~(Vos -- VT)VDS + OPVDS.

I

(I)

L =

The total conductance can then be expressed as:

Gz -- ~

= Gi -{-Gp =//Cox LeftW~

VS Fig. 3. (a) To model the parasitic effects. Rp and Ge are used to represent parts of the edge effects along the length and width directions, respectively. (b) For the range of Vos - VT biasing voltages chosen, we can neglect the effects of Re. 2. Rp Is inversely proportional to effective channel width, and its effect becomes increasingly important as the gate voltage biases were increased. To verify the existence of a negative conductance in parallel with the intrinsic MOSFET, a special range of gate biases satisfying the three conditions below was chosen. With this range of gate biases, the current-voltage description of the M O S F E T is simplified, and the three conditions are: 1. The effect of Rp is small enough to be neglected in a first-order approximation. To satisfy this condition, the Vos biases should not be very high. Although we can extract Rr from the experimental data first and then eliminate its effect, it is better for the "focus o f this paper to choose the range of gate bias voltages so that the effect o f Re can be neglected. This simpfifies the problem and allows us to concentrate on Gp.

x(Vas- VT)+Cp----AWM+B,

(2)

where W~ ffi WM -- AW,

(3)

B = Gp - A A W ,

(4)

,4 =//Cox(Vos - vT) L~

(5)

From the above expressions, it is obvious that GT is a function of both (Vos - VT) and WM, and that both A and B are functions of (Vos - VT). In ¢qn (2), when Ge -- Gz, then A W ffiWM, that is, the intersection GT vS W M lines at varying (Vos -- VT) occurs at the coordinates (AW, Ge). However, for the parameter extraction described here, we used the duallinear fittingmethod[7] to extract Gp and A W. In this dual-linear fitting technique, we firstly perform a linear least squares fittingof GT vs W M to obtain a set of A (slopes) and B (intercepts).Then we performed a subsequent linear least squares fittingof B vs A to get Ge (intercept) and A W (negative slope). To summarize, the algorithm for determining Gp and A W is: (a) select a group of M O S F E T s the W M dimension;

differing only in

Z. P. Zuo and M. J. DimN

1384

Figure 6a shows the results from four external conductances (resistances) of different values that were placed in parallel with same group of P M O S devices, and Fig. 6b shows the corresponding results for the NMOS group. As expected, the values of AW changed very little, by less than 10% (that is, they only changed in the experimental error region of +0.05/~m), but the value of Gw was proportional to G,~t. From G~ vs G~t in Figs 6a and b, the slopes are both ~ 1, and the intercepts on the GTp axis are Gp, that is, eqn (6) is indeed correct. These results are very important evidence that the concept of a large signal Gp and the algorithm described above in Section 2 are correct.

V D

external "onductance

V~

I--I

G.xt

' /

MOS [. . . . . . . . . .

Device ÷ . . . . . . . .

MS

Fig. 4. An external conductance (resistance) is added in parallel to the device to check the behavior of parallel parasitic conductance for narrow width devices. The extracted values of AW and GTv can then be plotted as a function of G,~t. Co) measure IDs vs Vos curve at a low drain bias and with varying gate biases; (c) extract VT for each devices by the conventional linear extrapohRion technique; (d) select an appropriate region of (Vos - VT, e,g. 4.6-5.4 V, and calculate GT from GT = IDs/VDs;

4. DISCUSSION 1. To compare our proposed method to extract Gp and AW with the traditional method[l] used to extract AL and Rp, Fig. 7 shows a plot of the total channel resistance vs mask length for a group of varying channel length devices. When Fig. 7 is compared with Fig. 2, which is from our 0.30

PMO$ Vl - VT = 4.6 to 5,4V stlp-O2V / ~

0.25

and then; (e) perform the dual linear fitting method described above to extract Gp and A W.

(~

0.20

sJ

GN = 1.78.104

0.15

0.10

3. EXPERIMENTSWITH EXTERNAL CONDUCTANCE

0.05

A series of experiments were then performed to confirm the concept of Gp and the algorithm described above. Several external conductances (resistances), one at a time, were placed in parallel with the devices, as shown in Fig. 4. Then the procedure described in Section 2 was repeated, but with two modifications: (1) step (c) was skipped because the threshold voltage of the device should not vary with the external conductance; (2) in step (e), the parameters extracted from the dual linear fitting method are the total parallel conductance GTp and A W, and are not Gp and AW. If the concept of Gp and the algorithm described above is correct, then it is expected that:

t G~

o.oo ~ -0.05

Milk

(6)

Therefore, with the addition of an external conductance, the intersection point of the lines corresponding to different ( V o s - ;IT) value should be shifted up vertically along the GTF axis, but not horizontally along the WM axis. This is clearly shown in Fig. 5, verifying the existence of a negative Gp.

Fig. 5b ~ L 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Gite

W i d t h W=.k (JAm.)

0.20

0.10

6 II -0.10

--0,20 0.0

GTp = Gp + G,..

L

~ 0.0 0.5

0.2

Malk e l t 0

0.4

0.6

0.8

1.0

W i d t h W.~ ( ~ m )

Fig. 5. (a) When an external conductance (resistance) is added in parallel to the device, the intersection of the full lines move up exactly along the GTpaxis direction from the original intersection point of the broken lines. This means that GTF increased with G~t , but that AW was unchanged. The different lines are for the same five Vos - VTbiases used in Fig. 2 above. Co) This figure shows the enlarged area around the intersection point in Fig. 5a.

Parasitic conductance in MOSFETs

]

1,0

0.06

Table 1. ComparisonbetweenFigs 2 and 7

(a)

Fig. 7

0.8

J

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Fig. 2

0.0 t

0.6

Device types x-Axis variable y-Axis variable Intersectionpoint

~

Coordinate of the

|

intersection -0.10

Short length Mask length Lu Resistance R 1st quadrant x = AL y = Rv

Narrow width Mask width W u Conductono¢ O 4th quadrant x = AW y = -- Ge

I~1

0.2

m t @ r ~ t G. 0.0 O.Oe÷O0

--0.15

5.0e-07

I.Oe-O6

1.5e-06

2.0e-06

External Conductance G . t (S) 2.0

0.05

1.6

~os

~

(b)

~

0.8

O.Ol

=0.08

o"

-0.07 zW

0.0 O.Oe÷O0

3.0e-07

~..Os-07

External

, 9.0e-07

Conductance

1.2e-05

-0.15 1.5e-06

G . , (S)

Fig. 6. Variation of A W and G~ with Gm. Note that while A W was almost the same value, G~ increased linearly with G~I: (a) is for PMOS group devices; and (b) is for NMOS group devices. For both graphs, the correlation coef~cient of the straight line fits G~ vs G~t was better than 0.999. experiments for a group of varying channel width devices, it is very interesting to observe that these two figures are symmetric, as detailed in Table 1. However, there are some differences between the narrow width and the short channel devices. F o r devices with conventionally doped drains, Re has a very weak dependence on VGs, but Ge is a strong function VGS. Also, AL is almost independent of Vts, but as shown in [11], A W decreases with Vos. 2. It should be emphasized, the negative conductance Gv used in this paper is not a real physical parameter, but rather arises directly from the model eqn (1) used as the starting point in the parameter extraction algorithm. Since the effec-

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i

This paper reported on detailed measurements of the parallel parasitic conductance in narrow-width MOSFETs. A procedure for extracting Gp was presented, and the existence of Ge was proved by adding external conductances in parallel to the M O S F E T and showing that while G ~ increased proportionately with Gut, A W was essentially unchanged. Finally, a discussion of the similarities and differences between the behavior of Gp and A W, compared to that of Rp and AL at varying effective gate biases was presented. assistance of J. Ilowski and R. Hadaway of Northern Telecom Electronics Limited, Ottawa. This research was supported in part by grants from the Center for Systems Science, Simon Fraser University, from the Natural Sciences and Engineering Research Council (NSERC) of Canada, and from Northern Telecom Electronics Ltd.

+ 2.72

2000

.I

5. C O N C L U S I O N

Acknowledgements--It is a pleasure to acknowledge the

2500

!~

tive width W,~ is increasing with Vos, then it will extend from the intrinsic region into the edge regions Bw shown in Fig. 1. In the edge region the threshold voltage is a function of distance outwards from the boundaries between the intrinsic region and the edge regions, because in the edge region: (a) the thickness of field oxide is increasing; and (b) the doping density is increasing owing to the channel-stop field implant region. Therefore, the negative conductance is required to compensate for the increase in the device's conductance which is not in proportion in the increase in effective channel width. Compared with standard I D s - V o s equation used in most parameter extraction techniques, only one more term, GpVDs, is added in eqn (1). A complete explanation of the physical origin of the negative parallel parasitic conductance (Gp) and both Ge and the effective channel width W~ variation with effective gate bias is beyond the scope of this paper, and will be presented at a later date.

*

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REFERENCES

R= o °'°Z~1 0.5

Mask

1.0

Oato

1.5

Longth

2.0

2.5

3.0

L m (pro)

Fig. 7. Conventional technique for extracting AL and Re from a group of varying channel length devices having a common width, but different mask lengths. The effective gate biases are as described in the graph.

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1386

Z.P. Zuo and M. J.

5. K. L, Peng, S. Y. Oh, M. A. Afromowitz and J. L. Moll, IEEE Electron Device Lett. EDL-5, 473 (1984). 6. D. J. Mountain, IEEE Trans. Electron Devices ED-36, 2499 (1989). 7. Z. P. Zuo, M. J. Deen and J. Wang, Conad/an Conf. on Electrical and Computer Engineering, p. 1038, Montreal, Quebec (1989).

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