On the DC extraction of the asymmetric parasitic source and drain resistances for MOSFETs

Journal Pre-proofs On the DC extraction of the asymmetric parasitic source and drain resistances for MOSFETs Rodolfo Rodriguez-Davila, Adelmo Ortiz-Conde, Carlos Avila-Avendano, Zeshaan Shamsi, Manuel A. Quevedo-Lopez PII: DOI: Reference:

S0038-1101(19)30536-2 https://doi.org/10.1016/j.sse.2019.107700 SSE 107700

To appear in:

Solid-State Electronics

Received Date: Revised Date: Accepted Date:

24 August 2019 29 October 2019 1 November 2019

Please cite this article as: Rodriguez-Davila, R., Ortiz-Conde, A., Avila-Avendano, C., Shamsi, Z., Quevedo-Lopez, M.A., On the DC extraction of the asymmetric parasitic source and drain resistances for MOSFETs, Solid-State Electronics (2019), doi: https://doi.org/10.1016/j.sse.2019.107700

This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

© 2019 Published by Elsevier Ltd.

On the DC extraction of the asymmetric parasitic source and drain resistances for MOSFETs Rodolfo Rodriguez-Davila1, Adelmo Ortiz-Conde2*, Carlos Avila-Avendano1, Zeshaan Shamsi1 and Manuel A. Quevedo-Lopez1 1Materials

Science and Engineering Department, University of Texas at Dallas, Richardson, TX 75080, USA.

Solid State Electronics Laboratory, Universidad Simón Bolívar, Caracas 1080, Venezuela.

2

Abstract –Two different parameter extraction methods are proposed in this article. First, a simple DC method is presented to extract the difference between the drain and source series resistance of MOSFETs. This method is valid for any threeor four-terminal MOSFET and it can be used in linear, triode or saturation region. Second, an integration-based method is proposed to extract the drain resistance and the source resistance of thin-film MOSFETs. Both methods were tested using simulated and measured data of two different devices: zinc oxide (ZnO) and polysilicon TFTs. Keywords: MOSFET, thin-Film transistors, parameter extraction, asymmetric parasitic drain and source series resistance,

threshold voltage, mobility enhancement factor. 1. INTRODUCTION Possible unintentional asymmetry between drain and source is an important aspect to be taken into consideration in modern devices [1-6]. Various AC methods [7-11], two capacitance–voltage methods [12,13] and numerous DC methods [14-19] have been proposed to extract this asymmetry. Even a sophisticated technique based in scanning Kelvin probe microscopy was also presented [20]. One of these interesting DC methods is based on the asymmetry of the current-voltage characteristics of the parasitic sourceand drain-body junctions [17,18]. Other DC method is based on the parasitic bipolar source-body-drain [19]. The use of additional external resistances has also been proposed [14,15]. A numerical solution of a system of four DC current and conductance equations was also proposed to extract this asymmetry [16]. It is generally accepted that the observed unintentional asymmetry between MOSFET source and drain resistance values results mainly from different drain and source contact resistances [21]. As far as we know, the first two different and equivalent methods [22-26] were proposed in the nineties to extract this asymmetry in the four terminal MOSFET. Up to now, all the published methods require the body contact in order to account for the small variation in threshold voltage between the normal and inverse mode of operation. Since the thin-film transistors (TFTs) are three-terminal devices, the previous methods cannot be used unless the threshold voltage variation is neglected. In Section 2, we generalize the previous DC method to extract the difference between the drain and source series resistance of MOSFETs [22,23], in order to apply it to the three-terminal TFTs. In contrast, the previous method [23] requires the body terminal in order to evaluate the variation of threshold voltage with respect to the body-source voltage. It is important to point out that this new method can also be used with any four-terminal MOSFET and it is based only on the assumption that the device asymmetry is in the parasitic resistances. We recently proposed an integration-based method [27] that allows to extract the source series resistance, the threshold voltage and the mobility enhancement factor of TFTs in the normal mode of operation. In Section 3, we propose to use this integrationbased method [27] in the inverse mode of operation, in order to extract the drain resistance, the threshold voltage and the mobility enhancement factor. It is worth noting that this integration-based method allows to extract the asymmetry of the device in the intrinsic channel but it is only valid for TFTs in which the drain saturation current obeys a power-law-type dependence on gate bias. On the other hand, the method proposed in Section 2 to extract the difference between the drain and source series resistance is valid for any MOSFET model in which the intrinsic channel is symmetric. In Sections 4 and 5, we test our two proposed methods using simulations and experimental data of zinc oxide (ZnO) and polysilicon TFTs. 2. EXTRACTION OF THE DIFFERENCE BETWEEN DRAIN AND SOURCE RESISTANCES FOR MOSFETs

*Corresponding author. E-mail addresses: [email protected] (R. Rodriguez-Davila), [email protected] (A. Ortiz-Conde), [email protected] (Carlos AvilaAvendano), [email protected] (Z. Shamsi), and [email protected] (M. A. Quevedo-Lopez).

Fig. 1 illustrates a TFT in the normal mode of operation with the source grounded as well as in the inverse mode operation with the drain grounded. The drain current IDn, in the normal mode of operation, is given by: I Dn = f Vgs  VTn ,Vds , (1)





where f is a general function defined by a particular MOSFET model, subscript n indicates normal mode operation, VTn is the threshold voltage in the normal mode, Vgs  VGn  I Dn RS and

(2)

Vds  VDn   RS  RD  I Dn

VDi

VDn IDn

+

IDi

RD

VRD

RS

+ VRS -

-

VGn

+ Vgs RS

+ Vds -

(3)

+ VRS

VGi

+ Vgd RD

-

+ Vsd -

+ VRD -

Fig. 1. A three-terminal thin-film transistor connected in the normal (source grounded) and inverse (drain grounded) modes of operation.

where VGn and VDn are the externally applied gate and drain voltage in the normal mode, RD and RS are the drain and source resistances. Likewise, the drain current IDi in the inverse mode is given by:

I Di = f Vgd  VTi ,Vsd 

and

,

(4)

Vgd  VGi  I D RD

(5)

Vsd  VSi   RS  RD  I D

(6)

where VGi and VSi are the externally applied gate and drain voltage in the inverse mode. The subscripts “n” and “i” stands for normal and inverse mode of operation. It is important to point out that the assumption that the general function f is the same in both mode of operations implies that the intrinsic device is symmetric and that the asymmetry is in the parasitic resistances and the threshold voltage. If the device is biased with VDn =VSi and VGi is adjusted such that IDn=IDi=ID, then (3) and (6) implies that Vds=Vsd. This result in combination with (1) and (4) yields Vgs  VTn =Vgd  VTi . (7) Substituting (2) and (5) into (7) and solving for (RD-RS):

 RD  RS   R =

VG  VT

(8)

ID

where VT  VTi  VTn and VG  VGi  VGn . Equation (8) can be rewritten as:

VG   R I D  VT

.

(9)

Then, according to (9) a plot of VG as a function of ID should produce a straight line with slope of  R and ordinates axis intercept of VT . An alternative graphical method consists in plotting (RD-RS) versus ID, using equation (8), with various different values of VT. We will recognize the correct value of VT because it will yield a nearly constant value of (RD-RS) with respect to ID. It is worth noticing that equation (8) is valid for any general three- or four-terminal MOSFET and that device can be biased in linear, triode or saturation region as long as VDn=VSi and IDn=IDi =ID. In contrast, the previous method [23] can only be used in a four-terminal MOSFET because it requires to measure the threshold voltage variation with respect to the source-body voltage.

We do not recommend that the required condition IDn=IDi=ID be measured using a current source or adjusting the gate voltage manually. Instead, we propose to measure the transfer characteristic in the normal and inverse mode, using a small increment of gate bias. Then, for a given drain current, the corresponding gate voltage is determined using linear extrapolation. A linear extrapolation procedure yields small errors because the extraction of (RD-RS) is done for strong conduction, where the drain current is approximately linear, and also because the increment in the gate bias is small. 3. EXTRACTION OF SOURCE AND DRAIN RESISTANCES FOR TFTs We recently proposed a method [27] to extract the source series resistance (RS), the threshold voltage (VTn) and the mobility enhancement factor (mn) of thin-film MOSFETs biased in the normal mode of operation. Now, we propose to bias the device in the inverse mode of operation and to use our previous method [27] in order to obtain the drain series resistance (RD), the threshold voltage (VTi) and the mobility enhancement factor (mi). For convenience, the procedure to obtain mn, mi, RS, RD, VTn and VTi is briefly summarized as follow. First, the saturation transfer characteristics are measured in the normal and inverse modes (IDsatn and IDsati respectively). Second, the corresponding H functions are numerically calculated using: VGn

Hn 

I

Dsatn

dVGn

0

(10)

I Dsatn

and VGi

Hi  Third, a fitting for Hn, in strong conduction, is done using the following equation [27]

Hn 

I

Dsati

dVGi

0

.

I Dsati

RS I Dsatn  mn  1 2  mn  1



VGn  VTn   mn  1

(11)

(12)

which allow us to extract mn, RS and VTn. Fourth, a fitting for Hi, in strong conduction, is done using the following equation R I  m  1 VGi  VTi   H i  D Dsati i (13) 2  mi  1  mi  1 in order to extract mi, RD and VTi . The present procedure allows the extraction of the possible asymmetry that could be present due to series resistance, threshold voltage and mobility enhancement factor for TFTs. The method presented in this section is based on assuming that saturation drain current obeys a perfect m power-law-type dependence on gate bias [27]. 4. PARAMETER EXTRACTION FROM SIMULATIONS We simulated an amorphous IGZO TFTs using AIM-SPICE [28] with RD=10 K RS=11 K and two different zero-bias threshold voltage: VTOn=0.7 V and VTOi=0.9 V for normal and inverse mode of operations respectively. The remaining parameters are presented in [27]. Fig. 2 illustrates on the left side the simulated saturation transfer characteristics in both modes of operation and on the top right side the corresponding difference between the inverse and the normal mode gate voltages versus drain current. This figure also illustrates the fitted straight line using (9) with a slope of R=-1 K and ordinates axis intercept of VT=0.2 V. The bottom right side of figure 2 presents (RD-RS) versus the drain current using equation (8) for various values of VT. The correct value of VT is the one that yields a nearly constant value of (RD-RS) with respect to ID. The present methods yield the extracted values of (RD-RS)=-1 K and VT=0.2 V which exactly coincide with the simulated values

10-3

140 AIM-SPICE level=15 VTOn = 0.7 V , VTOn = 0.9 V

100

IDn , IDi ( A )

IDn , IDi ( A )

0.15

RS = 11 K

10-6

80 Normal mode Inverse mode

10-7

40

10-9

20 VDn =VDi =30 V 0

5

10

15

20

25

0 30

 R = -1 K  VT = 0.2 V

0.10 0.05 2

60

10-8

10-10

 VG ( V )

RD = 10 K

10-5

Simulations Fitted:  VG = R ID + VT

0.20

120

RD - RS ( K )

10-4

RD - RS = -1 K

1

 VT = 0.20 V

0 -1 -2

 VT = 0.18 to 0.22

-3 -4

VGn , VGi ( V )

step 0.01 V 0

20

40

60

80 100 120 140

ID ( A )

Fig. 2 (Left pane) Simulated saturation transfer characteristic of amorphous IGZO thin-film transistors in normal and inverse modes of operation. (Top right pane) Corresponding difference between the inverse and the normal mode gate voltages versus drain current. The slope of the fitted straight line yields R = -1 K and the ordinates axis intercept gives VT =0.2 V. (Bottom right pane) Difference between drain and source resistances versus drain current for various VT. The correct value of VT=0.2V yields a constant value of (RD- RS)=-1K.

The left side of Fig. 3 presents a plot of the numerical calculation of the Hn function, defined in (10), and the corresponding fit with equation (12) which yields RS=15.3 K, VTn=0.48 V and mn=3.1. The right side of Fig. 3 shows the Hi function, defined in (11), and the corresponding fit with equation (13) which gives RD=14.3 K, VTi=0.69 V and mi=3.1. These extracted values yield (RD-RS)=-1 K and VT=0.2V which are in close agreement with the simulated values and the previously extracted values. We think that the extracted values of resistances are larger than the simulated values because AIM-SPICE accounts for second order effects and the analysis presented in section 3 is based on assuming that saturation drain current obeys a perfect m power-law-type dependence on gate bias. 8 AIM-SPICE Level=15 R D = 10 K

Hn , Hi ( A.V )

6

R S = 11 K VTOn = 0.7 V VTOi = 0.9 V

4

VDn = VDi =30 V

2

0

Normal mode Normal fit: R S = 15.3 K

Inverse mode Inverse fit: R D = 14.3 K

VTn = 0.48 V

VTi = 0.69 V m i = 3.10

m n = 3.10

0

5

10 15 20 VGn ( V )

25

30 0

5

10 15 20 VGi ( V )

25

30

Fig. 3 (Left pane) Plot of the H function in the normal mode versus the gate bias and the corresponding fit using equation (12). The symbols illustrate the numerical calculation of the H function using equation (10) to the simulated data. The solid line is the corresponding fitting. (Right pane) Plot of the H function in the inverse mode versus the gate bias and the corresponding fit using equation (13).

5. EXPERIMENTAL VALIDATION We have measured two different kinds of thin-film transistors (TFTs): polycrystalline ZnO and polysilicon. Measurements of normal and inverse transfer characteristics, with a 50 mV increment and VDS=6V, are presented in the left pane of Fig. 4 for a ZnO TFT. This device has a mask channel width of 160 m, a mask channel length of 80 m and a gate oxide thickness of 19 nm of aluminum oxide (Al2O3). Additional fabrication details of these devices are available in [29]. The values of the normal and the inverse drain current at VGS=6V are 42.4 A and 38.6 A respectively, which implies a 9 % difference. The top right side of this figure shows the corresponding difference between the inverse and the normal mode gate voltages versus drain current. This figure also illustrates the fitted straight line using (9) with a slope of R=-0.739 K and ordinates axis intercept of VT=0.186 V. The bottom right pane of Fig. 4 shows the evaluation of equation (8) for various possible values of VT. We observe that the correct value of VT =0.19 V yields a constant value of (RD-RS)=-0.9 K. We observe small differences in the extracted parameters between these two methods and this can be understood by noticing that the fitting of equation (8) is giving more importance to the low current level because there are more measured points in this region. On the other hand, the graphical method of equation (8) gives more importance to high current values. Fig. 5 presents plots of the numerical calculations of the normal and inverse H functions (Hn and Hi) and the corresponding fits with equation (12) and (13) respectively. The normal fit yields RS=7.8 K, VTn=0.74 V and mn=3.70 while the inverse fit gives RD=6.3 K, VTi=0.95 V and mi=3.65. These results imply VT =0.21 V, (RD-RS)=-1.5 K and m=(mi-mn)=0.05 which implies an

small asymmetry in the mobility enhancement factor. The values of VT =0.21 V and (RD-RS)=-1.5 K are reasonably close to the previous extracted values of VT =0.19 V and (RD - RS)=-0.9 K considering that the normal and inverse current presents a difference in the order of 9 % and that there is an small asymmetry in in the mobility enhancement factor. 10-4

0.19

10-5

40

Measurements Fitted:  VG = R ID + VT

 VG ( V )

ZnO W / L = 160 / 80 VDn =VDi = 6 V

0.18

0.17

IDn , IDi ( A )

30

10-7 Normal mode Inverse mode

10-8

10

10-10 10-11

0

1

2

3

4

VGn , VGi ( V )

0.15 2

20

10-9

5

6

0

 R = -0.739 K  VT = 0.186 V

0.16

RD - RS ( K )

IDn , IDi ( A )

10-6

RD - RS = -0.9 K

1

 VT = 0.19 V

0 -1 -2

 VT = 0.17 to 0.21

-3 -4

step 0.01 V 0

10

20

ID ( A )

30

40

Fig. 4 (Left pane) Measured saturation transfer characteristic of polycrystalline ZnO thin-film transistors, in the normal and inverse mode of operation, with a channel length of 80 m. (Top right pane) Corresponding difference between the inverse and the normal mode gate voltage versus drain current. The slope of the fitted straight line yields R = -0.739 K and the ordinates axis intercept gives VT =0.186 V. (Bottom right pane) Difference between drain and source resistances versus drain current for various VT. The correct value of VT=0.19V yields a constant value of (RD-RS)=0.9 K.

1.2 Inverse mode Inverse fit: R D = 6.3 K

Normal mode Normal fit: R S = 7.8 K

1.0

VTi = 0.95 V

Hn , Hi ( A.V )

VTn = 0.74 V

m i = 3.7

m n = 3.7

0.8 0.6 0.4 0.2 0.0

ZnO W / L = 160 / 80

0

1

2 3 4 VGn ( V )

5

6 0

1

2 3 4 VGi ( V )

5

6

Fig. 5 (Left pane) Plot of the H function in the normal mode versus the gate bias and the corresponding fit using equation (12). The symbols illustrate the numerical calculation of the H function using equation (10) and the measured data of a ZnO TFT. The solid line is the corresponding fit. (Right pane) Plot of the H function in the inverse mode versus the gate bias and the corresponding fit.

The left pane of Fig. 6 presents measured transfer characteristics for a ZnO TFT with a mask channel length of 10 m and the same remaining parameters of the previous figure. The top right side of this figure shows the corresponding difference between the inverse and the normal mode gate voltages versus drain current. This figure also illustrates the fitted straight line using (9) with a slope of R=-0.244 K and ordinates axis intercept of VT=0.15 V. The bottom right pane of Fig. 6 shows the evaluation of equation (8) for various possible values of VT. We observe that the correct value of VT =0.15 V yields a constant value of (RDRS)=-0.25 K.

10-3

350 300

0.12

IDn , IDi ( A )

250

10-6

200

10-7

Normal mode Inverse mode

10-8

100

10-10

50

10-11

0

2

1

0

4

3

VGn , VGi ( V )

0.10

6

5

 R = -0.244 K  VT = 0.15 V

0.08 0.06

150

10-9

Measurements Fitted:  VG = R ID + VT

0.14

RD - RS ( K )

IDn , IDi ( A )

10-5

0.16

 VG ( V )

ZnO W / L = 160 / 10 VDn =VDi = 6 V

10-4

0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0

RD - RS = -0.25 K

 VT = 0.15 V

 VT = 0.13 to 0.17 step 0.01 V 0

50 100 150 200 250 300 350

ID ( A )

Fig. 6 (Left pane) Measured saturation transfer characteristic of polycrystalline ZnO thin-film transistors, in the normal and inverse mode of operation, with a mask channel length of 10 m. (Top right pane) Corresponding difference between the inverse and the normal mode gate voltage versus drain current. The slope of the fitted straight line yields R = -0.244 K and the ordinates axis intercept gives VT =0.15 V. (Bottom right pane) Difference between drain and source resistances versus drain current for various VT. The correct value of VT=0.15V yields a constant value of (RD-RS)=-0.25 K.

Fig. 7 illustrates numerical calculations of the normal and inverse H functions (Hn and Hi) and the corresponding fits with equation (12) and (13) respectively. The normal fit yields RS=0.9 K, VTn=0.70 V and mn=3.2 while the inverse fit gives RD=0.73 K, VTi=0.89 V and mi=3.2. These results imply VT =0.19 V, (RD-RS)=-0.17 K and m=0. The values of VT =0.19 V and (RDRS)=-0.17 K are reasonably close to the previous extracted values of VT =0.15 V and (RD-RS)=-0.25 K. Comparing the results of this figure with that of Fig. 5, we conclude that the mobility enhancement factor changes from 3.7 to 3.2 as the channel length decreases from 80 m to 10 m. On the other hand, the threshold voltage presents a very small variation while the parasitic resistances decrease as the channel length decreases. We are studying this last dependence and we are evaluating the possibility that this could be due to a physical limitation of the power-law model used for the ZnO TFTs. 1.2 Inverse mode Inverse fit: R D = 0.73 K

Normal mode Normal fit: R S = 0.90 K

1.0

VTi = 0.89 V

Hn , Hi ( A.V )

VTn = 0.70 V

m i = 3.2

m n = 3.2

0.8 0.6 0.4

ZnO

0.2 0.0

W / L = 160 / 10 VDn =VDi = 6 V

0

1

2 3 4 VGn ( V )

5

6 0

1

2 3 4 VGi ( V )

5

6

Fig. 7 (Left pane) Plot of the H function in the normal mode versus the gate bias and the corresponding fit using equation (12). The symbols illustrate the numerical calculation of the H function using equation (10) and the measured data of a ZnO TFT with a mask channel length of 10 m. The solid line is the corresponding fit. (Right pane) Plot of the H function in the inverse mode versus the gate bias and the corresponding fit.

Experimental saturation transfer characteristics in normal and inverse modes are presented in the left pane of Fig. 8 for polysilicon TFTs with a channel length of 5 m, a channel width of 10 m, and a gate oxide thickness of 55 nm. Additional details on the fabrication process of these devices were reported in [30]. The values of the normal and inverse saturation drain current at VGS=12 V are 143.5 A and 142.0 A respectively, which implies only a 1 % difference. The top right side of this figure shows the corresponding difference between the inverse and the normal mode gate voltages versus drain current. This figure also illustrates the fitted straight line using (9) with a slope of R=-56  and ordinates axis intercept of VT=42 mV. The bottom right pane of Fig. 8 shows the results of equation (8) which yield VT =0.19 V and (RD-RS)=-0.9 K . We conclude that the asymmetry in this device is so small that the results of both methods are not very accurate.

10-3

50 140

W / L = 10 / 5

10-5

VDn = VGn

120

VDi = VGi

45 40 35

80

Normal mode Inverse mode

10-8 10-9

60 40

10-10

20

10-11 10-12

0

2

4

6

8

VGn , VGi ( V )

10

0 12

IDn , IDi ( A )

10-7

Measurements Fitted:

30

100

 VG = R ID + VT

25 20 1.0

RD - RS ( K )

IDn , IDi ( A )

10-6

 R = -56   VT = 42 mV

 VG ( mV )

Polysilicon 10-4

RD - RS = -0.1 K

 VT = 0.04 V

0.5 0.0

 VT = 0.02 to 0.06

-0.5 -1.0

step 0.01 V 0

20

40

60

80 100 120 140

ID ( A )

Fig. 8 (Left pane) Measured saturation transfer characteristic of polycrystalline ZnO thin-film transistors, in the normal and inverse mode of operation, with a mask channel length of 10 m. (Top right pane) Corresponding difference between the inverse and the normal mode gate voltage versus drain current. The slope of the fitted straight line yields R = -56  and the ordinates axis intercept gives VT =42 mV. (Bottom right pane) Difference between drain and source resistances versus drain current for various VT. The correct value of VT=0.04V yields a constant value of (RD-RS)=-0.1 K.

Fig. 9 shows plots of the numerical calculations of the H function in the normal (Hn) and inverse (Hi) modes and the corresponding fits with equation (12) and (13) respectively. The normal fit yields RS=4.6 K, VTn=2.55 V and mn=3.75 while the inverse fit gives RD=4.4 K, VTi=2.59 V and mi=3.73. These results imply VT =0.04 V, (RD-RS)=-0.2 K and m=(mi-mn)=-0.02 which implies an small asymmetry in the mobility enhancement factor. The values of VT =0.04 V and (RD - RS)=-0.2 K are reasonably close to the previous extracted values of VT =0.04 V and (RD - RS)=-0.1 K considering that the values of current in the normal and inverse modes presents only a difference in the order of 1 %. Finally, we would like to point out that the polysilicon TFTs are more symmetrical than the polycrystalline ZnO devices because of the fabrication processes. The Gate/Source and Gate/Drain distances in the ZnO devices are dependent on the alignment during photolithography while the polysilicon transistors are fabricated using a self-aligned process.

Inverse mode Inverse fit: R D = 4.4 K

Normal mode Normal fit: R S = 4.6 K

2.0

VTi = 2.59 V

Hn , Hi ( A.V )

VTn = 2.55 V

m i = 3.73

m n = 3.75

1.5

1.0 Polysilicon

0.5

0.0

W / L = 10 / 5 VDn = VGn VDi = VGi

0

2

4 6 8 VGn ( V )

10

12 0

2

4 6 8 VGi ( V )

10

12

Fig. 9 (Left pane) Plot of the H function in the normal mode versus the gate bias and the corresponding fit using equation (12). The symbols illustrate the numerical calculation of the H function using equation (10) and the measured data of a polysilicon TFT. The solid line is the corresponding fit. (Right pane) Plot of the H function versus the gate bias in the inverse mode and the corresponding fit.

6. CONCLUSION We have presented two parameter extraction methods. First, a simple method to extract the difference between drain and source series resistance for three- and four-terminal MOSFETs and thin-film transistors. Second, by using the saturation transfer characteristics of TFTs in the inverse and normal modes, we have presented an integration-based method to extract the asymmetry in the drain and source series resistance, the threshold voltage and the mobility enhancement factor. Both methods have been tested using simulated data and experimental data of two different TFTs: zinc oxide (ZnO) and polysilicon. References

[1]

N. Li, W. Deng, X. Wei, W. Wu, J. Huang, “Extraction of Contact Resistance and DC Modelling in Metal Oxide TFTs,” IEEE Journal of the Electron Dev. Soc., vol. 7, pp. 127-133, March 2019. DOI: 10.1109/jeds.2018.2885136 [2] G. Kim et al., “Highly Biased Linear Condition Method for Separately Extracting Source and Drain Resistance in MOSFETs,” IEEE Trans. Electron Devices, vol. 65, no. 2, pp. 419–423, Feb. 2018. DOI: 10.1109/TED.2017.2783924 [3] J. Kim et al., “Comprehensive separate extraction of parasitic resistances in MOSFETs considering the gate bias-dependence and the asymmetric overlap length”, Microelectronics Reliability, vol. 85, pp. 66–70, 2018. DOI: 10.1016/j.microrel.2018.04.011 [4] P. Oldiges, C. Zhang, X. Miao, M. G. Kang, T. Yamashita, , “Technique for Asymmetric Source/Drain Resistance Extraction on a Single Gate Length MOSFET”, Int. Conf. Simulation of Sem. Processes and Dev. (SISPAD), 2018. DOI: 10.1109/sispad.2018.8551676 [5] S. Jun et al., “Dual-sweep combinational transconductance technique for separate extraction of parasitic resistances in amorphous thin-film transistors,” IEEE Electron Device Lett., vol. 36, no. 2, pp. 144–146, Feb. 2015. DOI: 10.1109/LED.2014.2384504 [6] D. Tomaszewski et al., “A simple method for characterization of MOSFET serial resistance asymmetry,” in Proc. IEEE Int. Conf. Microelectron. Test Struct., Mar. 2015, pp. 116–121. DOI: 10.1109/ICMTS.2015.7106120 [7] D. Lovelace, J. Costa, N. Camilleri, “Extracting small-signal model parameters of silicon MOSFET transistors”, IEEE MTT-Symposium, pp. 865-868, 1994. DOI: 10.1109/MWSYM.1994.335220 [8] A. Bracale et al., “A new approach for SOI devices small-signal parameters extraction”, Analog Integrated Circuits and Signal Processing, pp. 157-169, 2000. DOI: 10.1023/A:1008332732738 [9] R. Torres-Torres, R.S. Murphy-Arteaga, S. Decoutere, “MOSFET bias dependent series resistance extraction from RF measurements”, Electronics Letters, vol. 39, No. 20, pp. 1476-1478, 2003. DOI: 10.1049/el:20030936 [10] J.C. Tinoco, J.-P. Raskin, “New RF extrinsic resistances extraction procedure for deep-submicron MOS transistors”, international Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol. 23, Issue 2, pp. 107-126, March 2010. DOI: 10.1002/jnm.726 [11] P. Yu, Y. Zhou, L. Sun, J. Gao, “A novel approach to extracting extrinsic resistances for equivalent circuit model of nanoscale MOSFET”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 29, 6, pp. 1044-1054, Nov. 2016. DOI: 10.1002/jnm.2163 [12] H. Bae et al., “Extraction of Separated Source and Drain Resistances in Amorphous Indium–Gallium–Zinc Oxide TFTs Through C–V Characterization,” IEEE Electron Device Letters, vol. 32, 6, pp. 761-763, 2011. DOI: 10.1109/LED.2011.2127438 [13] H. Bae et al., “A Separate Extraction Method for Asymmetric Source and Drain Resistances Using Frequency-DispersiveC–VCharacteristics in Exfoliated MoS2FET", IEEE Electron Device Letters, vol. 37, 2, pp. 231-233, 2016. DOI: 10.1109/LED.2015.2509473 [14] G. M. Lim, Y. C. Kim, Y. W. Park, D. J. Kim, D. M. Kim, “Additional resistance method for extraction of separated nonlinear parasitic resistances and effective mobility in MOSFETs,” Electron. Lett., vol. 36, pp. 1233–1234, 2000. DOI: 10.1049/el:20000810 [15] D. M. Kim, H. C. Kim, H. T. Kim, “Modeling and extraction of gate bias-dependent parasitic source and drain resistances in MOSFETs,” Solid-State Electron, vol. 47, pp.1707-1712, 2003. DOI: 10.1016/S0038-1101(03)00134-5 [16] M. Joodaki, “An extended drain current conductance extractionmethod and its application to DRAM support and array devices,” Solid State Electron., vol. 53, pp. 1020–1031, 2009. DOI: 10.1016/j.sse.2009.04.039 [17] H. Bae et al., “Separate Extraction of Source, Drain, and Substrate Resistances in MOSFETs With Parasitic Junction Current Method,” IEEE Electron Dev. Lett., vol. 31, pp. 1190-1192, 2010. DOI: 10.1109/LED.2010.2066257 [18] H. Bae et al., “Modeling and Separate Extraction of Gate-Bias- and Channel-Length-Dependent Intrinsic and Extrinsic Source–Drain Resistances in MOSFETs,” IEEE Electron Dev. Lett., vol. 32, pp. 722-724, 2011. DOI: 10.1109/LED.2011.2131116 [19] J. Kim et al., “Hybrid Open Drain Method and Fully Current-Based Characterization of Asymmetric Resistance Components in a Single MOSFET,” IEEE Trans. Electron Dev., vol. 63, pp. 4196-4200, 2016. DOI: 10.1109/TED.2016.2607721 [20] C.-F. Wu et al., “Contact resistance asymmetry of amorphous indium–gallium–zinc–oxide thin-film transistors by scanning Kelvin probe microscopy,” Chinese Physics B, vol. 25, 5, 057306, 2016. DOI: 10.1088/1674-1056/25/5/057306 [21] A. Ortiz-Conde et al., “A review of DC extraction methods for MOSFET series resistance and mobility degradation model parameters”, Microelectron. Reliab., vol. 69, pp. 1-16, Feb. 2017. DOI: 10.1016/j.microrel.2016.12.016 [22] A. Ortiz-Conde, J.J. Liou, W. Wong, F.J. García-Sánchez, “A simple method to extract the difference of the drain and source series resistances in MOSFETs,” Electron. Lett., vol. 30, pp. 1013–1015, 1994. DOI: 10.1049/el:19940681 [23] A. Ortiz-Conde, F.J. García-Sánchez, J.J. Liou, “An improved method for extracting the difference between drain and source resistances in MOSFETs,” Solid State Electron., vol. 39, pp. 419–421, 1996. DOI: 10.1016/0038-1101(95)00072-0 [24] A. Raychaudhuri, M.J. Deen, M.I.H. King, J. Kolk, “A simple method to extract the parasitic resistances from a single MOSFET using measurements of small-signal conductances,” Proc. 25th Europ. Solid State Dev. Research Conf. ESSDERC, pp. 749–752, 1995. [25] A. Raychaudhuri, M.J. Deen, M.I.H. King, J. Kolk, A simple method to extract the asymmetry in parasitic source and drain resistances from measurements on a MOS transistor, IEEE Trans. Electron Dev., vol. 42, pp. 1388–1390, 1995. DOI: 10.1109/16.391229 . [26] A. Raychaudhuri, M. J. Deen, M. I. H. King, and J. Kolk, “Finding the asymmetric parasitic source and drain resistances from the AC conductances of a single MOS transistor,” Solid-State Electron., vol. 39, no. 6, pp. 909–913, 1996. DOI: 10.1016/0038-1101(95)00269-3 [27] R. Rodriguez-Davila, A. Ortiz-Conde, C. Avila-Avendano, M. A. Quevedo-Lopez, “A new integration-based procedure to extract the threshold voltage, the mobility enhancement factor and the series resistance of thin-film MOSFETs,” IEEE Trans. Electron Dev., vol. 66, no. 7, pp. 2979- 2985, July 2019. DOI: 10.1109/TED.2019.2913699 [28] K. Lee, M. Shur, T. A. Fjeldly, and T. Ytterdal, Semiconductor Device Modeling for VLSI, Prentice-Hall, Englewood Cliffs, NJ, 1993. [29] R. A. Rodriguez-Davila, I. Mejia, M. Quevedo-Lopez, C. D. Young, “Hot Carrier Stress Investigation of Zinc Oxide Thin Film Transistors with an Al2O3 Gate Dielectric,” IEEE Int. Symp. Physical and Failure Analysis of Integrated Circuits (IPFA), July 2018. DOI: 10.1109/ipfa.2018.8452171 [30] C. Avila-Avendano et al., “Integrated Thin-Film Radiation Detectors and In-Pixel Amplification,” IEEE Trans. Electron Dev., vol. 65, pp. 3809-3815, Sept. 2018. DOI: 10.1109/TED.2018.2859778