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Performance enhancement in InZnO thin-film transistors with compounded ZrO2–Al2O3 nanolaminate as gate insulators
Ceramics International 42 (2016) 8115–8119
Contents lists available at ScienceDirect
Ceramics International journal homepage: www.elsevier.com/locate/ceramint
Performance enhancement in InZnO thin-film transistors with compounded ZrO2–Al2O3 nanolaminate as gate insulators Jianhua Zhang a,n, Xingwei Ding a,1, Jun Li b, Hao Zhang a, Xueyin Jiang b, Zhilin Zhang a,b a b
Key Laboratory of Advanced Display and System Application, Ministry of Education, Shanghai University, Shanghai 200072, China Department of Materials Science, Shanghai University, Shanghai 200072, China
art ic l e i nf o
a b s t r a c t
Article history: Received 9 January 2016 Accepted 2 February 2016 Available online 6 February 2016
We fabricated compounded ZrO2–Al2O3 nanolaminate dielectrics by the atomic layer deposition (ALD) and used them to successfully integrate the high-performance InZnO (IZO) thin-film transistors (TFTs). It is found that nanolaminate dielectrics combine the advantages of constituent dielectrics and produce TFTs with improved performance and stability compared to single-layer gate insulators. The mobility in IZO-TFT was enhanced about 22% by using ZrO2–Al2O3 gate insulators and the stability was also improved. The transfer characteristics of IZO-TFTs at different temperatures were also investigated and temperature stability enhancement was observed for the TFT with ZrO2–Al2O3 nanolaminates as gate insulators. A larger falling rate (∼1.45 eV/V), a lower activation energy (Ea, ∼1.38 eV) and a smaller density-of-states (DOS) were obtained based on the temperature-dependent transfer curves. The results showed that temperature stability enhancement in InZnO thin-film transistors with ZrO2–Al2O3 nanolaminate as gate insulators was attributed to the smaller DOS. & 2016 Elsevier Ltd and Techna Group S.r.l. All rights reserved.
Keywords: B. Interfaces Thin-film transistors Electronic materials Compounded dielectrics Density-of-states
1. Introduction Thin film transistors (TFTs) fabricated by using amorphous oxide semiconductors have received considerable attention and attracted increasing research interest owing to their potential application in active-matrix flat-panel displays (AMFPD) [1–3]. Both the channel layer and gate insulators play a crucial role in TFT performance. In order to obtain TFTs with better performance, many groups have paid attention to optimization of the channel layer fabrication process [4–7]. However, few effort has been made to investigate the effect of gate insulator fabrication parameters on the TFT performance. Among the gate insulators investigated to date, ZrO2 has been considered as a possible alternative because of its high dielectric constant and reasonable bandgap [8]. However, ZrO2 tends to crystallize easily [9]. As a result, crystalline gate dielectrics may have problems such as large current leakage (as grain boundaries serve as high-leakage paths) and surface roughness which leads to reduction of the mobility and the stability [10–12]. In comparison, Al2O3 films synthesized have been reported to remain amorphous up to 1000 °C. Hence, the novel ZrO2-Al2O3 nanolaminate dielectrics has a mixture structure of crystalline phase ZrO2 and amorphous phase Al2O3 in order to n
Corresponding author. E-mail addresses: [email protected], [email protected] (J. Zhang). 1 Contributed equally to this work.
http://dx.doi.org/10.1016/j.ceramint.2016.02.014 0272-8842/& 2016 Elsevier Ltd and Techna Group S.r.l. All rights reserved.
coordinate the tradeoff between capacitance and leakage current performances of a capacitor. Atomic layer deposition (ALD) is a highly conformal and uniform technique with inherent atomic-scale control of thin film composition, making it ideally suited for deposition of nanolaminates [13–15]. In this paper, with a goal of obtaining the TFT with high mobility and high stability, a nanolaminates film consisting of with a novel structure (200 nm) overlaid with ZrO2 (about 10 nm) and Al2O3 (about 10 nm) alternately, instead of a single layer, was used as the gate insulator. As comparison, the TFTs with single ZrO2 (200 nm) and Al2O3 (200 nm) as gate insulator were also prepared. However, the TFT with 200 nm ZrO2 insulator failed to show suitable transistor characteristics due to poor leakage properties. The IZO-TFT with Al2O3 (200 nm) as gate insulator was named ‘device A’, while the IZO-TFT with ZrO2–Al2O3 nanolaminates (total 200 nm) as gate insulator was named ‘device B’.
2. Experiments A schematic cross section of the staggered, bottom-gate IZOTFTs used in this study is shown in Fig. 1. A heavily-doped n-Si substrate served as a bottom-gate contact. n-Si coupons were cleaned with consecutive rinses of acetone, isopropyl alcohol, and de-ionized water, followed by dehydration in an oven for 30 min. Immediately following this procedure, the ZrO2 and Al2O3 films were deposited via ALD technique at 250 °C.
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Fig. 1. Schematic structure of the IZO-TFTs.
Fig. 2. XRD pattern of ZrO2 film (total 200 nm) and ZrO2–Al2O3 nanolaminates (total 200 nm).
Tetrakis dimethyl amino zirconium (TDMAZr) as zirconium source and water (H2O) as oxygen source were used to form ZrO2 films. The TDMAZr bubbler was heated at 60 °C. Al2O3 was deposited by using alternating exposures of Al(CH3)3 and H2O vapor. Al(CH3)3 and H2O were used as the sources of Al and O, respectively. Following deposition of the gate insulator, an IZO films with an thickness of approximately 20 nm were deposited by rf-magnetron sputtering at room temperature using an IZO target (99.99%, In2O3:ZnO¼1:1 mol%) with a power density of 1 W/cm2 and gas mixing ratio of Ar:O2 (30:1). Chamber pressure before sputtering was 5 10-4 Pa, and total pressure was 0.5 Pa. Prior to channel layer deposition, the target was pre-sputtered in pure Ar gas for 10 min to remove the natural surface oxide layer of the target. After deposition of IZO layer, about 200 nm Al was deposited by thermal evaporation to form the source and drain electrodes through a shadow-mask with the channel width (W) of 1000 mm and channel length (L) of 50 mm. Thermal annealing was carried out at 300 °C for 35 min in atmosphere. The thickness of the film was measured by the alpha step (Dektak 3st). The electrical characteristics of IZO-TFTs were measured by Agilent E3647A Dual output DC power supply and Keithley 6485 Picoammeter and related software. The capacitance characteristics were measured by Agilent E4980A LRC meter. The structural property of the films was determined using X-ray diffraction measurements with Cu–Kα radiation (D/MAX) and high-resolution transmission electron microscopy (HRTEM, FEI Tecnai™ G2 F 20).
3. Results and discussion Nearly all metal oxides of interest, with the exception of Al2O3, will form a polycrystalline film either during deposition or upon modest thermal treatments: HfO2 and ZrO2 are no exceptions. Fig. 2 shows the XRD pattern of ZrO2 film and ZrO2–Al2O3 nanolaminates. The ZrO2 (110) peak appearing at 35.2° indicates that
Fig. 3. Cross-sectional TEM images of ZrO2–Al2O3 nanolaminates at (a) low resolution and (b) high resolution.
the ZrO2 film is polycrystalline. The disadvantages of polycrystalline film are discussed in the introduction parts. The peak for ZrO2–Al2O3 nanolaminates is quite wide and of low intensity, suggesting that very small grains are locally embedded in the amorphous structure. We can conclude that inserting amorphous Al2O3 film is an effect way to suppress the crystalline of ZrO2. In our previous work, we have found that the IGZO-TFT with ALD-Al2O3 as gate insulator shows an amorphous phase with a very smooth interface between IGZO and Al2O3 [16]. So in recent experiment, the TEM was applied only to device B to evaluate its microstructure and interfacial layer properties, and results are displayed in Fig. 3. The ZrO2–Al2O3 nanolaminates show a mixed amorphous Al2O3 and poorly crystallized ZrO2 structure. The ZrO2 shows a poorly crystallized structure due to the fact that addition of Al2O3 into ZrO2 matrix affects nucleation and growth of ZrO2 grains from the composite matrix, so mixing of Al2O3 with ZrO2 is an effect way to suppress the crystallization. These results are consistent with our XRD results. As shown in Fig. 3. Another observation is that interface between Al2O3 and IZO is very smooth which is in favor of the carriers transportation. Fig. 4 shows the output characteristics of devices at applied gate voltage (VGS)¼10 V and source to drain voltage (VDS)¼ 10 V. The output current (IDS) is 3.9 10 4 A for device A while the value for device B is 5.8 10 4 A. The lack of current crowding at low source-drain biases indicates a good Ohmic contact at the Al/ IZO interface. Furthermore, this TFT operates as an n-channel,
J. Zhang et al. / Ceramics International 42 (2016) 8115–8119
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Fig. 5. Corresponding transfer characteristic IDS versus VGS at a fixed VDS 10 V and the IDS1/2–VGS curves of devices.
density of surface states at the channel-insulator interface as:
⎡ SSLog(e) ⎤C − 1⎥ i Nit = ⎢ ⎣ (kT /q) ⎦q
Fig. 4. Output characteristics of the IZO-TFTs.
enhancement-mode device. In addition, there is good saturation at high drain biases, indicating depletion of the entire thickness of the IZO layer of free electrons. Fig. 5 shows corresponding transfer characteristic IDS versus VGS at a fixed VDS ¼10 V and the IDS1/2–VGS curves of devices. The on/off ratios were measured at approximately 7 106 and 8 107 for device A and B, respectively. This shows that the devices have good characteristics as the backplane of OLEDs requiring a relatively high on-current and small off-current for a rapid response and low power consumption. The improvement in on/off ratio of device B is attributed to the decrease in offcurrent. From the IDS1/2–VGS curves shown in Fig. 4, field-effect mobility (m) and threshold voltage (VTH) can be extracted according to the following expression:
IDS =
CiμW (VGS − VTH)2 2L
(for VDS > VGS − VTH)
(1)
where Ci is the capacitance per unit area of the insulator layer (Ci for device A and B are 34 and 47.8 nF/cm2, respectively). W and L are the channel width and length, respectively, and VDS and VGS are the drainsource voltage and gate-source voltage. The field-effect mobility was obtained at 11.7 and 14.3 cm2/V s, whereas threshold voltage VTH was found 0.54 and 0.15 V for device A and B, respectively. Another figure of merit for evaluation of TFT devices is the subthreshold swing (SS), which is usually extracted from a semilog plot of the transfer curve taken at high VDS, as shown below.
SS =
dVGS d(Log IDS)
(2)
where SS is the inverse of the maximum slope in the transfer curve. Here we obtained a value of 0.3 and 0.2 V/dec for device A and B, respectively. Deriving from SS, we can infer the maximum
(3) 11
Based on the given value of Ci, the Nit of 8.59 10 and 7.05 1011 cm 2 was calculated for device A and B, respectively. According to above result, we conclude that the device B has the smaller trapping at the channel–insulator interface, thus improving the stability. In order to further analyze the device stability, temperature stress tests were conducted as shown in Fig. 6. The stress temperature was fixed at 293, 313, 333, 353, and 373 K, respectively. The transfer measurement was carried out in dark after the temperature had stayed at the fixed level for about 1 min. The ΔVTH of device B (1.32 V) was smaller than that of device A (4.24 V). Interestingly, the slope of curves had little change despite of the increase of the stress temperature, indicating that the change of mobility can be ignored. This suggests that the dominant factor is simple charge trapping in gate insulator and/or at the channel–insulator interface rather than the creation of defects within the oxide semiconductor channel material. In addition, VTH shifted negatively with the increase of the temperature for IZOTFTs. This phenomenon can be explained as follows: at higher temperatures, more electrons are able to escape from the localized states and contribute to the free carriers, which results in a smaller threshold voltage. The subthreshold current in amorphous ZnObased multicomponent oxide TFTs is well described by the thermally activated Arrhenius model [17–20], where it is assumed that thermally activated electrons from deep level trap sites into the conduction band move quickly toward the drain electrode due to a lateral electrical field. It is observed that the drain current is thermally activated and described by
ID = ID0⋅exp(−Ea/kT )
(4)
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Fig. 8. Active energy (Ea) as a function of VGS.
Fig. 9. Distribution of the acceptor-like localized states at the IZO-insulator interface at flat-band (a) and for gate bias increased beyond flat band (b). Fig. 6. The evalution of the transfer curve for IZO-TFTs as a function of the measurement temperature.
film (NSS) and an interfacial trap density (Nit). As all the trap sites below EF must be filled with electrons before they can move to the EF level in the forbidden bandgap region. Therefore, a much faster falling rate (∼1.45 eV/V) of Ea in device B compared to that (∼1.07 eV/V) in device A suggests that a Ntotal value of device B is reduced compared to device A. Device B exhibits a faster moving EF level with respective VGS, which means the reduction in bulk and interface trap density. To investigate in detail the distribution and density of tail states and deep states within energy band gap in a-IZO TFTs, the DOS is calculated based on the following equation: It was assume that the thermal energy (kBT) is much smaller than the characteristic energy of the density of states variation (Eo). In this case, the charge of the acceptor-like states (Qt) filled by the gate bias (VGS) is given by [21]:
Qt = q
C
Fig. 7. The relationship between 1/T and IDS as a function of VGS for device B.
where ID0 is the prefactor, Ea is the activation energy, k is the Boltzmann constant, and T is the temperature. Ea can be easily extracted by plotting log (IDS) and 1/kT. Fig. 7 shows the relationship between 1/T and IDS as a function of VGS for device B. The relationship between Ea and VGS is shown in Fig. 8. Ea (Ea ¼EC–EF) represents the energy difference between the Fermi level (EF) and the conduction band edge. The maximum Ea for device A and B was 1.64 eV (at a VGS of 0.6 V) and 1.38 eV (at a VGS of 1.6 V), respectively. It was reported that the rate of change in EF with respect to VGS (ΔEF/ΔVGS) was inversely proportional to the magnitude of Ntotal in the case of a TFT with a significantly large trap density (Ntotal) including the DOS of a semiconductor
EC− EFO+ qVs
∫E − E
g (E )dE
FO
(5)
where q is the electron charge, Vs is the surface potential, and EFo is the equilibrium Fermi level in the IZO layer (see Fig. 9 where Q/q is shown as the dashed area). The charge (Qt) can also be expressed as
Qt =
ε qnt = i (VGS − VFB) dt d td i
(6)
where qnt is the surface charge, VFB is the flat-band voltage, εi and di are respectively the permittivity and the thickness of the gate dielectric, and dt is the thickness of the space charge layer. Substituting Eq. (6) into Eq. (5) and differentiating both sides with respect to VGS, we obtain
dqVS dE d ⎛ nt ⎞ ⎜⎜ ⎟⎟ = g (Ea ) = − g (Ea ) a dVg ⎝ dt ⎠ dVGS dVGS
(7)
J. Zhang et al. / Ceramics International 42 (2016) 8115–8119
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References
Fig. 10. Calculated DOS distribution as a function of the energy (EC–E) for devices.
where Ea ¼Ec EFO qVs is the activation energy. Hence, we can relate the density of localized states to the derivative of the activation energy with respect to gate bias:
g (Ea ) = −
d ⎛ nt ⎞ ⎜ ⎟ dVGS ⎝ dt ⎠
dEa dVGS
(8)
We now consider two limiting cases. For a thick gate dielectric and a thin IZO layer, the band bending in the IZO layer is small compared to the characteristic energy (Eo). In this case, dt E t, where t is the thickness of the active layer, and Eq. (4) reduces to
g (Ea ) = −
εi dE
qdit dV a
GS
(9)
Fig. 10 shows the DOS of devices. The total DOS for device B is much smaller than that for device A, which is matched with their respective falling rates. It is important to note that the smaller value of ΔVTH under temperature stress of device B is well agreed with the results of DOS as shown in Fig. 6. The better stability for device B can be attributed to the reduced Ntotal at the channel/gate dielectric interface and semiconductor film. The above discussion could lead to the conclusion that using ZrO2 Al2O3 nanolaminates as gate insulator is an effective way to improve the electrical performance and stability.
4. Conclusion In conclusion, we have successfully fabricated ZrO2–Al2O3 nanolaminates for low-voltage-drive and high-mobility IZO-TFT. The device shows a high field effect mobility of 14.3 cm2/V s, a threshold voltage of 0.15 V, an on/off ratio of more than 107, and a very small sub-threshold swing of 0.2 V/dec. Moreover, characterization of DOS has been realized by temperature stress studies. The superior temperature stability is originated from the smaller DOS. The proposed device B in this paper can act as driving devices in the next-generation flat panel displays.
Acknowledgment This work is supported by the National Natural Science Foundation of China (61077013, 61274082, 51072111), Project Funded by China Postdoctoral Science Foundation (2015T580315).
[1] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, H. Hosono, Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors, Nature (Lond.) 432 (2004) 488–492. [2] L. Yue, H.F. Pu, H.L. Li, S.J. Pang, Q. Zhang, Dip-coated Al–In–Zn–O thin-film transistor with poly-methylmethacrylate gate dielectric, J. Phys. D: Appl. Phys. 46 (2013) 445106. [3] H.P. Lin, F. Zhou, J. Li, X.W. Zhang, L. Zhang, X.Y. Jiang, Zh.L. Zhang, J.H. Zhang, Effects of green emission on the performance of white organic light-emitting devices and their electroluminescent characteristics, J. Phys. Chem. C 115 (2011) 24341. [4] C.H. Woo, Y.Y. Kim, B.H. Kong, H.K. Cho, Effects of the thickness of the channel layer on the device performance of InGaZnO thin-film-transistors, Surf. Coat. Technol. 205 (2010) S168–S171. [5] J.H. Kang, E.N. Cho, C.E. Kim, M.J. Lee, S.J. Lee, J.M. Myoung, I. Yun, Mobility enhancement in amorphous InGaZnO thin-film transistors by Ar plasma treatment, Appl. Phys. Lett. 102 (2013) 222103. [6] W. Maeng, S.H. Lee, J.D. Kwon, J. Park, J.S. Park, Atomic layer deposited p-type copper oxide thin films and the associated thin film transistor properties, Ceram. Int. 42 (2016) 5517–5522, http://dx.doi.org/10.1016/j. ceramint.2015.12.109. [7] Y. Wang, X.W. Sun, G.K.L. Goh, H.V. Demir, H.Y. Y, Influence of channel layer thickness on the electrical performances of inkjet-printed In–Ga–Zn oxide thin-film transistors, IEEE Trans. Electron Device 58 (2011) 2. [8] M. Balog, M. Schieber, M. Michman, S. Patai, The chemical vapour deposition and characterization of ZrO2 films from organometallic compounds, Thin Solid Films 47 (1977) 109. [9] G.D. Wilk, R.M. Wallace, J.M. Anthony, High-k gate dielectrics: Current status and materials properties considerations, J. Appl. Phys. 89 (2001) 5243. [10] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, H. Hosono, Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor, Science 300 (2003) 1269. [11] M.S. Oh, D.K. Hwang, K. Lee, S. Im, Low voltage complementary thin-film transistor inverters with pentacene-ZnO hybrid channels on AlOx dielectric, Appl. Phys. Lett. 90 (2007) 173511. [12] K. Yim, Y. Yong, J. Lee, K. Lee, H.H. Nahm, J. Yoo, C. Lee, C. Seong Hwang, S. Han, Novel high-k dielectrics for next-generation electronic devices screened by automated ab initio calculations, NPG Asia Mater. 7 (2015) e190. [13] M. Ritala, M. Leskelä, Handbook of Thin Film Materials, Chapter 2, H.S. Nalwa Academic, New York (2002), p. 103. [14] Riikka L. Puurunen, Surface chemistry of atomic layer deposition: a case study for the trimethylaluminum/water process, J. Appl. Phys. 97 (2005) 121301. [15] T. Waggoner, J. Triska, K. Hoshino, J.F. Wager, J.F. Conley Jr., Zirconium oxidealuminum oxide nanolaminate gate dielectrics for amorphous oxide semiconductor thin-film transistors, J. Vac. Sci. Technol. B 29 (2011) 04D115. [16] X. Ding, H. Zhang, J. Zhang, J. Li, W. Shi, X. Jiang, Z. Zhang, IGZO thin film transistors with Al2O3 gate insulators fabricated at different temperatures, Mater. Sci. Semicon. Proc. 29 (2015) 69–75. [17] W. Kim, S.H. Lee, J.H. Bang, H.S. Uhm, J.S. Park, Role of O2/Ar mixing ratio on the performances of IZO thin film transistors fabricated using a two-step deposition process, Thin Solid Films 520 (2011) 1475–1478. [18] J. Jeong, Y. Hong, J.K. Jeong, J.S. Park, Y.G. Mo, Meyer–Neldel rule and extraction of density of states in amorphous indium–gallium–zinc-oxide thin-film transistor by considering surface band bending, Jpn. J. Appl. Phys. 49 (2010) 03CB02. [19] K. Takechi, M. Nakata, T. Eguchi, H. Yamaguchi, S. Kaneko, Temperature-dependent transfer characteristics of amorphous InGaZnO4 thin-film transistors, Jpn. J. Appl. Phys. 48 (2009) 011301. [20] H.C. Slade, M.S. Shur, S.C. Deane, M. Hack, Below threshold conduction in a-Si: H thin film transistors with and without a silicon nitride passivating layer, Appl. Phys. Lett. 69 (1996) 2560. [21] Y.H. Tai, H.L. Chiu, L.S. Chou, The deterioration of a-IGZO TFTs owing to the copper diffusion after the process of the source/drain metal formation, J. Electrochem. Soc. 159 (2012) J200–J203.
Contents lists available at ScienceDirect
Ceramics International journal homepage: www.elsevier.com/locate/ceramint
Performance enhancement in InZnO thin-film transistors with compounded ZrO2–Al2O3 nanolaminate as gate insulators Jianhua Zhang a,n, Xingwei Ding a,1, Jun Li b, Hao Zhang a, Xueyin Jiang b, Zhilin Zhang a,b a b
Key Laboratory of Advanced Display and System Application, Ministry of Education, Shanghai University, Shanghai 200072, China Department of Materials Science, Shanghai University, Shanghai 200072, China
art ic l e i nf o
a b s t r a c t
Article history: Received 9 January 2016 Accepted 2 February 2016 Available online 6 February 2016
We fabricated compounded ZrO2–Al2O3 nanolaminate dielectrics by the atomic layer deposition (ALD) and used them to successfully integrate the high-performance InZnO (IZO) thin-film transistors (TFTs). It is found that nanolaminate dielectrics combine the advantages of constituent dielectrics and produce TFTs with improved performance and stability compared to single-layer gate insulators. The mobility in IZO-TFT was enhanced about 22% by using ZrO2–Al2O3 gate insulators and the stability was also improved. The transfer characteristics of IZO-TFTs at different temperatures were also investigated and temperature stability enhancement was observed for the TFT with ZrO2–Al2O3 nanolaminates as gate insulators. A larger falling rate (∼1.45 eV/V), a lower activation energy (Ea, ∼1.38 eV) and a smaller density-of-states (DOS) were obtained based on the temperature-dependent transfer curves. The results showed that temperature stability enhancement in InZnO thin-film transistors with ZrO2–Al2O3 nanolaminate as gate insulators was attributed to the smaller DOS. & 2016 Elsevier Ltd and Techna Group S.r.l. All rights reserved.
Keywords: B. Interfaces Thin-film transistors Electronic materials Compounded dielectrics Density-of-states
1. Introduction Thin film transistors (TFTs) fabricated by using amorphous oxide semiconductors have received considerable attention and attracted increasing research interest owing to their potential application in active-matrix flat-panel displays (AMFPD) [1–3]. Both the channel layer and gate insulators play a crucial role in TFT performance. In order to obtain TFTs with better performance, many groups have paid attention to optimization of the channel layer fabrication process [4–7]. However, few effort has been made to investigate the effect of gate insulator fabrication parameters on the TFT performance. Among the gate insulators investigated to date, ZrO2 has been considered as a possible alternative because of its high dielectric constant and reasonable bandgap [8]. However, ZrO2 tends to crystallize easily [9]. As a result, crystalline gate dielectrics may have problems such as large current leakage (as grain boundaries serve as high-leakage paths) and surface roughness which leads to reduction of the mobility and the stability [10–12]. In comparison, Al2O3 films synthesized have been reported to remain amorphous up to 1000 °C. Hence, the novel ZrO2-Al2O3 nanolaminate dielectrics has a mixture structure of crystalline phase ZrO2 and amorphous phase Al2O3 in order to n
Corresponding author. E-mail addresses: [email protected], [email protected] (J. Zhang). 1 Contributed equally to this work.
http://dx.doi.org/10.1016/j.ceramint.2016.02.014 0272-8842/& 2016 Elsevier Ltd and Techna Group S.r.l. All rights reserved.
coordinate the tradeoff between capacitance and leakage current performances of a capacitor. Atomic layer deposition (ALD) is a highly conformal and uniform technique with inherent atomic-scale control of thin film composition, making it ideally suited for deposition of nanolaminates [13–15]. In this paper, with a goal of obtaining the TFT with high mobility and high stability, a nanolaminates film consisting of with a novel structure (200 nm) overlaid with ZrO2 (about 10 nm) and Al2O3 (about 10 nm) alternately, instead of a single layer, was used as the gate insulator. As comparison, the TFTs with single ZrO2 (200 nm) and Al2O3 (200 nm) as gate insulator were also prepared. However, the TFT with 200 nm ZrO2 insulator failed to show suitable transistor characteristics due to poor leakage properties. The IZO-TFT with Al2O3 (200 nm) as gate insulator was named ‘device A’, while the IZO-TFT with ZrO2–Al2O3 nanolaminates (total 200 nm) as gate insulator was named ‘device B’.
2. Experiments A schematic cross section of the staggered, bottom-gate IZOTFTs used in this study is shown in Fig. 1. A heavily-doped n-Si substrate served as a bottom-gate contact. n-Si coupons were cleaned with consecutive rinses of acetone, isopropyl alcohol, and de-ionized water, followed by dehydration in an oven for 30 min. Immediately following this procedure, the ZrO2 and Al2O3 films were deposited via ALD technique at 250 °C.
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Fig. 1. Schematic structure of the IZO-TFTs.
Fig. 2. XRD pattern of ZrO2 film (total 200 nm) and ZrO2–Al2O3 nanolaminates (total 200 nm).
Tetrakis dimethyl amino zirconium (TDMAZr) as zirconium source and water (H2O) as oxygen source were used to form ZrO2 films. The TDMAZr bubbler was heated at 60 °C. Al2O3 was deposited by using alternating exposures of Al(CH3)3 and H2O vapor. Al(CH3)3 and H2O were used as the sources of Al and O, respectively. Following deposition of the gate insulator, an IZO films with an thickness of approximately 20 nm were deposited by rf-magnetron sputtering at room temperature using an IZO target (99.99%, In2O3:ZnO¼1:1 mol%) with a power density of 1 W/cm2 and gas mixing ratio of Ar:O2 (30:1). Chamber pressure before sputtering was 5 10-4 Pa, and total pressure was 0.5 Pa. Prior to channel layer deposition, the target was pre-sputtered in pure Ar gas for 10 min to remove the natural surface oxide layer of the target. After deposition of IZO layer, about 200 nm Al was deposited by thermal evaporation to form the source and drain electrodes through a shadow-mask with the channel width (W) of 1000 mm and channel length (L) of 50 mm. Thermal annealing was carried out at 300 °C for 35 min in atmosphere. The thickness of the film was measured by the alpha step (Dektak 3st). The electrical characteristics of IZO-TFTs were measured by Agilent E3647A Dual output DC power supply and Keithley 6485 Picoammeter and related software. The capacitance characteristics were measured by Agilent E4980A LRC meter. The structural property of the films was determined using X-ray diffraction measurements with Cu–Kα radiation (D/MAX) and high-resolution transmission electron microscopy (HRTEM, FEI Tecnai™ G2 F 20).
3. Results and discussion Nearly all metal oxides of interest, with the exception of Al2O3, will form a polycrystalline film either during deposition or upon modest thermal treatments: HfO2 and ZrO2 are no exceptions. Fig. 2 shows the XRD pattern of ZrO2 film and ZrO2–Al2O3 nanolaminates. The ZrO2 (110) peak appearing at 35.2° indicates that
Fig. 3. Cross-sectional TEM images of ZrO2–Al2O3 nanolaminates at (a) low resolution and (b) high resolution.
the ZrO2 film is polycrystalline. The disadvantages of polycrystalline film are discussed in the introduction parts. The peak for ZrO2–Al2O3 nanolaminates is quite wide and of low intensity, suggesting that very small grains are locally embedded in the amorphous structure. We can conclude that inserting amorphous Al2O3 film is an effect way to suppress the crystalline of ZrO2. In our previous work, we have found that the IGZO-TFT with ALD-Al2O3 as gate insulator shows an amorphous phase with a very smooth interface between IGZO and Al2O3 [16]. So in recent experiment, the TEM was applied only to device B to evaluate its microstructure and interfacial layer properties, and results are displayed in Fig. 3. The ZrO2–Al2O3 nanolaminates show a mixed amorphous Al2O3 and poorly crystallized ZrO2 structure. The ZrO2 shows a poorly crystallized structure due to the fact that addition of Al2O3 into ZrO2 matrix affects nucleation and growth of ZrO2 grains from the composite matrix, so mixing of Al2O3 with ZrO2 is an effect way to suppress the crystallization. These results are consistent with our XRD results. As shown in Fig. 3. Another observation is that interface between Al2O3 and IZO is very smooth which is in favor of the carriers transportation. Fig. 4 shows the output characteristics of devices at applied gate voltage (VGS)¼10 V and source to drain voltage (VDS)¼ 10 V. The output current (IDS) is 3.9 10 4 A for device A while the value for device B is 5.8 10 4 A. The lack of current crowding at low source-drain biases indicates a good Ohmic contact at the Al/ IZO interface. Furthermore, this TFT operates as an n-channel,
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Fig. 5. Corresponding transfer characteristic IDS versus VGS at a fixed VDS 10 V and the IDS1/2–VGS curves of devices.
density of surface states at the channel-insulator interface as:
⎡ SSLog(e) ⎤C − 1⎥ i Nit = ⎢ ⎣ (kT /q) ⎦q
Fig. 4. Output characteristics of the IZO-TFTs.
enhancement-mode device. In addition, there is good saturation at high drain biases, indicating depletion of the entire thickness of the IZO layer of free electrons. Fig. 5 shows corresponding transfer characteristic IDS versus VGS at a fixed VDS ¼10 V and the IDS1/2–VGS curves of devices. The on/off ratios were measured at approximately 7 106 and 8 107 for device A and B, respectively. This shows that the devices have good characteristics as the backplane of OLEDs requiring a relatively high on-current and small off-current for a rapid response and low power consumption. The improvement in on/off ratio of device B is attributed to the decrease in offcurrent. From the IDS1/2–VGS curves shown in Fig. 4, field-effect mobility (m) and threshold voltage (VTH) can be extracted according to the following expression:
IDS =
CiμW (VGS − VTH)2 2L
(for VDS > VGS − VTH)
(1)
where Ci is the capacitance per unit area of the insulator layer (Ci for device A and B are 34 and 47.8 nF/cm2, respectively). W and L are the channel width and length, respectively, and VDS and VGS are the drainsource voltage and gate-source voltage. The field-effect mobility was obtained at 11.7 and 14.3 cm2/V s, whereas threshold voltage VTH was found 0.54 and 0.15 V for device A and B, respectively. Another figure of merit for evaluation of TFT devices is the subthreshold swing (SS), which is usually extracted from a semilog plot of the transfer curve taken at high VDS, as shown below.
SS =
dVGS d(Log IDS)
(2)
where SS is the inverse of the maximum slope in the transfer curve. Here we obtained a value of 0.3 and 0.2 V/dec for device A and B, respectively. Deriving from SS, we can infer the maximum
(3) 11
Based on the given value of Ci, the Nit of 8.59 10 and 7.05 1011 cm 2 was calculated for device A and B, respectively. According to above result, we conclude that the device B has the smaller trapping at the channel–insulator interface, thus improving the stability. In order to further analyze the device stability, temperature stress tests were conducted as shown in Fig. 6. The stress temperature was fixed at 293, 313, 333, 353, and 373 K, respectively. The transfer measurement was carried out in dark after the temperature had stayed at the fixed level for about 1 min. The ΔVTH of device B (1.32 V) was smaller than that of device A (4.24 V). Interestingly, the slope of curves had little change despite of the increase of the stress temperature, indicating that the change of mobility can be ignored. This suggests that the dominant factor is simple charge trapping in gate insulator and/or at the channel–insulator interface rather than the creation of defects within the oxide semiconductor channel material. In addition, VTH shifted negatively with the increase of the temperature for IZOTFTs. This phenomenon can be explained as follows: at higher temperatures, more electrons are able to escape from the localized states and contribute to the free carriers, which results in a smaller threshold voltage. The subthreshold current in amorphous ZnObased multicomponent oxide TFTs is well described by the thermally activated Arrhenius model [17–20], where it is assumed that thermally activated electrons from deep level trap sites into the conduction band move quickly toward the drain electrode due to a lateral electrical field. It is observed that the drain current is thermally activated and described by
ID = ID0⋅exp(−Ea/kT )
(4)
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Fig. 8. Active energy (Ea) as a function of VGS.
Fig. 9. Distribution of the acceptor-like localized states at the IZO-insulator interface at flat-band (a) and for gate bias increased beyond flat band (b). Fig. 6. The evalution of the transfer curve for IZO-TFTs as a function of the measurement temperature.
film (NSS) and an interfacial trap density (Nit). As all the trap sites below EF must be filled with electrons before they can move to the EF level in the forbidden bandgap region. Therefore, a much faster falling rate (∼1.45 eV/V) of Ea in device B compared to that (∼1.07 eV/V) in device A suggests that a Ntotal value of device B is reduced compared to device A. Device B exhibits a faster moving EF level with respective VGS, which means the reduction in bulk and interface trap density. To investigate in detail the distribution and density of tail states and deep states within energy band gap in a-IZO TFTs, the DOS is calculated based on the following equation: It was assume that the thermal energy (kBT) is much smaller than the characteristic energy of the density of states variation (Eo). In this case, the charge of the acceptor-like states (Qt) filled by the gate bias (VGS) is given by [21]:
Qt = q
C
Fig. 7. The relationship between 1/T and IDS as a function of VGS for device B.
where ID0 is the prefactor, Ea is the activation energy, k is the Boltzmann constant, and T is the temperature. Ea can be easily extracted by plotting log (IDS) and 1/kT. Fig. 7 shows the relationship between 1/T and IDS as a function of VGS for device B. The relationship between Ea and VGS is shown in Fig. 8. Ea (Ea ¼EC–EF) represents the energy difference between the Fermi level (EF) and the conduction band edge. The maximum Ea for device A and B was 1.64 eV (at a VGS of 0.6 V) and 1.38 eV (at a VGS of 1.6 V), respectively. It was reported that the rate of change in EF with respect to VGS (ΔEF/ΔVGS) was inversely proportional to the magnitude of Ntotal in the case of a TFT with a significantly large trap density (Ntotal) including the DOS of a semiconductor
EC− EFO+ qVs
∫E − E
g (E )dE
FO
(5)
where q is the electron charge, Vs is the surface potential, and EFo is the equilibrium Fermi level in the IZO layer (see Fig. 9 where Q/q is shown as the dashed area). The charge (Qt) can also be expressed as
Qt =
ε qnt = i (VGS − VFB) dt d td i
(6)
where qnt is the surface charge, VFB is the flat-band voltage, εi and di are respectively the permittivity and the thickness of the gate dielectric, and dt is the thickness of the space charge layer. Substituting Eq. (6) into Eq. (5) and differentiating both sides with respect to VGS, we obtain
dqVS dE d ⎛ nt ⎞ ⎜⎜ ⎟⎟ = g (Ea ) = − g (Ea ) a dVg ⎝ dt ⎠ dVGS dVGS
(7)
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References
Fig. 10. Calculated DOS distribution as a function of the energy (EC–E) for devices.
where Ea ¼Ec EFO qVs is the activation energy. Hence, we can relate the density of localized states to the derivative of the activation energy with respect to gate bias:
g (Ea ) = −
d ⎛ nt ⎞ ⎜ ⎟ dVGS ⎝ dt ⎠
dEa dVGS
(8)
We now consider two limiting cases. For a thick gate dielectric and a thin IZO layer, the band bending in the IZO layer is small compared to the characteristic energy (Eo). In this case, dt E t, where t is the thickness of the active layer, and Eq. (4) reduces to
g (Ea ) = −
εi dE
qdit dV a
GS
(9)
Fig. 10 shows the DOS of devices. The total DOS for device B is much smaller than that for device A, which is matched with their respective falling rates. It is important to note that the smaller value of ΔVTH under temperature stress of device B is well agreed with the results of DOS as shown in Fig. 6. The better stability for device B can be attributed to the reduced Ntotal at the channel/gate dielectric interface and semiconductor film. The above discussion could lead to the conclusion that using ZrO2 Al2O3 nanolaminates as gate insulator is an effective way to improve the electrical performance and stability.
4. Conclusion In conclusion, we have successfully fabricated ZrO2–Al2O3 nanolaminates for low-voltage-drive and high-mobility IZO-TFT. The device shows a high field effect mobility of 14.3 cm2/V s, a threshold voltage of 0.15 V, an on/off ratio of more than 107, and a very small sub-threshold swing of 0.2 V/dec. Moreover, characterization of DOS has been realized by temperature stress studies. The superior temperature stability is originated from the smaller DOS. The proposed device B in this paper can act as driving devices in the next-generation flat panel displays.
Acknowledgment This work is supported by the National Natural Science Foundation of China (61077013, 61274082, 51072111), Project Funded by China Postdoctoral Science Foundation (2015T580315).
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