Performance improvement of doped TFET by using plasma formation concept

Accepted Manuscript Performance improvement of doped TFET by using plasma formation concept Deepak Soni, Dheeraj Sharm, Shivendra Yadav, Mohd. Aslam, Neeraj Sharma

PII:

S0749-6036(17)31576-8

DOI:

10.1016/j.spmi.2017.10.012

Reference:

YSPMI 5306

To appear in:

Superlattices and Microstructures

Received Date: 29 June 2017 Revised Date:

10 October 2017

Accepted Date: 12 October 2017

Please cite this article as: D. Soni, D. Sharm, S. Yadav, M. Aslam, N. Sharma, Performance improvement of doped TFET by using plasma formation concept, Superlattices and Microstructures (2017), doi: 10.1016/j.spmi.2017.10.012. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

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Performance Improvement of Doped TFET by Using Plasma Formation Concept

Deepak Soni, Dheeraj Sharma, Shivendra Yadav, Mohd. Aslam, *Neeraj Sharma

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Nanoelectronics and VLSI Lab. Electronics and Communication Engineering Discipline PDPM Indian Institute of Information Technology, Jabalpur, 482005, India. Department of Computer Engineering*, Ramrao Adik Institute of Technology* Nerul, Navi Mumbai India

Abstract

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Formation of abrupt doping profile at tunneling junction for the nanoscale tunnel field effect transistor (TFET) is a critical issue for attaining improved electrical behaviour. The realization of abrupt doping profile is more difficult in the case of physically doped TFETs due to material solubility limit. In this concern, we propose a novel design of TFET. For this, P+ (source)I (channel)-N (drain) type structure has been considered, wherein a metal electrode is deposited over the source region. In addition to this, a negative voltage is applied to the source electrode (SE). It induces the surface plasma layer of holes in the source region, which is responsible for steepness in the bands at source/channel junction and provides the advantage of higher doping in source region without any addition of the physical impurity. The proposed modification is helpful for achieving steeper band bending at the source/channel interface, which enables higher tunneling generation rate of charge carriers at this interface and overcomes the issue of low ON-state current. Thus, the proposed device shows the increment of 2 decades in drain current and 252 mV reduction in threshold voltage compared with conventional device. The optimisation of spacer length (LSG ) between source/gate Email addresses: [email protected] (Deepak Soni), [email protected] (Dheeraj Sharma), [email protected] (Shivendra Yadav), [email protected] (Mohd. Aslam), [email protected] (*Neeraj Sharma)

Preprint submitted to Elsevier

October 13, 2017

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(LSG ) and applied negative voltage (Vpg ) over source electrode have been performed to obtain optimum drain current and threshold voltage (Vth). Further, for the suppression of ambipolar current, drain region is kept lightly doped, which reduces the ambipolar current up to level of Off state current. Moreover, in the proposed device gate electrode is underlapped for improving RF performance. It also reduces gate to drain capacitances (Cgd ) and increases cut-off-frequency (fT ), fmax , GBP, TFP. In addition to these, linearity analysis has been performed to validate the applicability of the device.

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Keywords: Ambipolar conduction, band to band tunneling, material solubility, surface plasma formation, threshold Voltage. 1. Introduction

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Miniaturisation of the conventional metal oxide semiconductor field effect transistor (MOSFET) delivers enhanced current drivability, device compactness, cost saving and improved RF performance [1-2]. Regardless of these benefits, MOSFET experiences many challenges like, limitation of 60 mV/decade subthreshold swing (SS) at room temperature, short channel effects (SCEs), drain-induced barrier lowering, low ION /IOF F ratio and high leakage current [3-6]. In this concern, tunnel field effect transistor (TFET) is a most suitable applicant for replacement of the MOSFET [7-8]. TFET can deliver subthreshold swing (SS) below 60 mV/dec due to a different carrier injection mechanism (band to band tunneling) [9-10]. It is more immune towards short channel effects (SCEs) and has low OFF-state current [11-12]. But TFET faces serious issues related to low ON-state current, ambipolar current and poor RF performance [13-16]. Thus, for the improvement of overall performance of TFET with downsizing, several works has been done previously like hetero structure [17-18], gate work function engineering [10],[19], gate overlapping over the drain region [20] and Gaussian doping in drain region [21-22]. But all these techniques have their limitations. The heterogeneous device uses low energy band gap material in source region for improving driving current and high energy band gap material is applied at the drain side for the suppression of ambipolar current. Use of different semiconductor materials in heterogeneous device creates lattice mismatch problem with increased cost and fabrication complexity. Gate work function engineering is advantageous to suppress ambipolar current, at the same time beneficial for improving drain current. However, it increases gate to drain 2

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Figure 1: Cross sectional view of (a) Conventional physically doped drain source tunnel field effect transistor (PDDS-TFET), (b) lightly doped drain, physically and electrically doped source tunnel field effect transistor (LDD-PEDS-TFET) and (c) Proposed, lightly Doped drain, underlapped gate, physically and electrically doped source tunnel field effect transistor (LDD-UG-PEDS-TFET).

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capacitance (Cgd ) which degrades RF performance and generates fabrication challenges. Whereas, overlapping of the gate over drain also increases Cgd and faces a problem of scalability. Drain Gaussian doping for minimising ambipolar current is not possible in dopingless devices. Simultaneously, the use of Gaussian doping for physically doped devices at the nanoscale is much difficult with existing fabrication technology. Although, higher source doping is helpful for creating steeper band bending at source/channel tunneling junction, which results in a higher band to band tunneling generation rate that leads to high ON-state current. The use of higher doping concentration creates mobility degradation of charge carriers and band gap narrowing [23]. In addition to these, silicon can’t be doped

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over 1 × 1020 cm−3 , and an increment in the doping level above 1 × 1020 cm−3 does not increase the carrier concentration due to material solubility limit [23]. To address the issues as mentioned above, we present a modified structure of doped TFET (P+ (Source)-I (Channel)-N (Drain)) by considering an electrode with negative supply voltage, which is placed over heavily doped source region for inducing large number of charge carrier in the same region, this phenomenon is also known as electrostatic doping [24-25]. In case of electrical doping, external voltage is applied over the surface region through metal electrode where doping is required. So depending upon the polarity of the applied voltage, it induces the charge carrier of the opposite polarity and repel same polarity charge carrier towards the body [26-29]. Therefore, in the proposed device to achieve higher concentration of holes, negative voltage is applied over the heavily doped source region through the metal electrode of 4.5 eV workfunction. It pushes the electron from the surface towards the body and attracts the holes, which increases the hole concentration and leads to the formation of hole plasma layer below the Si/HfO2 interface. Increment in hole concentration creates the steepness in the energy band at the source/channel junction which intern provides higher tunneling rate. Hence, the device offers the opportunity to get significantly improved drain current and reduced threshold voltage. In addition to this, improved transconductance, cut-off-frequency and other RF parameters shows the device usability for high-frequency circuit applications. Further for the improvement of RF performance, gate electrode is underlapped which provides the significant change in gate to drain capacitance. Along with this, in the proposed device drain region is kept lightly doped for the suppression of ambipolar current. For achieving best results, optimisation of LSG and Vpg has been done, and linearity performance has been carried out that shows the less variability as compared to other structures. Rest of the paper is organized as follows: Section II describes device geometry, dimensions used for simulations and technology computer aided design (TCAD) models. Section III shows the calibration of the device. Result and discussion which deals with the device characteristics are presented in Section IV. In Section V linearity analysis of devices has been compared. Optimisation for parameter are described in Section VI. Finally, section VII covers highlights of the discussion as conclusion.

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Table 1: Device dimension and structural parameters for TFETs PDDS-TFET 1 × 1020 1 × 1020 1 × 1017 100 100 50 10 2 50 4.5 -

LDD-PEDS-TFET 5 × 1018 1 × 1020 1 × 1017 100 100 50 10 2 2 [34] 50 4.5 4.5

LDD-UG-PEDS-TFET 5 × 1018 1 × 1020 1 × 1017 100 100 50 10 2 2 [34] 30 4.5 4.5

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Symbole NA ND NA LD LS LC tsi tox LSG LGE φGE φSE

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parameter Drain doping (cm−3 ) Source doping (cm−3 ) Channel doping (cm−3 ) Drain length (nm) Source length (nm ) Channel length (nm ) Silicon thickness (nm) oxide thickness (nm) Gate to source electrode space (nm) Gate electrode Length (nm) Gate electrode work function (eV) Source electrode work function (eV)

2. Device structure and simulation parameter

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Fig.1(a-c) shows the device cross-sectional view of conventional physically doped drain source tunnel field effect transistor (PDDS-TFET), lightly doped drain physically and electrically doped source tunnel field effect transistor (LDD-PEDS-TFET) and lightly doped drain, underlapped gate physically and electrically doped source tunnel field effect transistor (LDD-UG-PEDSTFET). In PDDS-TFET, source and drain regions are physical doped and channel is kept intrinsic. Simultaneously structure of LDD-PEDS-TFET is same as PDDS-TFET, except drain is lightly doped and source region is combination of physical and electrical doping. The proposed device LDDUG-PEDS-TFET has lightly doped drain, intrinsic channel with underlapped gate electrode at drain side and source region is combination of physical and electrical doping. Other design parameters are shown in table I. 2D, Silvaco ATLAS simulator has been used for the simulation [30]. In the simulation, the non-local BTBT model is integrated [30]. However, for measuring the tunneling probability Wentzel-Kramer-Brillouin (WKB) method is used. Shockley Read Hall and Auger recombination models stated in [31] are also incorporated in the simulation to integrate effects of minority recombination. The band gap narrowing (BGN) model and quantum confinement model [32] with trap-assisted tunnelling (TAT) model [19] is also employed for the simulation. 3. Calibration of the device For the purpose of calibration, we have considered all the dimensions and biasing conditions of our conventional device (PDDS-TFET) similar to the reported work in [8]. Further, the simulated results of calibrated PDDSTFET are similar as the results reported in [8] as shown in the Fig. 2(a-b). 5

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Figure 2: In ON-state (a) energy band diagram and (b) transfer characteristics.

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Fig. 2 (a) which presents the energy band diagram along the lateral length of the device in ON-state, the energy band diagram of PDDS-TFET follows the similar variations as reported in [8]. Furthermore, transfer characteristics of calibrated PDDS-TFET is also matched with reported work [8] as shown in the Fig. 2(b). In addition to these, the proposed modification in terms of electrostatic doping in the source region over the calibrated device (PDDSTFET) shows significant improvement in the device performances as shown in Fig. 2 (b). But, the reported work in [8] implies high voltages (Vgs = 1.8 V and Vds = 1 V), which is not suitable for low power devices in current scenario. Therefore, in this manuscript, Vgs and Vds voltages are scaled down as per the requirement of current scenario of low power devices. Along with this, the silicon body thickness of 10 nm to increase strength of the device and thickness of Hf O2 is 2 nm for better coupling of gate to channel is considered.

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4. Results and discussion This section comprises of analysis of various devices through energy band diagram and carrier concentration. Along with this, performance comparison in terms of analog/RF figure of merits (FOMs) and linearity distortion parameters has been analysed. 4.1. Impact of the source and drain doping on the tunneling barrier Tunneling barrier width at source-channel and drain-channel junctions are controlled by the doping concentrations of source and drain respectively. Fig. 6

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Figure 3: Impact of (a) source doping on the source-channel tunneling barrier and (b) drain doping on the drain-channel tunneling barrier.

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3 (a) shows the impact of the source doping on the tunneling barrier at the source-channel interface. It is observed that high doping of the source region makes the band bending steeper as well as maintains lower tunneling distance at the source-channel interface and makes better alignment of conduction bands of channel to valence bands of the source. ON-state current of the TFET can be improved by selecting higher doping concentration of the source region, although, doping of silicon beyond 1 × 1020 cm−3 is not possible due to solubility limit [23]. Therefore, our proposed method is suitable for increasing the ON-state current of TFET by migrating holes toward Si/HfO2 interface in the source region by applying an appropriate value of the voltage on the source electrode. Whereas, Fig. 3(b) presents the impact of the drain doping concentration on the tunneling barrier at the drain-channel interface. It is demonstrated that selecting lower drain doping is helpful for creating higher tunneling barrier at the drain-channel interface that results into suppressed band to band tunneling generation rate of the holes. Therefore, the issue of the ambipolar current can be eliminated by this approach. Table 2: Effect of electrostatic doping in the source region

parameter Hole concentration (Source region) (cm−3 ) Electron concentration (Source region) (cm−3 ) Tunneling barrier width (Sourec/channel interface) (nm) Electric field (Sourec/channel interface)(MeV)

PDDS-TFET 1 × 1020 1 × 101 20 2.56

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LDD-PEDS-TFET 1 × 1020.8 1 × 10−3.7 8 3.3

LDD-UG-PEDS-TFET 1 × 1020.8 1 × 10−3.7 8 3.3

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Figure 4: Carrier concentration in thermal equilibrium state.

Figure 5: Contour plot of devices in thermal state (Vgs = Vds = 0 V) for hole concentration (a) PDDS-TFET (b) LDD-PEDS-TFET and (c)LDD-UG-PEDS-TFET.

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Figure 6: In thermal state (Vgs = Vds = 0 V)(a) energy band diagram and (b) electric field.

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4.2. DC Performance Analysis The impact of deposition of a metal electrode with negative voltage over the source region can be examined by the carrier concentration as presented in Fig. 4. The deposition of metal electrode with supply voltage which induces charge carriers below the interface of semiconductor/oxide, is an electrostatic doping phenomenon, so as the negative voltage applied to the source electrode (SE) increases, it increases the hole concentration under Si/HfO2 interface in the proposed device. Since, negative voltage pushes the electron towards the body and attracts the holes which leads to the formation of hole plasma layer below the Si/HfO2 interface. Contour plot as shown in Fig. 5 (a-c) shows formation of plasma layer due to electrostatic doping in the source region. Further to this, a comparative analysis has been shown in table II in thermal equilibrium state for analysing the effect of electrostatic doping in the source region. Applied negative voltage to the source electrode (SE) increases the hole concentration and decreases electron concentration in the source region of LDD-PEDS-TFET and LDD-UG-PEDS-TFET in comparison to PDDSTFET, which results in reduced tunneling barrier width and increased electric field at source channel interface. The increased hole concentration on the surface of source region shows the higher P-type doping behaviour in this region as shown in Fig. 6 (a). The energy band diagrams are taken along the cut line which is drawn 1 nm below from Si/HfO2 interface as shown in Fig. 6 (a). The bands of source region are at the higher energy level in the proposed device as compared to conventional TFET due to increased hole 9

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concentration at the surface in source region. It also increases the steepness in the bands at source-channel junction (Fig. 6 (a)). Apart from this, Fig. 6 (b) demonstrates the electric field in the thermal equilibrium state, which shows that higher electric field is generated due to electrostatic doping in the source region, which is useful for achieving higher band to band tunneling generation rate. Consequently, in ON-state, proposed device attains ≈ 2 MeV more electric field than the conventional PDDS-TFET at the source-channel interface as shown in Fig. 7 (a) for achieving higher electron tunneling rate. The steepness of bands in the ON-state of the proposed device ( LDD-PEDS-TFET and LDD-UG-PEDS-TFET) is relatively higher as well as higher number of discrete valence bands of source are collinear with the conduction bands of channel in comparison to PDDS-TFET as shown in the Fig. 7 (b). As a result higher tunneling generation rate is achieved by the proposed device demonstrated in Fig. 7 (c), that results into the improved ON-state current as presented in Fig. 7 (d). So it can be stated that LDD-UG-PEDS-TFET and LDD-PEDS-TFET has achieved 2 decade of increment in ON-state current and 252 mV reduction in threshold voltage as compare to conventional structure due to electrostatic doping in the source region. Fig. 7 (e) shows the output drain current characteristic for all devices with the variation of Vds which shows proposed device has better drain current in comparison to conventional device. Apart from this, for the suppression of negative conduction, drain region is considered lightly doped (LDD-PEDS-TFET and LDD-UG-PEDS- TFET). Lower doping in drain region uplifts the energy band of drain region and increases barrier width as shown in Fig. 8 (a). Similarly Fig. 8 (b) shows the electric field in ambipolar state this is also low for proposed device, which is helpful for the suppression of holes tunnelling at drain/channel junction and leads to the suppression of the ambipolar conduction. Consequently, the current in negative conduction state is suppressed up to level of Off state current (Fig. 7 (d)). 4.3. Analog/ RF Performance Analysis In this section of a manuscript, ability and performance of the device for Radio-Frequency (RF) application has been discussed. Transconductance shows the capability of the device to analyse the change in drain current with respect to gate to source voltage. In other words, it shows the potential of the

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Figure 7: In ON-State (Vgs = 1.0 V, Vds = 0.5 V) (a) electric field (b) energy band diagram (c) electron tunneling rate (d) transfer characteristics and (e) output characteristic (Ids Vds ).

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Figure 8: In Ambipolar state (a) energy band diagram and (b) electric field at drainchannel junction.

device to convert input voltage into output current and can be formulated as gm =

∂Ids ∂Vgs

(1)

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The formation of steep junction at source channel interface by the use of electrostatic doping in case of LDD-PEDS-TFET and LDD-UG-PEDSTFET provides higher transconductance (Fig. 9 (a)) in comparison to PDDSTFET. This represents, LDD-UG-PEDS-TFET and LDD-PEDS-TFET has higher sensitivity for converting gate voltage into drain current. The other parameters which shows the effectiveness of change in drain current with respect to drain to source voltage called as output transconductance, which is presented in Fig. 9 (b). The output transconductance (gds ) is defined as gds = ∂Ids /∂Vds , where Ids is drain current and Vds is drain voltage. It is the inverse of output resistance, gds is higher for LDD-PEDS-TFET and LDD-UG-PEDS-TFET as compare to PDDS-TFET as shown in Fig. 9 (b). The electrical performance of the device at circuit level can be influenced by parasitic capacitances. The effect of parasitic capacitance at lower frequencies is negligible, but it plays a vital role when circuit works at high frequency. Parasitic capacitance creates a loop between the output and input, due to this reason, at high-frequency, circuit oscillates and results in signal distortion. So it is required to suppress these capacitances. In this concern, the gate to drain capacitance plays a vital roll in comparison to other capacitances for degradation of device performance. 12

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Figure 9: Variation in (a) transconductance ( gm ), (b) output transconductance (gds ), and (c) gate to drain capacitance (Cgd ) and gate to SE capacitance (CgSE ) and (d) total capacitance (Ctotal ) .

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Fig. 9 (c) illustrates the gate to drain capacitance for all the structures. The drain is kept lightly doped for LDD-PEDS-TFET, due to this reason depletion width is wider at drain channel interface, which decreases the capacitive coupling at the gate-drain electrode. Further to this, the underlapping of gate electrode at drain end is responsible for further decrement in gate to drain capacitance in case of LDD-UG-PEDS-TFET. Thus, gate to drain capacitance is much lesser in comparison to other two structures. Along with this, capacitive effect of source electrode (SE) (LDD-PEDS-TFET and LDDUG-PEDS-TFET) is also considered in this study, the capacitance (CgSE ) generated due to SE is also shown in Fig. 9 (c). CgSE is very small in comparison to gate to drain capacitance due to presence of negative voltage at SE electrode. Negative voltage increases the potential difference between gate and SE electrode, thus the CgSE capacitance is very small. Finally, total capacitances is presented in the Fig. 9 (d). In this figure, very small increment is observed in overall capacitance due to CgSE . Another RF parameter Cut-off frequency (fT ) and maximum frequency of oscillation (fmax ) are essential for determination of high frequency performance of the devices. fT can be defined as the operating frequency of device at which short circuit current gain decreases up to unity. Expression for cut-off frequency (fT ) can be expressed as: gm (2) fT = 2π(Cgs + Cgd + CgSE )

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Fig. 10 (a) shows the variation in cut-off frequency (fT ) as a function of Vgs . It can be observed that for lower gate voltage fT increases due to increment in gm and reaches to peak value. However, for higher value of gate to source voltage fT decreases due to the mutual influence of increment in capacitance Cgd and reduction in mobility. gm is high for LDD-UG-PEDS-TFET due to consideration of electrostatic doping in the heavily doped source region and Cgd is lower due to underlapping of gate electrode. Thus, collectively both parameter improves the cut-off-frequency of LDD-UG-PEDS-TFET. The maximum frequency of oscillation (fmax ) depends upon the cut-off frequency, gate to drain capacitance and gate to drain resistance. From Fig. 10 (b), it can observed that fmax follows the trend of Cgd and fT , because the behaviour of fmax is dominated by a ratio of both parameters Cgd and fT . LDD-UG-PEDS-TFET has achieved higher frequency than other two

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Figure 10: Variation in (a) cut-off-frequency with gate to source voltage and (b) maximum oscillation frequency with gate to source voltage

structure, and it is around 6.7 GHz. s fmax =

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fT 8π(cgs + cgd + cgSE )Rgd

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In this analysis gain bandwidth product (GBP) is calculated with the help of TCAD tool, which is trade-off between gain and bandwidth, GBP is computed as GBP = (gm )/ (20 π(cgd + cgSE )). It can be observed that GBP for LDD-UG-PEDS-TFET is higher than PDDS-TFET and LDD-PEDSTFET as shown in Fig. 11 (a), because of the same reason as illustrated for fT . Fig. 11 (b) illustrates transit time as a function of Vgs , where it is defined as transit time(τ ) = 1/2π10fT . In other words, it can also be defined as the time required by the carriers to reach from the source region to the drain regions. It is observed that LDD-PEDS-TFET and LDD-UG-PEDSTFET shows the minimum value of τ as compared to PDDS-TFET, so it can be stated that LDD-PEDS-TFET and LDD-UG-PEDS-TFET have higher switching speed in comparison to PDDS-TFET. Further, transconductance frequency product (TFP) is also a critical parameter for the performance analysis at high frequency, where TFP depends upon ratio of transconductance to current and fT , and is given by TFP = (gm / Ids )* fT . As depicted in Fig. 11 (c), TFP for the proposed device increases for lower gate voltage because it is dominated by gm . After attaining 15

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Figure 11: Variation in (a) GBP, (b) Transit Time, (c) TFP and (d) TGF.

Table 3: Summarised output result for comparative analysis

parameter ION IOF F IAmbi gm (P eakvalue) Cgd fT fmax GBP Vth TFP

Unit (A/µm) (A/µm) (A/µm) (mS) (f F ) ( GHz) ( GHz) (GHz) (V ) (T Hz/V )

PDDS-TFET 2.5 × 10−6 2 × 10−16 5.42 × 10−7 0.019 10 0.35 0.18 0.038 0.75 0.04 × 10−3

LDD-PEDS-TFET 2.5 × 10−4 2 × 10−16 5.39 × 10−18 1.7 10 43 3.1 6.5 0.48 0.52

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LDD-UG-PEDS-TFET 2.5 × 10−4 2 × 10−16 5.39 × 10−18 1.7 6.2 69.9 6.7 13 0.48 0.9

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Figure 12: Comparative plot of (a) third order transconductance coefficient (gm3 ), (b) VIP2, (C) VIP3, (d) IIP3, (e) IMD3 and (f) 1db Compression Point.

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the peak value of TFP at Vgs ≈ 0.7 volt, it starts to decrease with increasing Vgs because in this region gm decreases and Cgd increases. Fig. 11 (d) shows the comparative picture of transconductance generation factor (TGF) with the variation of gate voltage. TGF shows the efficiency of the device to convert the DC parameter to AC parameter. TGF is a ratio of gm to Ids and due to electrostatic doping in the source region LDD-UG-PEDS-TFET attains higher transconductance and drain current. Therefore, TGF is high for proposed device in comparison to PDDS-TFET. From Table III, it can observed that DC/RF performance of LDD-UG-PEDS-TFET is better in comparison to LDD-PEDS-TFET and PEDS-TFET due to significant improvement in gm and reduction in parasitic capacitance.

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5. Linearity Analysis

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Linearity analysis of the device is required for analysing the performance and reliability of the communication system at higher frequencies. For sustainable system, the distortion in the output signal over the desired input voltage range must be minimum. For this, gm must be constant over an input voltage range to achieve a high degree of linearity. But, with the variation of Vgs , transconductance of TFET varies, which designates undesired nonlinear behaviour of device. So for linearity analysis, parameters such as third order harmonic distortion (gm3 ), voltage intercept point of second-order (VIP2), voltage intercept point of third-order (VIP3), intermodulation distortion of third order (IMD3), intermodulation intercept point of third order (IIP3) and 1-dB compression point are carried out as stated in [33]. In this section, linearity parameters of all three structures are compared and analysed. To suppress the nonlinear distortions in the output signal, the amplitude of third order harmonic distortion gm3 must be smaller because it is the main cause of distortion [33]. Fig. 12 (a) demonstrated gm3 for all devices with the variation of Vgs . It can be seen that, the peak value of gm3 and the point where gm3 crossing to zero is attained at lower gate voltage by LDD-PEDS-TFET and LDD-UG-PEDS-TFET as compared to PDDS-TFET. Fig. 12 (b) shows the second-order voltage intercept point characteristics of all devices with the variation of Vgs . An increment in VIP2 can perceive as Vgs increases. The amplitude of VIP2 of LDD-PEDS-TFET and LDD-UG-PEDS-TFET is higher as compared to PDDS-TFET which is required to achieve higher degree of linearity. The peak of VIP2 moved toward the lower gate voltage, it indicates that, to attained higher linearity lower gate voltage is required. Mostly, VIP2 is calculated to evaluate the harmonic distortion of dissimilar dc characteristic [33]. Similarly, from Fig. 12 (c) it can be seen that VIP3 of LDD-PEDS-TFET and LDD-UG-PEDS-TFET is higher than PDDS-TFET and the peak value is achieved for lower gate voltage which is required for achieving higher linearity. Fig. 12 (d) demonstrates the comparative picture of IIP3 for all three structures where, IIP3 is higher for LDD-PEDS-TFET and LDD-UG-PEDSTFET is higher. Higher value of IIP3 shows better linearity performance, this is also the effect of higher transconductance of proposed device. Another important linearity parameter called as a intermodulation distortion (IMD3) describe extrapolated intermodulation current for which first and third order intermodulation harmonic currents are equal and IMD3 is responsible for de18

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Figure 13: Effect of LSG variation on (a) electric field in thermal state, (b) hole Concentration in thermal state, (c) energy Band diagram in ON-state, (d) drain Current in ON-state (e) electric field in ON-state and (f) drain current and threshold voltage with variation in LSG .

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Figure 14: Effect of Vpg variation on (a) hole Concentration in thermal state, (b) electric field in thermal state, (c) energy Band diagram in thermal state, (d) energy Band diagram in ON-state (e) drain Current in ON-state and (f) drain current and threshold voltage with Variation in Vpg .

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generacy in a communication system. Fig. 12 (e) illustrates the lower value of IMD3 for LDD-PEDS-TFET and LDD-UG-PEDS-TFET compared with PDDS-TFET, which is essential for distortion less communication system. 1dB compression point is defined as the minimum input power to fall gain by 1-dB from its model value. It provides information about maximum input power beyond which the gain of the amplifier drops. The system requires higher value of 1-dB compression point to attain low distortion and high linearity [33]. Fig. 12 (f) depicted that the peak of 1dB compression point moved toward lower gate voltage which is the desired condition for achieving higher linearity.

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6. OPTIMIZATION

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6.1. Optimization for Spacer Length LSG It is essential to check the optimization of the spacer length between the gate to source terminals. Fig. 13 (a-f) illustrated the effect of variation in LSG from 2 nm to 10 nm. Fig. 13 (a) displays the electric field variation in the proposed device for different LSG in the thermal equilibrium state, where it can be observed that electric field increases with decrement in gatesource spacer length, which is helpful for tunneling the charge carriers at the source to channel junction. Similarly, The increment in hole concentration is observed with decreasing value of spacer length as shown in Fig. 13 (b). Moreover, to see the effect of spacer length in the ON-state, energy band diagram and ID -VG characteristic shown in Fig. 13 (c-d). As the LSG reduces, steepness of energy bands at the tunneling junction increases by the reduction of tunneling barrier between source and channel as presented in Fig. 13 (c). It provides a higher amount of electrons to tunnel from the source to channel region, therefore, drain current increases with the lowering of LSG as illustrated in Fig. 13 (d). The increased electric field at the sourcechannel interface can also provide evidence for improvement in ON-state current which is also increasing with the reduction in LSG as shown in Fig. 13 (e). In the variation of spacer length and source electrode voltage, at LSG = 2 nm optimum results are found, so to achieve better performance of the device, spacer length of 2 nm is fixed in the proposed device [34]. Variation in ON-state current and threshold voltage with incremented LSG is shown in Fig. 13 (f).

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6.2. Optimization for Source Electrode Voltage Vpg Variation of applied negative voltage over source electrode is presented in Fig. 14 (a-f). For this, Fig. 14 (a) shows the hole concentration in the thermal state, as the applied negative voltage over source electrode increases, an increment is observed in hole concentration due to attraction of opposite polarity of charges. Whereas, in Fig. 14 (b) increment in the electric field is detected due to increment in energy level of source region (Fig. 14(c)), which is responsible for lowering of tunneling barrier. This increment in energy level of source region in ON state (Fig. 14 (d)) increases tunneling area at source/channel interface with negative polarity voltage which provides increment in drain current (Fig. 14 (e)). In variation of Vpg , at Vpg = -1.2 V optimum results are found, so to achieve better performance of the device 21

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Vpg of -1.2 V is fixed in the proposed device [34]. Variation in ON-state current and threshold voltage with incremented Vpg is shown in Fig. 14 (f) 7. Conclusion

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For the first time, concept of electrostatic doping in the physically doped source region of TFET is presented. The proposed device shows 100 times increment in drain current as well as 252 mV reduction in threshold voltage. The formation of hole plasma layer provide huge improvement in RF parameters where, 89 times improvement in gm , 199 times increment in fT , 342 times increment in GBP, and 37.2 times increment in fmax is observed. The presence of SE electrode generates CgSE in LDD-PEDS-TFET and LDDUG-PEDS-TFET, however, the effect of CgSE is negligible due to presence of negative voltage over SE electrode which increases the potential difference between gate and SE. Along with this, the issue of ambipolar current is overcome by the use of lightly doped drain region and underlapped gate electrode at the drain side.

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Acknowledgements The authors would like to thank the Science and Engineering Research Board, Department of Science and Technology, Government of India (established through an act of parliament) for providing the financial support to carry out this work. As this work has been implemented under the project Implementation of Sigma Delta Modulator Using Nanowire Electrically Doped Hetero Material Tunnel Field Effect Transistor (TFET) for Ultra Low Power Applications which is funded by this board. References

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Highlight 1. we propose a novel design of TFET. For this, P+ (Source)-I (Channel)-N

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Drain) type structure has been considered, wherein a metal electrode is deposited over the source region. In addition to this, a negative voltage has been applied over the source electrode (SE). It induces the surface plasma layer of holes in the source region. Hole plasma layer in source region provides the steepness at source channel junction and provides the advantage of higher doping in source region without an addition of the physical impurity.

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Hole plasma layer in source region overcome the problem of material solubility which does not allow to dope above a certain limit.

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Used concept provides the 2 decade increment in ON-state current and decreases threshold voltage by 252 mV. It is also helpful for improving RF performance of the device.

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2.