Performance Evaluation of a Novel GAA Schottky Junction (GAASJ) TFET with Heavily Doped Pocket

Accepted Manuscript Performance evaluation of a novel GAA Schottky Junction (GAASJ) TFET with heavily doped pocket Navjeet Bagga, Anil Kumar, A. Bhattacharjee, S. Dasgupta PII:

S0749-6036(17)30194-5

DOI:

10.1016/j.spmi.2017.05.040

Reference:

YSPMI 5021

To appear in:

Superlattices and Microstructures

Received Date: 1 February 2017 Revised Date:

19 May 2017

Please cite this article as: N. Bagga, A. Kumar, A. Bhattacharjee, S. Dasgupta, Performance evaluation of a novel GAA Schottky Junction (GAASJ) TFET with heavily doped pocket, Superlattices and Microstructures (2017), doi: 10.1016/j.spmi.2017.05.040. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

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Performance Evaluation of a Novel GAA Schottky Junction (GAASJ) TFET with Heavily Doped Pocket Navjeet Bagga, Anil Kumar, A. Bhattacharjee and S. Dasgupta

E-mail: [email protected]

Abstract

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Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee-247667, India.

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The evolution of microelectronics industry is only possible through a combined effort of device miniaturization, innovative device structures and improved material property retaining the same functional efficiency. Out of several non-conventional device structures proposed in the literature, Tunnelling Field Effect Transistor (TFET) is becoming a probable alternative device for future generation VLSI circuits due to its inherent feature of carrier conduction by the band to band tunneling mechanism. In the present work, a novel Gate All Around Schottky Junction (GAASJ) TFET with Highly Doped Pocket (HDP) and stacked gate oxide is proposed and investigated by Synopsys 3D TCAD. The device under consideration is having a Schottky Junction between Source made up of Nickel Silicide (NiSi2) and HDP which provides the steep tunneling width and improvises the device performance in terms of vital parameters such as ION, ION/IOFF and Subthreshold Slope (SS). The reported parameters of the proposed GAASJ TFET have shown improvement in the technological mode of TFETs with ION ~10-5A and SS ~58.2 mV/decade. We have found 15x ION/IOFF for the GAASJ-HDP TFET over the conventional GAA TFET. Keywords: Subthreshold Slope, Tunnel FET; Highly Doped Pocket; Schottky Barrier; Gate all around; Stacked Oxide.

1.

Introduction

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The downscaling of conventional MOSFET raises various issues like short channel effects (SCEs), DIBL etc., which degrades the device performance [1-2]. During the span of technological growth enormous structures of conventional MOS device were proposed [3-4], but still, the basic phenomenon of the carrier diffusion in MOS structures puts the kT/q limit in sub-threshold slope and this is a prime pitfall for low power applications. To resolve the challenging issues of MOSFETs, many devices with different geometries are proposed in different spell of time. The Tunnel Field Effect Transistors (TFETs) are among the foremost devices which do not have any subthreshold (SS) limit [5-6]. Tunnel FETs are based on the phenomenon of band-to-band tunneling (BTBT) which causes the carriers to migrate from source to drain when the device is turned ON and the barrier keeps the current at extremely low level when the device is turned OFF. The built-in tunnel barrier in TFETs eludes the problem of short channel effects up to some extent and structural similarity with that of MOSFET provides ease in fabrication through conventional processing techniques. However, apart from all these advantages, TFETs have the disadvantage of low ON current and ambipolar behavior [7-12]. Numerous approaches are reported to improvise the TFET performance in terms of ON current and SS [13-18]. It is found in the literature that the gate all around structure provides better electrostatic control over the channel. GAA structures yield more channel width per unit area and therefore increase the current drive as compared to planar structures [19-20]. In this paper, we have proposed a GAA Schottky Junction TFET with Heavily Doped Pocket and analyze the same using the commercial Synopsys 3D TCAD software. The superiority of the proposed structure with the incorporation of additional effects i.e. the impact of the dual metal gate and the gate-drain underlap is also discussed. The remaining part of the paper is organized as follows. The device structure and 3-D simulation framework are explained in section II. Section III explains the obtained results with necessary physical explanations based on the electrostatics of the device. Section IV concludes the paper.

2. Device Structure and Simulation Framework A schematic along with the cross-sectional view of the proposed Gate All Around Schottky Junction Tunnel Field Effect Transistor with Heavily Doped Pocket (GAASJ-HDP) considered in numerical simulations is shown in Fig. 1. The experimentally proposed Schottky Barrier Nanowire [21] has been used as a starting framework for our

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simulation study. The GAASJ-HDP TFET structure consisting of lightly doped p-type silicon core forms the channel region with a doping density of 1×1015 cm-3, heavily doped pocket with an arsenic doping density of 1×1018 cm-3 and a drain region with arsenic doping of density 1×1019 cm-3. The source region of the transistor is made up of Nickel Silicide (ϕm= 4.64eV) to prompt a Schottky Junction at the source-pocket interface for increasing the tunneling probability. The device is made up of a silicon nanowire of length 260 nm and 20 nm in diameter embedded in a stack gate oxide of EOT 1nm. In the proposed structure, the stacked oxide is preferred to avoid the lattice mismatch between silicon channel and HfO2. Hence, the stacked oxide consists SiO2 (ɛr=3.9) of 0.7 nm and HfO2 (ɛr=25) of 2 nm. The equivalent oxide thickness (EOT) is calculated by the formula (thigh-κ×3.9)/κhigh-κ and is found to be 1 nm. The channel region is kept as 60 nm which includes the HDP of 2nm. Schottky Barrier Height (SBH) is taken as 0.61 eV for electrons (ϕBn) and 0.49 eV for holes (ϕBp). The tunneling masses of holes and electrons are chosen as 0.3mo and 0.2mo respectively [22], where mo is the rest mass of the electron. All the simulations are carried out at room temperature and unless mentioned otherwise the device dimensions are same for the entire analysis as shown in Fig. 1. The simulation setup is well calibrated with the experimental data [21] and shows a good agreement as given in Fig. 2, and afterwards the proposed GAASJ-HDP TFET structure is implemented on the Synopsys 3D TCAD [23]. Our simulation framework is also verified with analytical modeling results in our previously reported work from our group [17, 24]. The key models included in our simulation are barrier lowering, barrier tunneling and thermionic emission to take into account the abrupt change in energy fluxes at the NiSi2/semiconductor interface. Furthermore, near the tunneling junction, nonlocal meshes are specified and coupled by the barrier tunneling models. It is worth mentioning that the coupled drift-diffusion model is also activated along with the doping dependent mobility model to specify the carrier transport in the device. The recombination terms include the Shockley-Read-Hall (SRH) expression along with Auger effects. We have neglected non-ideal effects i.e. the gate leakage in our simulation. The device operates on the principle of tunneling width modulation, achieved through proper tuning of externally applied gate bias. In the ON State, when the positive gate bias is applied, there is a reduction of tunneling width, as a result of which the tunneling of electrons takes place from the source to channel region and results into the flow of drain current. During the OFF state, the electrons cease to tunnel but there is a thermionic current at Schottky Junction which results in leakage current. The thermionic current at the Schottky Junction is very less sensitive to the applied bias and only dependent on the barrier height and the junction cross-sectional area. To evaluate the performance of the proposed structure, we have compared the GAASJ-HDP TFET with its various analogues. The superiority of the incorporation of HDP over conventional GAA-TFET and without HDPGAASJ is discussed in the manuscript. The cross-sectional view of GAASJ TFET without HDP (GAASJ-WHDP) is shown in Fig. 3. To improvise the overall device performance different modifications have been performed on the proposed structure. In the proposed structure, we incorporated dual metal over the channel region to make Dual Metal GAASJ-HDP TFET (DM-GAASJ-HDP) as shown in Fig. 4. The research goal of the Tunnel FETs is to reduce the tunneling width at the source-channel junction (for nTFET) and increase the tunneling width at the drainchannel junction, to reduce the ambipolarity. In DM-GAASJ-HDP TFET, we have taken metal of a higher work function at the drain side to increase the tunneling width and metal having a lower work function to reduce the tunneling width at the source side. To further reduce the ambipolar conduction the underlap GAASJ-HDP TFET (UL-GAASJ-HDP) is proposed in which an underlap region is created between the drain and the channel region as shown in Fig. 5. The evaluated results are discussed in next section.

3. Results and Discussions

In this section, we have discussed the results obtained from our proposed work and investigate the device performance in various aspects. The energy band diagram of the GAASJ-HDP TFET is shown in Fig. 6, which illustrates that the effective tunneling width gets modulated at the source-channel junction by externally applied gate bias. The dominant mechanism of the carrier transport is determined by the barrier height at the Schottky junction. For the smaller barrier height, the dominating phenomenon is thermionic emission which causes more leakage, while the tunneling dominates for an increase in barrier height and decrease in tunnelling width. The externally applied gate voltage modulates the resistance at the tunneling junction, which is liable for the ON-state current. However, increase in barrier height increases the resistance across the tunnel junction and therefore reduces the current but in our proposed structure the presence of HDP boosts the drive current as shown in Fig. 7. The band diagram of the conventional GAA TFET is also shown in the inset of Fig. 6, having a large tunnel width compared to the proposed GAASJ-HDP TFET. The transfer characteristic in Fig. 7 is drawn for various values of gate work functions. It is clear from the Fig. 7(a) that the shift in the transfer characteristics occurs due to change in the metal

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work function. For a given value of VDS, it is observed that ID increases rapidly for higher values of VGS above the onset voltage. The value of the threshold voltage is extracted from the transfer characteristics using a constant current criterion (ID=10-7A) which is found to be 0.371 V. The device under consideration displays substantial increase in the magnitude of drive current with an ION of the order of 10-5 A, which shows a better result as compared to reported values in available literature [25-26]. The comparative analysis of GAASJ-HDP and conventional GAA TFET is done in Fig. 7(b) and inset of Fig. 7(a). We have found improvement in the performance of the proposed structure as explained by Fig. 7(b). To our level of detection, the subthreshold slope (SS) is 58.2 mV/decade. The impact of short channel length on the device parameters are discussed in Fig. 8. It is found that the figure of merit (FOM) of the proposed device i.e. ION/IOFF is reduced with the reduction in the channel length. From the analysis of the output characteristics as plotted in Fig. 9, a perfect saturation of the drain current (ID) can be observed. For any particular value of VGS, ID is found to rise rapidly up to a certain VDS, after which the rate of increase of ID decreases. It may be noted that at lower VDS, the applied gate bias produces an accumulation in the channel region of the nanowire, which is filled up with the electrons that are being supplied from the drain terminal; this, in turn, results in a lower value of channel resistance. As a result of this, the entire VDS (~0-0.4 V), appear across the metal-semiconductor Schottky interface which is the tunnel source in the case of proposed structure. Because of this reason, in the VDS range from 0-0.4 V, we find a rapid increase in drain current ID with increasing VDS which is evident from Fig. 9. When VDS is increased further, there is a reduction of electron concentration in the channel, because due to higher positive values of VDS, the maximum number of electrons is actually dragged away by the drain terminal itself. This causes the rise in channel resistance, which results in the drain current to increase at a slower rate with increasing VDS, than earlier. The extra drain potential (beyond~0.4V) appears across the channel drain interface, resulting in good saturation characteristics of the output current. The performance evaluation of the proposed structure over GAASJ-WHDP can be explained by transfer characteristics as illustrated in Fig. 10. The advantage of the stacked gate oxide over the conventional SiO2 gate oxide is shown in Fig. 11. The introduction of HfO2 in the gate oxide may attribute the higher electric field and hence increases the tunneling current. We have also compared the oxide thickness variation in Fig. 10, which explains the gate control on the channel charge. The proposed GAASJ-HDP TFET shows the better performance in terms of ION and also with respect to the saturation point of the drain current. The higher drain current is obtained because of HDP present near the tunneling junction. The tunneling of the electron is more in the proposed structure compared to GAASJ-WHDP, and it can be easily visualized by the contours shown in Fig. 12. It is evident from Fig. 10, that the electric field near the tunneling junction is higher and causes more electrons to tunnel in the case of GAASJ-HDP TFET. The highly doped pocket helps to reduce the tunneling width at lower VGS, compared to GAASJ-WHDP structure. Therefore, the ratio of electron tunneling is less (for a particular VGS) compared to structure under consideration. The advantage of GAASJ-WHDP structure over the proposed structure is lower OFF current (measured at VGS=0V). The tunneling junction i.e. the junction between NiSi2 and semiconductor without HDP (GAASJ-WHDP) does not pull down the barrier height and hence the leakage current is less compared to the proposed structure. To probe the physical mechanisms responsible for the reduction in OFF current, we have incorporated Dual Metal over the channel region to form a gate electrode as shown in Fig. 4. The order of the ON current is not changed because we keep the same work function of M1 near to source, as taken for the proposed structure (ϕm=4.6eV), but we changed the work function of M2 near the drain side, to be ϕm=4.8eV for suppressing the leakage current. The lower work function of the metal M1 helps to boost the electric field at the source-channel junction and the higher work function at the drain side creates a band pass structure [13], [17]. The better ION/IOFF ratio is obtained with DMGAASJ-HDP TFET structure, and, the modification in the proposed structure boost the superiority of the device performance as shown in Fig. 13. Further, reduction of the current for the negative polarity of the gate bias can be obtained by creating an underlap between drain and channel as shown in Fig. 5 (UL-GAASJ-HDP TFET). The current measured for negative gate bias for nTFET is basically a pitfall for the Tunnel FETs, named as ambipolar effect. Fig. 13 shows the effective evaluation of the obtained results by modifying the proposed structure. 4.

Conclusion

The 3D TCAD based device performance evaluation reveals that the newly proposed GAASJ-HDP TFET structure exhibits enhanced electrical characteristics in terms of ION and ION/IOFF ratio as compared to reported data in existing literature. A further research by modifying the proposed structure in terms of DM-GAASJ-HDP and ULGAASJ-HDP TFETs shows an innovative way to improve the device performance. The evaluation task is also performed with the comparison of proposed structure with conventional GAA and GAASJ-WHDP TFET. The

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performance, operation, and output current saturation mechanism of the device is explained qualitatively. The physical origin behind the performance gain is also illustrated based on the electrostatics of the device.

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Highlights:

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Schottky Junction at the Source-Channel Junction of TFET. Evaluative study with Work function and Structural Engineering. A stacked gate oxide is used in the GAASJ TFET for better gate electrostatic control. Proposed work provides 15x better ION/IOFF ratio compare to conventional GAA TFET.

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