Performance optimizing on multi-function MMIC design

Microelectronic Engineering 86 (2009) 2114–2118

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Performance optimizing on multi-function MMIC design M.C. Tu a, Y.C. Wang b, H.Y. Ueng a,* a b

Department of Electrical Engineering, National Sun Yat-Sen University, 70 Lien-hai Rd., Kaoshiung 804, Taiwan WIN Semiconductors Corporation, Hwaya Technology Park, Tao Yuan 333, Taiwan

a r t i c l e

i n f o

Article history: Received 10 August 2008 Received in revised form 31 December 2008 Accepted 15 February 2009 Available online 25 February 2009 Keywords: GaAs HBT pHEMT Enhancement-mode pHEMT

a b s t r a c t Integration of GaAs BiFET (bipolar-FET) devices to obtain the optimum performance for multiple functions of MMIC design has been achieved. In this study, heterojunction bipolar transistors (HBTs), enhancement mode pseudomorphic HEMTs (E-pHEMTs), and depletion mode pHEMTs are developed for potential applications, including the integration of HBT power amplifier circuitry with pHEMT-based bias control, logic, RF switch, and low-noise amplifier circuitries. Critical processes including gate photolithography and gate recess control are presented and discussed in detail. The enhancement-depletion modes of pHEMT, HBT electrical performance, and uniformity are investigated comprehensively. In addition, power amplifiers and high power switches based on BiFET technology are investigated. Ó 2009 Elsevier B.V. All rights reserved.

1. Introduction The challenges involved in developing RF transceiver integrated circuit designs have been reported [1,2]. A combination of GaAs HBT and E/D-pHEMT technologies has been considered as a promising solution to achieving significant design flexibility and novel circuit design opportunities [1–3]. The advantages of HBT, such as high current driving capability, excellent output power density, and better linearity characteristics in combination with the merits of pHEMT, such as low-noise at high frequencies, high input impedance, low threshold voltage, and low power consumption, can provide high performance RF solutions [3]. Recently, monolithic integration of logic control circuits, RFswitches, low-noise amplifiers, and power amplifiers was reported [4–6]. The challenges involved were examined with regard to using stacked FET–HBT geometry for an integrated transmit/receive switch [4]. The objective was to deliver the same level of functionality in the smallest possible form-factor with emphasis on the functional test yield and fabrication process yield as compared to an alternative approach of utilizing advanced multi-chip module (MCM) techniques. The BiHEMT process has been reported to integrate InGaP/GaAs HBT power amplifier technology with InGaAs/AlGaAs E/D-pHEMT technology into a single GaAs process [5]. In addition, the InGaP-PlusTM BiFET technology [6] has been developed for high volume production of commercial MMICs. Vertical integration of the InGaP HBT and pHEMT on GaAs epitaxial wafer allows independent optimization of each type of device.

* Corresponding author. Tel.: +886 7 5252000x4124/4181; fax: +886 7 5254199. E-mail address: [email protected] (H.Y. Ueng). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.02.022

Two distinct approaches, each having their own advantages, have been described. The first approach involves manufacturability and simplicity of process at the expense of device performance by co-integrating a MESFET structure into the emitter of the HBT [7]. The second approach offers improved device performance by cointegrating a pHEMT epitaxial structure in the sub-collector of the HBT at the expense of additional processing steps and a highly complex crystal growth process [8]. In the abovementioned techniques, the pHEMT epitaxial process remains a compromise between compatibility with the HBT epitaxial structure and the pHEMT device performance. Innovative technologies and detailed processes must be developed, and further studies are required. In this paper, new development on BiFET technology has been reported in detail. It includes the design of epitaxial layers, process flow, and critical gate photolithography on non-planarity structures. In addition to device fabrication, device-level DC characteristics, load-pull power performance, high performance of InGaP HBT power amplifiers, and D-mode pHEMT single-pole-doublethrow (SPDT) power switches are investigated and evaluated comprehensively. 2. Experiments 2.1. Epitaxial structure The HBT structure is designed to provide excellent power performance with high ruggedness characteristics for wireless mobile applications. The pHEMT epitaxial structure is designed to be compatible with a double selective gate recess-etch process by using AlGaAs and InGaAs as the Schottky layer and channel layer, respectively. The layer thickness, doping concentration, and mole fraction

M.C. Tu et al. / Microelectronic Engineering 86 (2009) 2114–2118

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3. Results and discussions 3.1. BiFET device structure

Fig. 1. Schematic epitaxial structure cross-section of the BiFET technology.

Fig. 2. Process flow in BiFET technology.

As shown in Fig. 1, the stacked layer structure with InGaP HBT on top of pHEMT is designed to provide the following advantages: (1) it is suitable for high volumes with low manufacturing costs as compared with selective re-growth techniques [2]; (2) it avoids the MOCVD growth temperature restrictions (normally, for performance and reliability considerations, the pHEMT growth temperature is higher than that of HBT) and eliminates the generation of additional parasitic capacitance in the pHEMT device; and (3) the InGaP etch-stop layer used can fully separate the HBT and pHEMT. Hence, there exists no HBT and pHEMT shared layers in the designed structure, which can optimize the HBT and E/D-mode pHEMT performance independently. Due to the deep HBT mesa morphology, the minimum obtainable gate length and the source/drain-to-gate or gate-to-gate spacing during pHEMT fabrication are limited. For obtaining a uniform

Fig. 3. Cross-section of deep HBT mesa morphology.

of group III elements are designed to obtain the optimum trade-off among parameters such as breakdown voltage, on-resistance, pinch-off voltage, transconductance, and gate lag. Fig. 1 shows the schematic BiFET epitaxial structure grown by MOCVD on a 150-mm semi-insulating GaAs substrate. 2.2. Process flow Fig. 2 shows the process flow of device fabrication. The process implements a total of 16 masking levels with an additional option of a Schottky diode layer. A Pt sink-in refractory base metal scheme is implemented to form an alloy through the InGaP layer, and excellent contact resistance is achieved for the base contact. This alloy, through a contact scheme, offers simplicity for the process to form a direct ohmic contact with GaAs base layer without relying on the relatively less controllable InGaP etching step. An excellent specific contact resistance of 10 7 X cm2 is achieved. A typical Au/Ge/Ni/Au ohmic metal is used for the collector contact of HBT and the source/drain contacts of pHEMTs. The boron-implant is provided with effective isolation among the devices. The first recess-etch is selected after the gate metallization. To further reduce the processing cost, a refractory first level metal is used to form a direct emitter contact without an additional emitter ohmic metal contact. A TaN thin film with a sheet resistance of 50 X/ square is used as the resistor. Two interconnection metal levels and a 100-nm SiN layer are used to form the 600-pF/mm2 MIM capacitor. Polyimide is used as a bridge layer, and a nitride protective layer is adopted for reliability. After the front-side process is completed, the thickness of the substrate is reduced to 100 lm.

Fig. 4. SEM photographs of single- and triple-gate formed by using bi-layer photoresist process.

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Collector-to-Emitter Current, Ice (A)

2.0

Ib= 0 mA to 20 mA step 4 mA 1.5

1.0

0.5

0.0 0

1

2

3

4

5

Collector-to-Emitter Voltage, Vce (Volt.) Fig. 6. IV curves of 11,522-m2 HBT power device.

BVeco (V)

b

Vturn-on (V)

ft (GHz)

fmax (GHz)

InGaP HBT 31

7

20

75

1.26

31

110

<1.0 lm single and multiple-gate pHEMT device across a 150-mm wafer is the most challenging process in BiFET technology development. Fig. 3 shows a cross-section of the deep HBT mesa morphology. Gate metals, Ti/Pt/Au and Pt/Ti/Pt/Au, are deposited for D- and E-mode pHEMTs, respectively. Fig. 4 shows the SEM cross-section of single and trip-gate devices. BiFET technology exhibits multiple-gate process ability, thus offering both high isolation and high linearity switch applications. Fig. 5 shows the cross-sectional SEM photographs of a fully completed BiFET HBT and pHEMT. The base layer is designed with DC current gain of 75, and the turn-on voltage measured for the InGaP HBT is 1.26 V. Table 1 summarizes the critical DC and RF parameters of the developed BiFET HBT. 3.2. HBT and power amplifier characteristics With regard to HBT power amplifier design, one of the most important strategies is to optimize the performance (PAE, Pout, linearity, etc.), thermal stability, RF stability, ruggedness, and chip size. For GSM 4 W handset power amplifiers, the transistor ruggedness is of great concern to the final product robustness under severe environment-extreme load mismatch and excess voltage. Under severe load mismatch conditions, a large amount of output power delivered by the power transistor is dumped back to the RF power transistor itself, causing catastrophic device failure [9]. Two of the most common failure mechanisms are (1) voltage swings exceeding the transistor breakdown voltage limit at the output stage; and (2) hot spot formation resulting in uneven current distribution across the power transistor and eventually causing thermal runaway. By optimizing both the emitter and base ballasting resistors, transistor basic unit cell design, high ruggedness and high performance can be achieved simultaneously. Fig. 6 shows the IV curve of a discreet power chip mounted on a FR4 evaluation board with a total emitter area of 11,520 lm2. The absence of significant current collapse up to 5 V indicates that the thermal design is appropriate. Fig. 7 shows the result of a

Pout

60

30 PAE

25

50

20 40

15

Gain

30

10 5

20

0 12

14

16

18

20

22

24

26

28

Input Power, Pin (dBm) Fig. 7. 1.85 GHz load-pull measurement result biased at VCE = 3.6 V under CW operation without using harmonic tuning.

80

36

Vce= 3.6 V, Ic=200 mA Freq= 900 MHz

32

70 60

Pout

28

50

24

PAE 40

20

30

PAE (%)

BVebo (V)

70 35

PAE (%)

BVcbo (V)

Output Power (dBm) /Gain (dB)

Table1 Summary of DC and RF characteristics of InGaP HBT in BiFET process.

Output Power, Pout (dBm) /Gain (dB)

Fig. 5. Cross-sectional SEMs of the HBT and pHEMT devices.

16 20 12

Gain 10

8 0 0

5

10

15

20

25

30

Input Power (dBm) Fig. 8. 900 MHz load-pull measurement result biased at VCE = 3.6 V under CW operation.

1.85-GHz load-pull measurement biased at VCE = 3.6 V with fixed VBE under CW operation and without using harmonic tuning; the power cell is able to deliver 36 dBm output power with a peak power-added efficiency (PAE) over 60%. By using pulse measurements, the PAE is obtained 3–5% higher than when measured under CW operation. The power density is 1 W/mm normalized to the total

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M.C. Tu et al. / Microelectronic Engineering 86 (2009) 2114–2118 Table 2 Summary of DC and RF characteristics of ED-mode pHEMTs.

3.5

Collect current (A)

3.0 2.5 2.0 1.5 1.0 0.5

Pout=35dBm Vce=3.6V Fequency=900MHz

0.0 -400

-300

-200

-100

Idss (mA/mm)

Vdg (V)

gm (mS/mm)

Ron (X mm)

ft (GHz)

fmax (GHz)

D-mode pHEMT 0.8 150

20

270

2.5

22

83

E-mode pHEMT +0.35 0.02

20

400

3.3

25

99

Vto (V)

VSWR3vs1 VSWR6vs1 VSWR12vs1

analyzer. The values of ft extracted for biases of Vds = 3 V and Vgs selected for maximum transconductance are 22 and 25 GHz for the D-mode pHEMTs and the E-mode pHEMTs, respectively. The corresponding fmax values are 83 and 99 GHz. Table 2 summarizes the relative characteristics of E/D-mode pHEMTs.

0

Phase angle(degree) Fig. 9. The collector current of HBT power device versus various phase angles under different output matching conditions.

2

emitter length or 0.52 mW/lm normalized to the total emitter area. Fig. 8 shows the load-pull performance of the same device at a frequency of 900 MHz. As shown in Fig. 9, the linear gain is 16 dB with a saturated output power of 35.6 dBm. The peak power-added efficiency (PAE) is 67%. The same device tested under severe load mismatch conditions (VSWR > 12:1) is able to survive up to VCE = 5 V in all the phase angles for both Ta = 25 and 90 °C at Pout = 35 dBm. This demonstrates that the HBT of BiFET technology possesses high roughness characteristics without sacrificing power performances.

3.4. SPDT high power switches Gate stacking is a technique to isolate high power RF. Stacking of gates can be achieved by using multiple-gate transistors or by connecting several transistors in series. Due to the essential advantages, a smaller chip size for a multiple-gate approach and higher isolation of serial connection approach, a mix-type of both approaches is employed for achieving the optimum results [10]. Fig. 11 shows the schematic circuit topology of a single-pole-double-throw (SPDT) switch used for evaluation of BiFET technology multi-gate processes. The switch demonstrates an insertion loss (Tx–Ant) of 0.48 dB and isolation greater than (Tx-to-Rx) 20 dB at 900 MHz. Harmonic testing is carried out to further investigate

3.3. E/D-mode pHEMT device characteristics

Fig. 11. The circuit schematic of a high power SPDT switch.

-40

E-mode pHEMTs

V ds=1.5 V

400

D-mode pHEMTs

300 200 100 0 -1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Gate-to-Source Voltage, Vgs (Volt.) Fig. 10. DC Ids–gm–Vgs characteristics of the AlGaAs/InGaAs pHEMTs in the BiFET technology.

Second Harmonic Third Harmonic

-50

-60

dBc

500

Transconductance, gm (mA/mm)

Drain-to-Source current, Ids (mA/mm)

Duplexing of wireless transmission and reception is often achieved with solid state switches. Due to low battery drainage and low cost, the mobile communication system drives the market from PIN diodes toward pHEMT switches. Advanced multi-throw pHEMT switches have emerged as one of the key components from the integration of several PAs and receivers into multi-mode cell phones. This need for expansion requires low insertion loss and high isolation from a switch. The E/D-mode pHEMT DC transfer characteristics are shown in Fig. 10, which exhibits excellent device pinch-off characteristics. The threshold voltage (Ids = 1 mA/mm), and the values of Idss are 0.8 V and 150 mA/mm for the D-mode pHEMT and +0.35 V and 0.02 A/mm for the E-mode pHEMTs, respectively. On-wafer microwave S-parameter evaluation was carried out by using a network

-70

-80

-90

-3.0

-2.8 -2.6 -2.4 -2.2 -2.0 Voltage Control Bias (Volt.)

-1.8

Fig. 12. The second- and third-harmonic reject ration measurement results of a SPDT switch.

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the linearity characteristics of the SPDT switch. As shown in Fig. 12, a 70 dBc second-harmonic rejection ratio and a 75 dBc third-harmonic rejection ratio are obtained at a Tx-to-Ant input power of 35 dBm; the control voltages are 2.5 and 0 V for the Rx and Tx, respectively. This clearly shows that the BiFET optical gate lithography process is suitable for multiple-gate high power and high linearity applications under low control voltages.

Acknowledgement Authors would like to show the greatest appreciation to WIN’s staffs: T.C. Tsai, Iris Hsieh, C.L. Chao, H.K. Lin, Jeff Yeh, Benny Ho, Forrest Cho and Paul Yeh for their contributions to develop the BiFET processes. References

4. Summary In this paper, we summarize the fabrication and characteristics of a BiFET device. MOCVD-grown epitaxial material is selected with InGaP HBT on top of a pHEMT device in order to minimize potential drawbacks as compared to the pHEMT atop of HBT structure. The challenge involved in the formation of 0.5-lm multiple-gate fingers on a high-topology wafer with a controllable small un-gated region has been overcome by using a double selective recess process, which is combined with a dual-layer gate photolithography process to offer sufficient breakdown voltage and to minimize the surface charge effect for both E- and D-mode pHEMTs. The E/ D-pHEMT and HBT electrical performances (DC, small signal, noise, and power) are presented. Functional building blocks such as high power switches and power amplifiers based on the BiFET technology are demonstrated with satisfactory performances. The results indicate that this technology offers great potential and degrees of freedom to design power amplifiers, high-integrated RF transceivers, and opportunities for the development of novel RFIC circuits.

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