- Email: [email protected]
Post etch cleaning of low-k dielectric materials for advanced interconnects: Characterization and process optimization
MICR©ELECTRONIC ENGINEERING
ELSEVIER
Microelectronic Engineering 41/42 (1998 ) 415-418
POST ETCH CLEANING OF LOW-k DIELECTRIC MATERIALS ADVANCED INTERCONNECTS: CHARACTERIZATION AND PROCESS OPTIMIZATION"
FOR
D. Louis 1 - E. Lajoinie 2 - F. Pires 2 - W. M. Lee 3 - D. Holmes 3
1. Leti (CEA - Technologies Avancees) - CEA - G, 17 rue des Martyrs, F-38054 Grenoble cedex 9, France Tel: (33) 0476883653 Fax: (33) 0476885103 2. SGS Thomson Microelectronics, Central R&D / Joint Program ST/GRESSI CEA - G, 17 rue des Martyrs, F-38054 Grenoble cedex 9, France 3. EKC Technology LTD, 19 Law Place Nerston lnd. Estate, East Kilbride, G74 4QL Scotland Tel: (44) 1355244652 Fax : (44) 1355263876
Abstract
The removal of photoresist and etch residues from an Interlayer Dielectric sandwich incorporating a FOX (fiowable oxide) low-k dielectric polymer can be successfully achieved by implementing a process using H2/N2 forming gas plasma in conjunction with Posistrip~EKC~LE. This cleaning procedure allows W filling to be carried out without delamination and via poisoning. 1. I N T R O D U C T I O N As minimum devices features continuously shrink to the deep sub-half micron region, the requirements of multi-level interconnect technology become more stringent. Interconnections have become the limiting factor for circuit speed ~-2. A key challenge for advanced VLSI interconnect technologies is to reduce the resistance of the conducting metal lines, by using copper interconnects and the capacitance between them, by using inter-metal dielectric (IMD) films with low dielectric constants and good gap-filling properties 3. Figure 1 shows various candidates for such low-k material. Currently the leading candidates for IMD's are Silicon Based Spin-on- Materials (SBSOM) low-k films. The purpose of this evaluation was to develop a process for the resist removal after via hole etching of low-k films. It is demonstrated that some cleaning techniques can drastically degrade SB-
SOM characteristics, showing an increase in dielectric constant, via edge degradation and via poisoning. am t
3
t
Sl r i c h
C rlclt
Figure 1 : Various low-k material candidates.
The evaluation first took place on unpatterned low-k dielectric wafers t o test a range of potential products for compatibility with the dielectric polymer. The study then continued with the effects of these products on cleaning, patterned and etched vias, particularly examining bowing effects. Finally
This work has been carried out within the GRESSI consortium between CEA-LETI and France TelecomCNET
"
0167-9317/98/$19.00 © Elsevier Science B.V. All rights reserved. Pll: S0167-9317(98)00096-3
416
D. Louis et aL /Microelectronic Engineering 41/42 (1998) 415-418
the cleaning effects on an integrated structure were examined to determine the influence of clean treatments on Tungsten (W) plug formation. The study was supported by electrical testing of a dual layer metal structure incorporating the low-k dielectric. 2.
EXPERIMENTAL PROCEDURE
The low-k material selected for this evaluation was a Hydrogen Silsesquioxane polymer (HSQ FOX) supplied by Dow Chemical with a dielectric constant less than three and excellent gap filling and planarisation properties. 2.1. Low k Deposition Process The spin-on low-k material was coated and cured in a Nitrogen environment. The final annealing of the material determines the chemical state of the SB-SOM. It was verified that HSQFOX annealing can be made between 400 to 450°C without significant degradation of the dielectric characteristics ; the amount of residual oxygen must however remain low4. 2.2. Low k Constant Measurement The evaluation of cleaning treatments for compatibility with FOX material was achieved using Fourier Transform Infra Red ( F T - I R ) spectroscopy. This technique monitored possible degradation of the Si-H peaks (2260 cm1) and the subsequent formation of Si-OH and H - O H peaks (3400 cm-1). Samples used for this compatibility evaluation were coated with blanket sheet of the dielectric. Chemistries tested were EKC265 TM, n-methyl pyrrolidone (NMP) based products and dimethyl sulphoxide (DMSO) based products. Results are reported in paragraph 3.1. 2.3. Low k Integration Evaluation The analysis of vias for bowing and via poisoning was carried out on a FOX dielectric sandwich in order to evaluate the efficiency of the photoresist removal process. The following structure was used : firstly an A1Cu/Ti/TiN metal stack was deposited, followed by the dielectric sandwich TeOs USG (50 nm)/HSQ FOX (400 nm)/TeOs USG (500 nm). The
lithography process was realised using DUV (Shipley SN-R 200) resist on an ASM-L/90 stepper. Via etching of the sandwich dielectric was carried out on a TEL Unity System. To minimise the impact of 02 plasma on the organic dielectric, an evaluation was carried out using products to determine the photoresist removal performance. Two cleaning processes were tested : 1. (H2/N2 Forming Gas Plasma + EKC265 TM ) 2. (H2/N2Forming Gas Plasma + solvent blend Posistrip*EKC~LE ). Results are reported in section 3.2. 2.4. Electrical Tests In order to evaluate the performance of the system into real process conditions, the structure previously described was completed after cleaning with a second metal layer, which consisted of a TiN barrier followed by W filling. Via chains between metal 1 (AICu/Ti/TiN) and metal 2 with vias of various size were used to evaluate contact resistance (Rc). Structures consisting of interlocked metal combs at metal 2 level (Figure 2) were used for linear lateral capacitance measurement. A similar structure was prepared using standard HDP (High Density Plasma) dielectric oxide as a comparison.
ill IIILn I I
I I
E
E = 0.3 or 0.4 ~tm L = 320 mm (0.3) or 290 mm (0.4) Figure 2 : Interlocked combs for capacitance measurement at metal 2.
lateral
3. RESULTS 3.1. Compatibility Study Between HSQ FOX Low k Material And Proposed Chemistries The cleaning treatments involved a comparison between the current standard clean i.e. [02 Plasma + EKC265 TM at 85°C for 15 mins.] and two other ranges of products. Solvents based on n-methyl
D. Louis et al./Microelectronic Engineering 41/42 (1998) 415-418
pyrrolidone were studied at 85°C for 15 mins and a similar study was made with products containing dimethyl sulphoxide. The FT-IR spectrum showed that the current standard oxide cleaning i.e. EKC265 TM modified Sil l bonds (Figure 3). This effect was also observed when an 02 plasma was applied.
!
810_~d-OH Sl-n
p o n ~ t l ~
Cam ComponeBt2
I
I
I
~
t
3900
3400
$900
2,100
1900
,
t
t
1dO0
900
dOO
Wavenumb~ (cm-1)
Figure 3 : FT-IR Spectrum : influence Eh'C265 TM components on the Si-H bond.
of
417
3.2. Cleaning Evaluation After Via Etch. This evaluation was camed out using FESEM to examine the edge and shape of the via. The two processes tested were : 1. (H2/N2 Forming Gas Plasma + EKC265 TM ) 2. (H2/N2 Forming Gas Plasma + solvent blend Posistrip~EKC*LE ). It was observed that both processes successfully removed photoresist with no damage at the edge of the via on 0.3 and 0.25 micron via holes. However, a bowing effect was observed in the first case at the FOX layer of the sandwich structure. The cleaning process, consisting of forming gas followed by Posistrip~EKC~LE, left the side wall of the via with straight features. This is clearly demonstrated in two cross section after W plug filling (Figure 6).
However, we observed a good compatibility between the HSQ FOX polymer and chemistries based on NMP (Figure 4) and those based on DMSO (Figure 5). Si-~
F•OH
A
~(Lg.._-, 3900
3~00
ggO0
2400
1900
ldO0
900
dO0
Wavenumber(cm -1) Figure 4 : PT"-IR Spectrum : influence of NMP chemistries.
H-OH
I 3900
I 3400
2960
24OO
I ~0
1400
900
"
W a v e n u m b e r (era-l)
Figure 5 : FT-IR Spectrum : Influence o f DMSO based products on Si-H bond.
Figure 6 .'Via cleaned with a) Plasma HyN: i. EKC265 TM, b) Plasma H ~ 2 + Posistrip® E K ~ L E .
418
D. Louis et al./Microelectronic Engineering 41/42 (1998) 415-418
3.3. Electrical Performances Electrical tests show an improvement of Rc for vias smaller than 0.3 Ixm (Figure 7), as well as an improvement of 30% for lateral capacitance (Figure 8) for this ]MD structure cleaned with Posistrip*EKC~_~E.
8 L-(~-- ~ s . . . . . . . . . . . . . . . . . .
! ..........................
' i .........
I .....
s ~
I
. . . . .
i .....
•
Fox,'reos
2 ~
I
......
..................
0.25
]
0.3
0.35 Via hole size (prn)
Figure 7 : Vias2 Kelvin Resistance versus via size.
• StanaardlrdD| IBI F O X + T E O S !
..... '
. . . .
:
With the introduction of low-k organic polymers into the ILD structure, the strategy for residue and photoresist removal must be modified. It has been shown that for this new structure, incorporating an N2/H2 plasma treatment in conjunction with PosistripcEKCCLE, cleaning can significantly improve low-k dielectric film characteristics and via hole cleaning. It was verified that this cleaning process allows W via filling to be successfully achieved without delamination from the via sidewall. The optimised dry/wet process was confirmed by electrical testing of the dual layer metal structure where good Rc via performance and improved lateral capacitance was demonstrated. Further studies are required for the dimethyl sulphoxide products to determine the cleaning performance in an integrated structure. ACKNOWLEDGEMENT
The authors wish to thank D. Fauchery for the SEM observations and are grateful to G. Passemard and E. Tabouret for fntitful discussions and assistance with the experiments. We also like to thank R. Garcia Santana for support.
Count ~:1 25 ~1
4. C O N C L U S I O N
-
2O
REFERENCES
15 10
1.
5 0
6O
70
80
90 100 Capaci~nce(pF/m)
110
120
2. 3.
Figure 8 ." Lateral capacitance comparison between standard IMD oxide and HSQ F O X sandwich structure.
4.
J. Parasczak, D. Edelstein, S. Cohen, E. Babich and J. Hummel : IEDM 1993, p. 261-264. R. K. Laxman : Semiconductor International (May 1995), p. 71-74. M. Telford : European Semiconductor, (Sep. 1997) p. 11-12. F. Pires, P. Noel, C. Lecornec, G. Passemard, D. Louis, E. Lajoinie : MAM 1997, p. 68.
ELSEVIER
Microelectronic Engineering 41/42 (1998 ) 415-418
POST ETCH CLEANING OF LOW-k DIELECTRIC MATERIALS ADVANCED INTERCONNECTS: CHARACTERIZATION AND PROCESS OPTIMIZATION"
FOR
D. Louis 1 - E. Lajoinie 2 - F. Pires 2 - W. M. Lee 3 - D. Holmes 3
1. Leti (CEA - Technologies Avancees) - CEA - G, 17 rue des Martyrs, F-38054 Grenoble cedex 9, France Tel: (33) 0476883653 Fax: (33) 0476885103 2. SGS Thomson Microelectronics, Central R&D / Joint Program ST/GRESSI CEA - G, 17 rue des Martyrs, F-38054 Grenoble cedex 9, France 3. EKC Technology LTD, 19 Law Place Nerston lnd. Estate, East Kilbride, G74 4QL Scotland Tel: (44) 1355244652 Fax : (44) 1355263876
Abstract
The removal of photoresist and etch residues from an Interlayer Dielectric sandwich incorporating a FOX (fiowable oxide) low-k dielectric polymer can be successfully achieved by implementing a process using H2/N2 forming gas plasma in conjunction with Posistrip~EKC~LE. This cleaning procedure allows W filling to be carried out without delamination and via poisoning. 1. I N T R O D U C T I O N As minimum devices features continuously shrink to the deep sub-half micron region, the requirements of multi-level interconnect technology become more stringent. Interconnections have become the limiting factor for circuit speed ~-2. A key challenge for advanced VLSI interconnect technologies is to reduce the resistance of the conducting metal lines, by using copper interconnects and the capacitance between them, by using inter-metal dielectric (IMD) films with low dielectric constants and good gap-filling properties 3. Figure 1 shows various candidates for such low-k material. Currently the leading candidates for IMD's are Silicon Based Spin-on- Materials (SBSOM) low-k films. The purpose of this evaluation was to develop a process for the resist removal after via hole etching of low-k films. It is demonstrated that some cleaning techniques can drastically degrade SB-
SOM characteristics, showing an increase in dielectric constant, via edge degradation and via poisoning. am t
3
t
Sl r i c h
C rlclt
Figure 1 : Various low-k material candidates.
The evaluation first took place on unpatterned low-k dielectric wafers t o test a range of potential products for compatibility with the dielectric polymer. The study then continued with the effects of these products on cleaning, patterned and etched vias, particularly examining bowing effects. Finally
This work has been carried out within the GRESSI consortium between CEA-LETI and France TelecomCNET
"
0167-9317/98/$19.00 © Elsevier Science B.V. All rights reserved. Pll: S0167-9317(98)00096-3
416
D. Louis et aL /Microelectronic Engineering 41/42 (1998) 415-418
the cleaning effects on an integrated structure were examined to determine the influence of clean treatments on Tungsten (W) plug formation. The study was supported by electrical testing of a dual layer metal structure incorporating the low-k dielectric. 2.
EXPERIMENTAL PROCEDURE
The low-k material selected for this evaluation was a Hydrogen Silsesquioxane polymer (HSQ FOX) supplied by Dow Chemical with a dielectric constant less than three and excellent gap filling and planarisation properties. 2.1. Low k Deposition Process The spin-on low-k material was coated and cured in a Nitrogen environment. The final annealing of the material determines the chemical state of the SB-SOM. It was verified that HSQFOX annealing can be made between 400 to 450°C without significant degradation of the dielectric characteristics ; the amount of residual oxygen must however remain low4. 2.2. Low k Constant Measurement The evaluation of cleaning treatments for compatibility with FOX material was achieved using Fourier Transform Infra Red ( F T - I R ) spectroscopy. This technique monitored possible degradation of the Si-H peaks (2260 cm1) and the subsequent formation of Si-OH and H - O H peaks (3400 cm-1). Samples used for this compatibility evaluation were coated with blanket sheet of the dielectric. Chemistries tested were EKC265 TM, n-methyl pyrrolidone (NMP) based products and dimethyl sulphoxide (DMSO) based products. Results are reported in paragraph 3.1. 2.3. Low k Integration Evaluation The analysis of vias for bowing and via poisoning was carried out on a FOX dielectric sandwich in order to evaluate the efficiency of the photoresist removal process. The following structure was used : firstly an A1Cu/Ti/TiN metal stack was deposited, followed by the dielectric sandwich TeOs USG (50 nm)/HSQ FOX (400 nm)/TeOs USG (500 nm). The
lithography process was realised using DUV (Shipley SN-R 200) resist on an ASM-L/90 stepper. Via etching of the sandwich dielectric was carried out on a TEL Unity System. To minimise the impact of 02 plasma on the organic dielectric, an evaluation was carried out using products to determine the photoresist removal performance. Two cleaning processes were tested : 1. (H2/N2 Forming Gas Plasma + EKC265 TM ) 2. (H2/N2Forming Gas Plasma + solvent blend Posistrip*EKC~LE ). Results are reported in section 3.2. 2.4. Electrical Tests In order to evaluate the performance of the system into real process conditions, the structure previously described was completed after cleaning with a second metal layer, which consisted of a TiN barrier followed by W filling. Via chains between metal 1 (AICu/Ti/TiN) and metal 2 with vias of various size were used to evaluate contact resistance (Rc). Structures consisting of interlocked metal combs at metal 2 level (Figure 2) were used for linear lateral capacitance measurement. A similar structure was prepared using standard HDP (High Density Plasma) dielectric oxide as a comparison.
ill IIILn I I
I I
E
E = 0.3 or 0.4 ~tm L = 320 mm (0.3) or 290 mm (0.4) Figure 2 : Interlocked combs for capacitance measurement at metal 2.
lateral
3. RESULTS 3.1. Compatibility Study Between HSQ FOX Low k Material And Proposed Chemistries The cleaning treatments involved a comparison between the current standard clean i.e. [02 Plasma + EKC265 TM at 85°C for 15 mins.] and two other ranges of products. Solvents based on n-methyl
D. Louis et al./Microelectronic Engineering 41/42 (1998) 415-418
pyrrolidone were studied at 85°C for 15 mins and a similar study was made with products containing dimethyl sulphoxide. The FT-IR spectrum showed that the current standard oxide cleaning i.e. EKC265 TM modified Sil l bonds (Figure 3). This effect was also observed when an 02 plasma was applied.
!
810_~d-OH Sl-n
p o n ~ t l ~
Cam ComponeBt2
I
I
I
~
t
3900
3400
$900
2,100
1900
,
t
t
1dO0
900
dOO
Wavenumb~ (cm-1)
Figure 3 : FT-IR Spectrum : influence Eh'C265 TM components on the Si-H bond.
of
417
3.2. Cleaning Evaluation After Via Etch. This evaluation was camed out using FESEM to examine the edge and shape of the via. The two processes tested were : 1. (H2/N2 Forming Gas Plasma + EKC265 TM ) 2. (H2/N2 Forming Gas Plasma + solvent blend Posistrip~EKC*LE ). It was observed that both processes successfully removed photoresist with no damage at the edge of the via on 0.3 and 0.25 micron via holes. However, a bowing effect was observed in the first case at the FOX layer of the sandwich structure. The cleaning process, consisting of forming gas followed by Posistrip~EKC~LE, left the side wall of the via with straight features. This is clearly demonstrated in two cross section after W plug filling (Figure 6).
However, we observed a good compatibility between the HSQ FOX polymer and chemistries based on NMP (Figure 4) and those based on DMSO (Figure 5). Si-~
F•OH
A
~(Lg.._-, 3900
3~00
ggO0
2400
1900
ldO0
900
dO0
Wavenumber(cm -1) Figure 4 : PT"-IR Spectrum : influence of NMP chemistries.
H-OH
I 3900
I 3400
2960
24OO
I ~0
1400
900
"
W a v e n u m b e r (era-l)
Figure 5 : FT-IR Spectrum : Influence o f DMSO based products on Si-H bond.
Figure 6 .'Via cleaned with a) Plasma HyN: i. EKC265 TM, b) Plasma H ~ 2 + Posistrip® E K ~ L E .
418
D. Louis et al./Microelectronic Engineering 41/42 (1998) 415-418
3.3. Electrical Performances Electrical tests show an improvement of Rc for vias smaller than 0.3 Ixm (Figure 7), as well as an improvement of 30% for lateral capacitance (Figure 8) for this ]MD structure cleaned with Posistrip*EKC~_~E.
8 L-(~-- ~ s . . . . . . . . . . . . . . . . . .
! ..........................
' i .........
I .....
s ~
I
. . . . .
i .....
•
Fox,'reos
2 ~
I
......
..................
0.25
]
0.3
0.35 Via hole size (prn)
Figure 7 : Vias2 Kelvin Resistance versus via size.
• StanaardlrdD| IBI F O X + T E O S !
..... '
. . . .
:
With the introduction of low-k organic polymers into the ILD structure, the strategy for residue and photoresist removal must be modified. It has been shown that for this new structure, incorporating an N2/H2 plasma treatment in conjunction with PosistripcEKCCLE, cleaning can significantly improve low-k dielectric film characteristics and via hole cleaning. It was verified that this cleaning process allows W via filling to be successfully achieved without delamination from the via sidewall. The optimised dry/wet process was confirmed by electrical testing of the dual layer metal structure where good Rc via performance and improved lateral capacitance was demonstrated. Further studies are required for the dimethyl sulphoxide products to determine the cleaning performance in an integrated structure. ACKNOWLEDGEMENT
The authors wish to thank D. Fauchery for the SEM observations and are grateful to G. Passemard and E. Tabouret for fntitful discussions and assistance with the experiments. We also like to thank R. Garcia Santana for support.
Count ~:1 25 ~1
4. C O N C L U S I O N
-
2O
REFERENCES
15 10
1.
5 0
6O
70
80
90 100 Capaci~nce(pF/m)
110
120
2. 3.
Figure 8 ." Lateral capacitance comparison between standard IMD oxide and HSQ F O X sandwich structure.
4.
J. Parasczak, D. Edelstein, S. Cohen, E. Babich and J. Hummel : IEDM 1993, p. 261-264. R. K. Laxman : Semiconductor International (May 1995), p. 71-74. M. Telford : European Semiconductor, (Sep. 1997) p. 11-12. F. Pires, P. Noel, C. Lecornec, G. Passemard, D. Louis, E. Lajoinie : MAM 1997, p. 68.