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Potential modeling and performance analysis of junction-less quadruple gate MOSFETs for analog and RF applications
Microelectronics Journal 66 (2017) 89–102
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Potential modeling and performance analysis of junction-less quadruple gate MOSFETs for analog and RF applications Akash Singh Rawat, Santosh Kumar Gupta
MARK
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Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, 211004, India
A B S T R A C T In this paper, a quasi-3-D analytical model for Junction-less quadruple MOSFET is presented. The model is developed based on an equivalent number of gates by solving two 2-D Poisson's equations instead of solving complex full 3-D Poisson's equation considering it as two double gate MOSFETs. The model is verified for different channel length, height (or width), oxide thickness, doping concentration, and bias voltages. The presented device is then analysed for digital, analog and RF performance parameters using numerical computations. It has been shown in the paper that the JLQG provides improved gain and SCEs with increase of channel length and decrease in height (or width), oxide thickness and doping concentration whereas a higher cut-off frequency is obtained by decreasing channel length and increase in height (or width), oxide thickness and doping concentration. The doping affects the device performance parameters the most.
1. Introduction MOSFET dimension has been continuously scaled down since its introduction called scaling, without much change in basic structure results in an increase in leakage current in terms of SCEs. Reduction in SCEs requires a change in the conventional MOSFET structure. Multigate MOSFET is one of the front runners for next generation MOSFET structures [1]. Multi-gate has better short channel control at sub-nano meter range [2]. Since device dimension is shrinking, the ultra-sharp doping of source and drain impose technology and budget limitations. Junction-less MOSFET has been reported to avoid these problems [3]. The distinct property of junction-less is its homogenous doping profile from source to drain including channel region which makes its fabrication simpler at sub-nanometre range [4]. In addition to above said benefits, it has higher sub-threshold swing and higher ON current with constant OFF current making its ratio further better compared to conventional junction based MOSFETs [5]. Due to all the above advantages, it's important to propose a model which describes its electrostatic potential and which lays a foundation for its electrical properties. A number of research papers have been published for junction less devices [6–11]. Ashkhen Yesayan et al. [6] and Guang-Ming et al. [7] presented channel potential of double gate junction-less MOSFETs. Te-Kuang [8] presented a model for subthreshold swing based on solution of complex 3-D Poisson's equation which requires complex hyperbolic function solutions. Ying Xiao et al. [9] presented subthreshold model current based on a solution of 2-D
⁎
Corresponding author. E-mail addresses: [email protected] (A.S. Rawat), [email protected] (S.K. Gupta).
http://dx.doi.org/10.1016/j.mejo.2017.06.004 Received 16 June 2016; Received in revised form 12 May 2017; Accepted 8 June 2017 0026-2692/ © 2017 Elsevier Ltd. All rights reserved.
Poisson's equation for Junctionless cylindrical gate MOSFETs, but this model fails for larger channel lengths since device is 3-dimentional. Zebang Guo [10] presented model for short channel junction less triple gate MOSFETs. In this paper, 3-D Poisson's equation is solved using two 2-D Poisson's equation for Junctionless quadruple gate (JLQG) MOSFETs, which decreases the complexity of 3-D Poisson's equation based on equivalent number of gates (ENG) method [12–22]. The Poisson's equation is then solved for the equation of electrostatic potential in the middle of the channel. The model is validated and agreed with a good degree from numerical simulation for different electrical condition like source/drain voltage and device parameters such as channel length, gate oxide thickness, doping concentration. None of above papers investigates its analog and RF performance, whereas this paper also presents its scope in analog and RF performance. The effect on digital, analog and RF parameters by varying the channel length, height (or width), width, donor concentration and oxide thickness has been tabulated and presented. 2. Device structure and simulation setup The schematic diagram of the Junction-less Quadruple Gate (JLQG) MOSFET with rectangular cross section is shown in Fig. 1. The JLQG MOSFET has uniform doping concentration for source, channel and drain with N+-N+-N+ structure and gate is P+ poly-silicon with work function 5.2 eV. The physical dimensions of the structure are adopted
Microelectronics Journal 66 (2017) 89–102
A.S. Rawat, S.K. Gupta
Fig. 1. n-type JLQG MOSFET: (a) 3-D view and 2-D cross-sectional views along planes (b) x-y (c) z-x and (d) y-z.
(SRH) recombination model and Boltzmann transport model have been used to simulate the current and the electrostatics of the device. Quantum mechanical effect has not been considered in the simulations and model. The used models are sufficient and necessary to capture the true electrical characteristics of JLQG MOSFETs. The analog and RF simulation is performed to examine the impact of variation of device parameters on small signal analog and RF Figures of Merits (FOMs) including transconductance, transconductance generation factor, intrinsic gain, output conductance, and unity-gain cut-off frequency (fT) calculated using the expressions as shown by Table 6. The RF FOM (fT) has been calculated using the Cgs and Cgd which also include the parasitic capacitances [23]. The parasitic resistance of source/drain and channel regions has not been taken into account because of high doping. This assumption over estimates the fT. The gate is also assumed to offer negligible resistance for calculation of fT (Table 1).
Table 1 Parameters taken for modeling and numerical calculations. Device parameter
Values
Channel length (Lch, nm) Channel width (Wsi, nm) Channel height (Hsi, nm) Oxide thickness (tox, nm) Source/Drain/Channel doping
20, 30, 40, 50, 60 10 10, 12, 14, 16, 18 1, 1.5, 2, 2.5, 3
5×1018,1×1019,1. 5×1019,2×1019,2. 5×1019
(Nd, cm−3 ) Gate work function (∅G , eV ) Lattice temperature (0K)
5.2 300
with following specifications: channel length (Lch) is 20 nm, silicon height (Hsi) is 10 nm, silicon width (Wsi) is 10 nm, oxide thickness (tox) is 2 nm, donor concentration (Nd) is 1 × 1019 cm−3, lattice temperature is 300 K and source (drain) extensions of 5 nm each. The device design parameters are varied one by one keeping other specifications same to study the short channel effects, analog and RF performance parameters of JLQG MOSFET. The simulations are carried out using commercially available Silvaco ATLAS device simulation tool, which is commonly used to characterize the electrical properties of the semiconductor devices. In simulation Lombardi CVT Model, field-dependent mobility (FLDMOB), concentration dependent mobility (CONMOB), Shockley-Read-Hall
3. Model development JLQG MOSFET shown by Fig. 1(a) can be viewed as two separate Junction-lessdouble gate (JLDG) MOSFETs in z-x and y-z planes as shown in Fig. 1(c) and (d) respectively. So, we can analyze JLQG using the equivalent number of gates (ENG) method [12–20]. The characteristics length λQG of JLQG can be calculated using 90
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Fig. 2. Center potential along channel for different (a) channel length (b) height (or width) (c) oxide thickness (d) concentration (e) drain voltage and (f) gate voltage.
1 1 1 = 2 + 2 2 λQG λDGzx λDGyz
(1)
where λDGzx and λDGyz are the characteristics length of the JLDG MOSFETs in z-x and y-z planes. Considering the JLDG MOSFET of z-x plane (also similarly for y-z plane) the characteristics length is calculated solving following 2-D Poisson's equation:
−qNd ∂2ϕ (z , x ) ∂2ϕ (z , x ) = + 2 εsi ∂z 2 ∂x
(2)
Where Nd is the donor concentration; ϕ (x, z) is the potential in the channel; εsi is the permittivity of the silicon; q is the unit charge in coulombs. Assuming the parabolic potential approximation [21,22] in the x direction
ϕ (z , x ) = c0 (z) + c1 (z) x + c2 (z) x 2
ϕ (0, z ) = ϕs (z )
(4)
ϕ (Wsi, z ) = ϕs (z )
(5)
W ϕ ⎛ si , z ⎞ = ϕc (z ) ⎝ 2 ⎠
(6)
Cox (ϕs (z ) − VGS − VFB ) ∂ϕ(z , x ) x=0= εsi ∂x
(7)
Cox (ϕs (z ) − VGS − VFB ) ∂ϕ(z , x ) x = Wsi = − ∂x εsi
(8)
∂ϕ (z , x ) W x = si = 0 2 ∂x
(9)
εox tox
and VFB = ϕM − ϕSi which is flat band voltage where Cox = using Eq. (4) which states that at x = 0 the potential is equal to the surface potential, gives
(3)
c0 (z), c1 (z), c2 (z) are constants to be determined by using the following boundary conditions:
c0 (z) = ϕs (z ) 91
(10)
Microelectronics Journal 66 (2017) 89–102
A.S. Rawat, S.K. Gupta
Table 2 SCE parameters of JLQG for different channel lengths. Channel Length (nm)
SS (mV/decade)
20 30 40 50 60
IOFF ( ×10−18 A/um)
ION (×10−6 A/um)
ION/IOFF ratio (×1012 )
DIBL (mV/V)
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
68.395 62.850 61.325 60.616 60.256
69.660 62.873 61.224 60.494 60.139
157 3.35 2.14 0.499 0.340
905 6.77 3.01 2.26 1.50
5 . 42 4.15 3.36 2.82 2.42
11. 2 8.90 7.48 6.36 5.50
345 1.24 1.57 5.65 7.12
123 1.31 2.49 2.82 3.67
52.8956 22.646 15.044 12.117 11.14
Table 3 SCE parameters of JLQG for different channel height (or width). Channel Height (nm)
SS (mV/decade)
10 12 14 16 18
IOFF (×10−15 A/um)
ION (×10−6 A/um)
ION/IOFF (×109 )
DIBL (mV/V)
VDS = 0.1 V
VDS=1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
68.395 70.555 73.297 75.834 78.733
69.660 72.609 76.805 81.284 87.358
0. 157 1.60 13.9 71.4 231
0. 905 6.38 75.9 476 2250
5 . 42 6.50 7.59 8.67 9.76
11. 2 13.7 16.3 18.9 97.6
34. 5 4.07 0.545 0.121 0.04.22
12. 3 2.15 0.214 0.0396 0.00953
52.8956 62.081 73.128 80.069 87.824
Table 4 SCE parameters of JLQG for different oxide thickness (tox). tox (nm)
1.0 1.5 2.0 2.5 3.0
Sub-threshold Swing (mV/decade)
IOFF (×10−15 A/um)
ION (×10−6 A/um)
ION/IOFF (×109 )
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
63.987 66.075 68.395 71.18 74.418
64.24 66.732 69.661 73.411 78.2
0.00969 0.0133 0.157 2.06 20
0.00308 0.125 0.905 8.84 118
5.38 5.40 5.42 5.42 5.43
9.73 10.6 11.2 11.7 12
555 408 34.5 2.64 0.272
3160 84.4 12.3 1.32 0.102
DIBL (mV/V)
29.371 39.941 52.896 64.881 76.453
Table 5 SCE parameters of JLQG for different doping concentration (Nd). Nd (×10 19 cm−3)
0.5 1.0 1. 5 2. 0 2.5
SS (mV/decade)
IOFF (×10−15 A/um)
ION (×10−6 A/um)
ION/IOFF (×109 )
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
67.168 68.395 72.304 105.828 299.644
68.298 69.661 75.111 131.815 325.08
0. 0000221 0.157 30.3 10500 2590000
0. 000142 0.905 177 61200 14600000
3. 62 5.42 7.10 8.73 10.3
6 . 21 1.12 16.4 21.9 27.7
16400 34.5 0.234 0.0000219 0.0000039
4370 12.3 0.0924 0.000358 0.0000019
using Eq. (7) which states at x = 0 the electric field can be written as ∂ϕ (0, z)/ ∂z = (Cox / εsi )(ϕs (z ) − VGS + VFB ) , gives
c1 (z) =
Cox (ϕ (z ) − VGS + VFB ) εsi s
Cox (ϕs (z ) − VGS + VFB ) εsi Wsi
is
(11)
∂z2
of
the
2 −λQG (VGS
ϕc (z) = Ae λQG z + Be−λQG z −
form
qNd . εsi
− VFB ) − boundary conditions:
βQG λQG 2
where
βQG =
Constants A and B can be calculated using the
Potential at source terminal is Vs : ϕc (0) = VS
(14a)
Potential at drain terminal is VD : ϕc (L) = VD
(14b)
(12)
c0 (z), c1 (z), c2 (z) are substituted in the Eq. (3) and from this the center potential can be calculated by putting x = Wsi/2 , gives ∂2 (ϕc (z))
43.986 52.896 57.702 63.882 69.052
length of y-z plane JLDG can be calculated to be λDGyz = 8{Cox /[Hsi (4εsi + Hsi Cox )]} . From Eq. (1) we can calculate the λQG and the solution of Eq. (2)
using Eq. (8) which states that at x = Wsi the electric field can be written as ∂ϕ (Wsi, z)/ ∂z = − (Cox / εsi )(ϕs (z ) − VGS + VFB ) , gives
c2 (z) = −
DIBL (mV/V)
Using Boundary conditions of (14a) and (14b) we get, constants A and B are calculated as:
qN 8Cox (VGS − VFB ) 8Cox − ϕ (z) = − d − εsi wx (4εsi + Wsi Cox ) c wx (4εsi + Wsi Cox ) (13)
From Eq. (13) the characteristic length of z-x plane JLDG is λDGxz = 8{Cox /[Wsi (4εsi + Wsi Cox )]} and similarly characteristic 92
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Fig. 3. (a) ID vs. VGS (b) gm1 vs. VGS (c) ID and gd vs. VDS (d) TGF vs. VGS (e) VEA vs. VGS and (f) AV vs. VGS at VDS = 1 V for different channel length.
A=
B=
βQG ⎞ ⎛ βQG ⎞ ⎛ −λQGL ⎜VD + λ 2 ⎟ − ⎜VS + λ 2 ⎟e QG ⎠ ⎝ QG ⎠ ⎝ e−λQGL(e2λQGL − 1) βQG ⎞ ⎛ βQG ⎞ ⎛ λQGL ⎜VD + λ 2 ⎟ − ⎜VS + λ 2 ⎟e QG ⎠ ⎝ QG ⎠ ⎝ e λQGL(e−2λQGL − 1)
4. Model verification
and
In Fig. 2(a), Center potential variation for different channel lengths (20 nm, 30 nm and 40 nm) has been shown. It is observed that for short channel lengths the analytical values are well matched with the numerically calculated values obtained from Silvaco ATLAS device
(15) 93
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Fig. 4. (a) ID vs. VGS (b) gm1 vs. VGS (c) ID and gd vs. VDS (d) TGF vs. VGS (e) VEA vs. VGS and (f) AV vs. VGS at VDS = 1 V for different channel height (or width).
5. Results and discussion
simulator. In Fig. 2(b) Center potential variation for different heights (10 nm, 12 nm, 14 nm, 16 nm and 18 nm) has been shown for channel length 20 nm. In Fig. 2(c) Center potential variation for different oxide thickness (1 nm, 1.5 nm, 2 nm, 2.5 nm and 3 nm) have been shown for channel length 20 nm. In Fig. 2(d) Center potential variation for different donor concentrations in the channel region (5 × 1018 cm−3, 1 × 1019 cm−3, 1.5 × 1019 cm−3, 2 × 1019 cm−3, 2.5 × 1019 cm−3) have been shown for channel length 20 nm. In Fig. 2(e) Center potential variation for different drain voltages (VDS = 0 V, 0.5 V, 1.0 V) have been shown for channel length 20 nm. In Fig. 2(f) Center potential variation for different gate voltages (VGS = 0 V, 0.25 V, 0.5 V) have been shown for channel length 20 nm. All the results presented show that the developed model is in good agreement with the numerically obtained data.
In this section we present the digital, analog and RF parameter variations based on the results obtained from numerical calculation using the ATLAS device simulator. Appropriate models have been chosen and applied to capture the effects affecting the device performance. Subsections 5.1, 5.2 and 5.3 present the short channel effects, analog and RF performance parameters respectively. 5.1. Short channel effects (SCEs) In this subsection the SCE parameters of JLQG for variations of physical dimensions have been discussed. Table 2 presents the SCE parameters for different channel length of JLQG MOSFET. Subthreshold swing (SS) decreases with increase in the channel length due to increase in the oxide capacitance which increases the control of gate over the channel. ION/IOFF ratio increases with increase in the channel 94
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Fig. 5. (a) ID vs. VGS (b) gm1 vs. VGS (c) ID and gd vs. VDS (d) TGF vs. VGS (e) VEA vs. VGS and (f) AV vs. VGS at VDS = 1 V for different gate oxide thickness.
between them. Table 3 represents the SCE parameters for different heights (or widths) of JLQG. SS is observed to increase with the increase of height (or width) as SS is directly dependent on the depletion capacitance and
length even when there is decrement in due to increase in the resistance of the channel because decrement in IOFF is much more than decrease in ION. DIBL is decreasing as the channel length increases because effect of the drain on the source side barrier is reduced due to increased distance
95
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Fig. 6. (a) ID vs. VGS (b) gm1 vs. VGS (c) ID and gd vs. VDS (d) TGF vs. VGS (e) VEA vs. VGS and (f) AV vs. VGS at VDS = 1 V for different concentration.
same. Table 4 summarizes the SCEs parameters for different gate oxide thickness (tox). SS increases with increase of gate oxide thickness (tox) due to reduction of gate control over the channel. Also, ION/IOFF decreases because IOFF increases much faster than ION as tox is increased due to the reduction in gate control over channel. DIBL increases
as height is increased the area and hence depletion capacitance also increases which increases Sub-threshold slope. ION/IOFF decreases with increase in the height (or width) even with increase of ION due to increase in the cross sectional area but the IOFF increases faster. DIBL increases with the height (or width) increase because of the fact the control of the top gate reduces whereas the effect of the drain remain 96
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resistance. MOS analog circuits require transistors with lower gd in order to achieve higher gain. Dependence of analog performance on oxide thickness is shown by Fig. 5. Fig. 5(a) shows increase in OFF current with increase of tox since control of gate reduces and lowering of barrier height. Whereas, ON current does not increase in same proportion resulting in decrease of ION/IOFF ratio. So, smaller values of tox should be chosen for higher ION/ IOFF ratio. gm1 for higher oxide thickness is high till VGS = 0.8 V but after that it starts increasing for lower tox and maximum peak is observed at the low tox (1 nm) at VGS = 1.08 V as shown by Fig. 5(b). Also, the peak values of gm1 decrease at higher tox. As tox increases, gd increases (i.e. output resistance decreases) reducing the gain represented by Fig. 5(c). Fig. 5(d–f) show the variation of TGF, early voltage (VEA) and intrinsic gain (AV) as a function of VGS respectively. TGF decreases as oxide thickness increases i.e. gain available per unit power dissipation reduces. Peak value reduces by 14.3% from 1 nm to 3 nm oxide thickness. Early voltage is high for the low oxide thickness but at the middle range of gate voltages high oxide thickness have high early voltage but after VGS = 0.9 V again low oxide thickness value starts increasing and peak value decreases by 15.4% from 1 nm to 3 nm. Gain reduces with gate oxide thickness. For tox = 2 nm the gain is more than tox = 1.5 nm till VGS = 0.4 V after that gain at 1.5 nm is more than that of 2 nm. Peak value of gain reduces by 29% from 1 nm to 3 nm oxide thickness. From Fig. 6(a) it is observed that ID increases as concentration increases because the drain current is directly proportional to free carriers (i.e. concentration). But, ON current does not increase as much as OFF current increases resulting in a decrease of ION/IOFF ratio. So, doping concentration should be kept high for higher drain current and less for higher ION/IOFF ratio. Higher trans-conductance is preferable for analog applications because it increases carrier transport efficiency. But as we increase concentration, trans-conductance increases due to increase in drain current as shown by Fig. 6(b). As concentration increases, gd also increases resulting into decrease in output resistance shown by Fig. 6(c). MOS analog circuits require transistors with lower gd in order to achieve higher gains. Fig. 6(d–f) shows the variation of TGF, VEA and AV respectively. TGF decreases as the concentration increases. The peak value reduces by 22.4% from 5.0 × 1018 cm−3 to 2.5 × 1019 cm−3 doping concentration i.e. gain per unit power deteriorates. Early voltage increases with doping concentration increase and peak value increases by 30% from 5.0 × 1018 cm−3 to 2.5 × 1019 cm−3 doping concentration. Gain at high VGS is high for the low doping concentrations but as VGS is reduced the gain at lower doping concentration starts dominating.
Table 6 Formulae used for calculation of analog and RF parameters. Parameters
Formula used
Transconductance ( gm1)
gm1 =
Transconductance generation factor (TGF) Output conductance ( gd )
TGF =
Intrinsic gain (AV)
AV =
Early voltage (VEA)
VEA =
Cut-off-frequency ( fT )
fT =
gd =
δID δVGS gm1 ID
δID δVDS gm1
gd ID gd gm1
2πCgs 1 + 2
Gain frequency product (GFP) Transconductance frequency product (TFP) Gain transconductance frequency product (GTFP)
GFP = ⎛ ⎝ TFP =
gm1 ⎞ gd ⎠
g ⎛ m1 ⎞ ⎝ gd ⎠
GTFP = ⎛ ⎝
Cgd Cgs
≈
gm1 2π (Cgs + Cgd)
× fT = AV × fT × fT
gm1 ⎞ gd ⎠
×⎛ ⎝
gm1 ⎞ Id ⎠
× fT = AV ×TFP
because influence of drain bias (VDS) increases with tox. SS increases with increase in doping concentration shown by Table 5. ION/IOFF ratio decreases with increase in the concentration even when ION increases due to increase in the doping concentration but IOFF increases even faster. DIBL also increases with increase in concentration. Tables 2–5 demonstrate that for good digital characteristics and lower SCEs; lower channel length, lower channel height (or width), lower gate oxide thickness and lower doping concentrations can be chosen suitably. Looking at the variation of different SCE parameters it is revealed that the doping concentration affects the device performance the most. 5.2. Analog performance Fig. 3 shows variation of analog performance for different channel length. From Fig. 3(a), it is observed that as channel length decreases; drain current increases because the drain current is inversely proportional to channel length. But, OFF current increases more as compared to ON current, results in decrease in ION/IOFF as shown by Table 2. So, lower channel length should be taken for higher drain current and large high ION/IOFF ratio. Higher trans-conductance is preferable for analog applications because it shows higher carrier transport efficiency. Fig. 3(b) shows decrease of trans-conductance with increase in channel length. A decrease of 26% in peak value of gm1 is observed when channel length is increased from 20 nm to 60 nm. As channel length increases, gd decreases resulting into increase in output resistance as shown by Fig. 3(c). MOS analog circuits require transistors with lower gd in order to achieve higher gains. Fig. 3(d–f) show the variations of trans-conductance generation factor (TGF), early voltage (VEA) and intrinsic gain (AV) as a function of VGS respectively. TGF is defined as the available gain per unit value of the power dissipation so its higher value is desirable to get high gain for a given power. VEA is the measure of the output resistance and for higher gain, a higher value of VEA is desired. This also leads to higher intrinsic gain required for amplification. Fig. 4 shows analog performance of JLQG MOSFET by varying channel height (or width). In Fig. 4(a), drain current variation with VGS has been shown for different silicon thickness i.e. channels height. It is observed that as height (or width) increases drain current also increases because drain current is directly proportional to cross section area of channel. But, ON current increment is offset by an increase in OFF current resulting in decrease of ION/IOFF ratio. Fig. 5(b) shows the increase of trans-conductance with height (or width) due to increase in drain current. In Fig. 5(c), drain current and output conductance increases as height (or width) increases resulting into decrease in output
5.3. RF performance In this subsection we present the RF performance of JLQG MOSFETs. The performance parameters have been calculated using the formulae listed in Table 6. In Fig. 7(a), the Cgs and Cgd has been computed numerically setting AC small signal analysis at 1 MHz frequency with DC solutions obtained at VDS = 1 V. Both Cgs and Cgd of device increases with increase of channel length resulting into lower switching speed. But cut-off frequency increases as channel length decreases and 300% increase in fT is observed when channel length is decreased from 60 nm to 20 nm as shown by Fig. 7(b). Other performance parameters like gain frequency product (GFP), trans-conductance frequency product (TFP) and gain trans-conductance frequency product (GTFP) are also essential for amplifiers for high frequency operations with higher values. In Fig. 7(c), the GFP increases with decrease of channel length from 60 nm to 30 nm; but as the channel length is reduced to 20 nm, it reduces due to reduction of intrinsic gain (Fig. 3(f)). The highest value of GFP is obtained around VGS = 0.8 V for 30 nm whereas it is high for 20 nm up to VGS = 0.64 V. At higher gate voltage again GFP of 20 nm channel length start dominating and is higher as compared to other channel lengths because GFP is the product of gain and cut off 97
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Fig. 7. (a) Cgs and Cgd (b) cut-off frequency (c) GFP (d) TFP and (e) GTFP vs. VGS at VDS = 1.0 V for different channel lengths.
increases in peak value is observed for 20 nm to 60 nm change in channel length. This is due to the fact that for higher channel lengths gain is higher and dominates. Fig. 8(a) shows Cgs and Cgd of device to increase with increase in height (or width) due to increase in total gate area. The cut-off
frequency, and intrinsic gain and fT show opposite behavior with the increase of the channel length. TFP in Fig. 7(d) decreases with channel length increase. A decrease of 76% in peak TFP is observed as channel length is increases from 20 nm to 60 nm as inferred from graph. In Fig. 7(e), GTFP increases with channel length increase and 89%
98
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Fig. 8. (a) Cgs and Cgd (b) cut off frequency (c) GFP d) TFP and (e) GTFP vs. VGS at VDS = 1.0 V for different channel height (or width).
frequency increases as height (or width) is increased because gm increases much more compared to the capacitances; but at higher VGS the cut off frequency for different values of height (or width) tend to approach same value. The peak value of the cut-off frequency reduces by 1.2% from 10 nm to 18 nm height as shown by Fig. 8(b). GFP is more for the higher height (or width) up to VGS = 0.63 V but after that lower height (or width) value start dominating as represented by Fig. 8(c). At
VGS = 0.94 V maximum value of GFP is observed at 10 nm height and a decrement of 34% in peak value from 10 nm to 18 nm as inferred from above plots. This is due to the fact that gain at lower height is more whereas cut off frequency is less at low VGS but at higher VGS the cut off frequency become same. TFP of larger height (18 nm) is large up to VGS = 0.52 V after that lower height values start to dominate and maximum peak is observed at VGS = 0.7 V for 10 nm and the peak value decreases 99
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Fig. 9. (a) Cgs and Cgd vs. gate voltage (b) cut off frequency vs. gate voltage (c) GFP vs. gate voltage (d) TFP vs. gate voltage (e) GTFP vs. gate voltage for different oxide thickness at VDS = 1.0 V.
more till VGS = 0.5 V after that lower height values start dominating it and maximum peak is found at VGS = 0.72 V for 10 nm and peak value reduces by 61% from 10 nm to 18 nm. Fig. 9(a) shows Cgd of device to increase with decrease in the tox. Cgs for large tox (i.e. 3 nm) is low at lower gate voltages up to VGS = 0.18 V
by 30.3% from 10 nm to 18 nm height as shown by Fig. 8(d). This is due to fact that TGF (Fig. 4(d)) is almost constant at lower gate voltages and decreases as the gate voltage increases whereas cut off frequency increases. TGF decreases with increase in the height and cut off frequency increases with height. GTFP shown by Fig. 8(e) of the higher height is 100
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Fig. 10. (a) Cgs and Cgd (b) cut-off frequency (c) GFP (d) TFP and (e) GTFP for different doping at VDS = 1 V.
value is observed at low oxide thickness at VGS = 0.98 V and maximum value reduces by 59.5% from 1 nm to 3 nm. In Fig. 9(d), TFP of high oxide thickness is more for low gate voltage till VGS = 0.58 V after that thin tox starts dominating and maximum value is found at VGS=0.82 V for the tox = 1 nm. The peak value of TFP reduces by 19.5% from 1 nm
after that it is dominated by lower tox up to VGS = 0.74 V and once again thin tox starts dominating and maximum value is found for lower tox. Cut off frequency shown by Fig. 9(b) is higher for large tox due to lower capacitances. In Fig. 9(c), GFP of high tox is more at low voltage till VGS = 0.64 V after that it starts increasing for low tox. Maximum 101
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concentration result in higher cut-off frequency. TFP, GFP and GTFP peak values reduce as the donor concentration increases. In short, for good digital, analog and RF characteristics; lower channel length, lower channel height (or width), lower gate oxide thickness and lower doping concentrations should be chosen. The doping concentration affects the device performance parameters most and should be carefully chosen.
to 3 nm. In Fig. 9(e), peak value of the GTFP reduces by 73.9% from 1 nm to 3 nm oxide thickness; maximum peak value is found for the 1 nm oxide thickness at VGS = 0.82 V. Peak value for the higher oxide thickness shifts toward lower gate voltages. In Fig. 10(a) variation of Cgs and Cgd w.r.t. gate voltage has been shown at VDS = 1 V. The Cgs of device increases with increase in doping concentration resulting into lower switching speed. But cut off frequency increases with doping concentration as represented by Fig. 10(b). In Fig. 10(c) GFP for higher doping concentration is more at the lower VGS but as VGS increases the lower doping concentration GFP starts increasing and maximum value is found at lower concentration and high VGS. This is due to the fact GFP is the product of gain and cut off frequency; gain and cut off frequency is low for low concentration but at high gate voltage gain of the lower concentration dominates and the difference in cut off frequency at different concentration also decreases. Figs. 10(e) and (f) representing TFP and GTFP show unique behavior for different concentrations having peaks at different VGS and peaks are found at higher VGS for lower concentrations. Maximum value of GFP, TFP and GTFP reduces by 40.1%, 38.2% and 59.5% respectively when doping concentration is changed from 5.0 × 10 18 cm−3 to 2.5 × 1019 cm−3.
References [1] ITRS-International Technology Roadmap for Semiconductors, 2013. [2] J.P. Colinge, Multi-gate SOI MOSFETs, Solid-State Electron. 48 (2004) 897–905. [3] C.W. Lee, et al., Junctionless multigate field-effect transistor, Appl. Phys. Lett. 94 (5) (2009) 053511. [4] J.P. Colinge, Nanowire transistor without junctions, Nat. Nanotechnol. 5 (3) (2009) 225–229. [5] C.W. Lee, S.R.N. Yun, C.G. Yu, J.T. Park, J.P. Colinge, Device design guidelines for nano-scale MuGFETs, Solid-State Electron. 51 (2007) 505–510. [6] Ashkhen Yesayan, Farzan Jazaeri, Jean-Michel Sallese, Charge based modeling of double gate and nanowire junctionless FETs including interface –trapped charges, IEEE Trans. Electr. Dev. 63 (3) (2016) 1368–1374. [7] Guang-Ming Zhang, Yi-Kai Su, Hsin-Yi Hsin, Yao-Tsung Tsai, Double gate junctionless MOSFET simulation and comparison with analytical model, in: IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 2013. [8] Te-Kuang, A new subthreshold current model for junctionless trigate MOSFETs to examine interface trapped charge effects, IEEE Trans. Electron Devices 62 (9) (2015). [9] Ying Xiao, Baili Zhang, Haijun Lou, Lining Zhang, Xinnan Lin, A compact model of subthreshold current with source/drain depletion effect for the short-channel junctionless cylindrical surrounding-gate MOSFETs, IEEE Trans. Electron Devices 63 (5) (2016) 2176–2181. [10] Zebang Guo, Jinyu Zhang, Zuochang Ye, Yan Wang, 3-D analytical model for shortchannel triple-gate Junctionless MOSFETs, IEEE Trans. Electron Devices 63 (10) (2016). [11] J.P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, Berlin, 2008. [12] N. Chevillon, J.M. Sallese, C. Lallement, F. Pregaldiny, M. Madec, J. Sedlmeir, J. Aghassi, Generalization of the concept of equivalent thickness and capacitances to multigate MOSFETs modeling, IEEE Trans. Electron Devices 59 (1) (2012) 60–71. [13] M.J. Kumar, A.A. Orouji, D. Harshit, New dual-material SG nanoscale MOSFET: analytical threshold-voltage model, IEEE Trans. Electron Devices 53 (2006) 920–923. [14] B. Yu, J. Song, Y. Yuan, W.Y. Lu, Y. Taur, A unified analytic drain-current model for multiple-gate MOSFETs, IEEE Trans. Electron Devices 55 (2008) 2157–2163. [15] C.W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, J.-P. Colinge, Junction-less multigate field-effect transistor, Appl. Phys. Lett. 94 (5) (2009) 053511. [16] J.P. Colinge, C.-W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, Nanowire transistors without junctions, Nat. Nanotechnol. 5 (3) (2010) 225–229. [17] Nirmal Ch. Roy, Abhinav Gupta, Sanjeev Rai, Analytical surface potential modeling and simulation of junction-lessdouble gate (JLDG) MOSFET for ultra low-power analog/RF circuits, Microelectron. J. 46 (2015) 916–922. [18] T.K. Chiang, A novel scaling theory for fully depleted, multiple gate MOSFET, including effective number of gates (ENGs), IEEE Trans. Electron Devices 61 (2014) 631–633. [19] Visweswara Rao Samoju, Sarvesh Dubey, Pramod Kumar Tiwari, Quasi-3D subthreshold current and subthreshold swing Models of Dual-Metal Quadruple-Gate (DMQG) MOSFETs, J. Comput. Electron. 14 (2015) 582–592. [20] T.K. Chiang, A novel quasi-3D threshold voltage model for fully depleted quadruple-gate (FDQG) MOSFETs: with equivalent number of gates (ENG) included, IEEE Trans. Nanotechnol. 12 (2013) 1022–1025. [21] T.K. Chiang, A new interface trapped charge degraded sub threshold current model for quadruple-gate MOSFETs, IEEE Trans. Electron Devices 61 (2014) 1611–1614. [22] K.K. Young, Short channel effects in fully depleted SOI MOSFET, IEEE Trans. Electron Devices 36 (1989) 399. [23] Angsuman Sarkar, Study of RF performance of surrounding gate MOSFET with gate overlap and underlap, Adv. Nat. Sci.: Nanosci. Nanotechnol. 5 (2014) 035006.
6. Conclusion In this work, center potential based on ENG for JLQG MOSFET is developed and its analog/RF performance is investigated for different channel lengths, height (or width), gate oxide thickness and doping concentrations. We report improvement in various parameters such as subthreshold swing, ION/IOFF ratio, IOFF and DIBL with channel length increment, height (or width) decrement, oxide thickness decrement and doping concentration decrement. The ION increases with channel length decrement, height (or width) increment, oxide thickness increment and doping concentration increment. As the channel length increases the analog parameters such as intrinsic gain, TGF, early voltage increases. Increase in channel length results in higher capacitances (Cgs and Cgd) which decreases cut-off frequency, TFP and GFP. But an increase in GFP is observed when channel length is increased from 20 nm to 30 nm. GTFP peak value increases with channel length. As the height (or width) increases the analog parameters such as intrinsic gain and TGF decreases whereas the peak value of the early voltage reduces. Increase in height (or width) result in higher capacitances (Cgs and Cgd) and a high cut-off frequency because gm1 increases much more compared to the capacitances. TFP, GFP and GTFP peak values reduce as the height (or width) increases. With oxide thickness increase, analog parameters such as intrinsic gain and TGF decrease whereas the peak value of the early voltage reduces. Increase in oxide thickness results in lower Cgs and Cgd which gives higher cut-off frequency. TFP, GFP and GTFP peak value reduces with oxide thickness increase. As the oxide thickness increases the analog parameters such as intrinsic gain and TGF decrease whereas the peak value of the early voltage reduces. As the donor concentration increases the analog parameters such as TGF and intrinsic gain decrease whereas early voltage increases. Increase in donor
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Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Potential modeling and performance analysis of junction-less quadruple gate MOSFETs for analog and RF applications Akash Singh Rawat, Santosh Kumar Gupta
MARK
⁎
Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, 211004, India
A B S T R A C T In this paper, a quasi-3-D analytical model for Junction-less quadruple MOSFET is presented. The model is developed based on an equivalent number of gates by solving two 2-D Poisson's equations instead of solving complex full 3-D Poisson's equation considering it as two double gate MOSFETs. The model is verified for different channel length, height (or width), oxide thickness, doping concentration, and bias voltages. The presented device is then analysed for digital, analog and RF performance parameters using numerical computations. It has been shown in the paper that the JLQG provides improved gain and SCEs with increase of channel length and decrease in height (or width), oxide thickness and doping concentration whereas a higher cut-off frequency is obtained by decreasing channel length and increase in height (or width), oxide thickness and doping concentration. The doping affects the device performance parameters the most.
1. Introduction MOSFET dimension has been continuously scaled down since its introduction called scaling, without much change in basic structure results in an increase in leakage current in terms of SCEs. Reduction in SCEs requires a change in the conventional MOSFET structure. Multigate MOSFET is one of the front runners for next generation MOSFET structures [1]. Multi-gate has better short channel control at sub-nano meter range [2]. Since device dimension is shrinking, the ultra-sharp doping of source and drain impose technology and budget limitations. Junction-less MOSFET has been reported to avoid these problems [3]. The distinct property of junction-less is its homogenous doping profile from source to drain including channel region which makes its fabrication simpler at sub-nanometre range [4]. In addition to above said benefits, it has higher sub-threshold swing and higher ON current with constant OFF current making its ratio further better compared to conventional junction based MOSFETs [5]. Due to all the above advantages, it's important to propose a model which describes its electrostatic potential and which lays a foundation for its electrical properties. A number of research papers have been published for junction less devices [6–11]. Ashkhen Yesayan et al. [6] and Guang-Ming et al. [7] presented channel potential of double gate junction-less MOSFETs. Te-Kuang [8] presented a model for subthreshold swing based on solution of complex 3-D Poisson's equation which requires complex hyperbolic function solutions. Ying Xiao et al. [9] presented subthreshold model current based on a solution of 2-D
⁎
Corresponding author. E-mail addresses: [email protected] (A.S. Rawat), [email protected] (S.K. Gupta).
http://dx.doi.org/10.1016/j.mejo.2017.06.004 Received 16 June 2016; Received in revised form 12 May 2017; Accepted 8 June 2017 0026-2692/ © 2017 Elsevier Ltd. All rights reserved.
Poisson's equation for Junctionless cylindrical gate MOSFETs, but this model fails for larger channel lengths since device is 3-dimentional. Zebang Guo [10] presented model for short channel junction less triple gate MOSFETs. In this paper, 3-D Poisson's equation is solved using two 2-D Poisson's equation for Junctionless quadruple gate (JLQG) MOSFETs, which decreases the complexity of 3-D Poisson's equation based on equivalent number of gates (ENG) method [12–22]. The Poisson's equation is then solved for the equation of electrostatic potential in the middle of the channel. The model is validated and agreed with a good degree from numerical simulation for different electrical condition like source/drain voltage and device parameters such as channel length, gate oxide thickness, doping concentration. None of above papers investigates its analog and RF performance, whereas this paper also presents its scope in analog and RF performance. The effect on digital, analog and RF parameters by varying the channel length, height (or width), width, donor concentration and oxide thickness has been tabulated and presented. 2. Device structure and simulation setup The schematic diagram of the Junction-less Quadruple Gate (JLQG) MOSFET with rectangular cross section is shown in Fig. 1. The JLQG MOSFET has uniform doping concentration for source, channel and drain with N+-N+-N+ structure and gate is P+ poly-silicon with work function 5.2 eV. The physical dimensions of the structure are adopted
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Fig. 1. n-type JLQG MOSFET: (a) 3-D view and 2-D cross-sectional views along planes (b) x-y (c) z-x and (d) y-z.
(SRH) recombination model and Boltzmann transport model have been used to simulate the current and the electrostatics of the device. Quantum mechanical effect has not been considered in the simulations and model. The used models are sufficient and necessary to capture the true electrical characteristics of JLQG MOSFETs. The analog and RF simulation is performed to examine the impact of variation of device parameters on small signal analog and RF Figures of Merits (FOMs) including transconductance, transconductance generation factor, intrinsic gain, output conductance, and unity-gain cut-off frequency (fT) calculated using the expressions as shown by Table 6. The RF FOM (fT) has been calculated using the Cgs and Cgd which also include the parasitic capacitances [23]. The parasitic resistance of source/drain and channel regions has not been taken into account because of high doping. This assumption over estimates the fT. The gate is also assumed to offer negligible resistance for calculation of fT (Table 1).
Table 1 Parameters taken for modeling and numerical calculations. Device parameter
Values
Channel length (Lch, nm) Channel width (Wsi, nm) Channel height (Hsi, nm) Oxide thickness (tox, nm) Source/Drain/Channel doping
20, 30, 40, 50, 60 10 10, 12, 14, 16, 18 1, 1.5, 2, 2.5, 3
5×1018,1×1019,1. 5×1019,2×1019,2. 5×1019
(Nd, cm−3 ) Gate work function (∅G , eV ) Lattice temperature (0K)
5.2 300
with following specifications: channel length (Lch) is 20 nm, silicon height (Hsi) is 10 nm, silicon width (Wsi) is 10 nm, oxide thickness (tox) is 2 nm, donor concentration (Nd) is 1 × 1019 cm−3, lattice temperature is 300 K and source (drain) extensions of 5 nm each. The device design parameters are varied one by one keeping other specifications same to study the short channel effects, analog and RF performance parameters of JLQG MOSFET. The simulations are carried out using commercially available Silvaco ATLAS device simulation tool, which is commonly used to characterize the electrical properties of the semiconductor devices. In simulation Lombardi CVT Model, field-dependent mobility (FLDMOB), concentration dependent mobility (CONMOB), Shockley-Read-Hall
3. Model development JLQG MOSFET shown by Fig. 1(a) can be viewed as two separate Junction-lessdouble gate (JLDG) MOSFETs in z-x and y-z planes as shown in Fig. 1(c) and (d) respectively. So, we can analyze JLQG using the equivalent number of gates (ENG) method [12–20]. The characteristics length λQG of JLQG can be calculated using 90
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Fig. 2. Center potential along channel for different (a) channel length (b) height (or width) (c) oxide thickness (d) concentration (e) drain voltage and (f) gate voltage.
1 1 1 = 2 + 2 2 λQG λDGzx λDGyz
(1)
where λDGzx and λDGyz are the characteristics length of the JLDG MOSFETs in z-x and y-z planes. Considering the JLDG MOSFET of z-x plane (also similarly for y-z plane) the characteristics length is calculated solving following 2-D Poisson's equation:
−qNd ∂2ϕ (z , x ) ∂2ϕ (z , x ) = + 2 εsi ∂z 2 ∂x
(2)
Where Nd is the donor concentration; ϕ (x, z) is the potential in the channel; εsi is the permittivity of the silicon; q is the unit charge in coulombs. Assuming the parabolic potential approximation [21,22] in the x direction
ϕ (z , x ) = c0 (z) + c1 (z) x + c2 (z) x 2
ϕ (0, z ) = ϕs (z )
(4)
ϕ (Wsi, z ) = ϕs (z )
(5)
W ϕ ⎛ si , z ⎞ = ϕc (z ) ⎝ 2 ⎠
(6)
Cox (ϕs (z ) − VGS − VFB ) ∂ϕ(z , x ) x=0= εsi ∂x
(7)
Cox (ϕs (z ) − VGS − VFB ) ∂ϕ(z , x ) x = Wsi = − ∂x εsi
(8)
∂ϕ (z , x ) W x = si = 0 2 ∂x
(9)
εox tox
and VFB = ϕM − ϕSi which is flat band voltage where Cox = using Eq. (4) which states that at x = 0 the potential is equal to the surface potential, gives
(3)
c0 (z), c1 (z), c2 (z) are constants to be determined by using the following boundary conditions:
c0 (z) = ϕs (z ) 91
(10)
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Table 2 SCE parameters of JLQG for different channel lengths. Channel Length (nm)
SS (mV/decade)
20 30 40 50 60
IOFF ( ×10−18 A/um)
ION (×10−6 A/um)
ION/IOFF ratio (×1012 )
DIBL (mV/V)
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
68.395 62.850 61.325 60.616 60.256
69.660 62.873 61.224 60.494 60.139
157 3.35 2.14 0.499 0.340
905 6.77 3.01 2.26 1.50
5 . 42 4.15 3.36 2.82 2.42
11. 2 8.90 7.48 6.36 5.50
345 1.24 1.57 5.65 7.12
123 1.31 2.49 2.82 3.67
52.8956 22.646 15.044 12.117 11.14
Table 3 SCE parameters of JLQG for different channel height (or width). Channel Height (nm)
SS (mV/decade)
10 12 14 16 18
IOFF (×10−15 A/um)
ION (×10−6 A/um)
ION/IOFF (×109 )
DIBL (mV/V)
VDS = 0.1 V
VDS=1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
68.395 70.555 73.297 75.834 78.733
69.660 72.609 76.805 81.284 87.358
0. 157 1.60 13.9 71.4 231
0. 905 6.38 75.9 476 2250
5 . 42 6.50 7.59 8.67 9.76
11. 2 13.7 16.3 18.9 97.6
34. 5 4.07 0.545 0.121 0.04.22
12. 3 2.15 0.214 0.0396 0.00953
52.8956 62.081 73.128 80.069 87.824
Table 4 SCE parameters of JLQG for different oxide thickness (tox). tox (nm)
1.0 1.5 2.0 2.5 3.0
Sub-threshold Swing (mV/decade)
IOFF (×10−15 A/um)
ION (×10−6 A/um)
ION/IOFF (×109 )
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
63.987 66.075 68.395 71.18 74.418
64.24 66.732 69.661 73.411 78.2
0.00969 0.0133 0.157 2.06 20
0.00308 0.125 0.905 8.84 118
5.38 5.40 5.42 5.42 5.43
9.73 10.6 11.2 11.7 12
555 408 34.5 2.64 0.272
3160 84.4 12.3 1.32 0.102
DIBL (mV/V)
29.371 39.941 52.896 64.881 76.453
Table 5 SCE parameters of JLQG for different doping concentration (Nd). Nd (×10 19 cm−3)
0.5 1.0 1. 5 2. 0 2.5
SS (mV/decade)
IOFF (×10−15 A/um)
ION (×10−6 A/um)
ION/IOFF (×109 )
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
VDS = 0.1 V
VDS = 1 V
67.168 68.395 72.304 105.828 299.644
68.298 69.661 75.111 131.815 325.08
0. 0000221 0.157 30.3 10500 2590000
0. 000142 0.905 177 61200 14600000
3. 62 5.42 7.10 8.73 10.3
6 . 21 1.12 16.4 21.9 27.7
16400 34.5 0.234 0.0000219 0.0000039
4370 12.3 0.0924 0.000358 0.0000019
using Eq. (7) which states at x = 0 the electric field can be written as ∂ϕ (0, z)/ ∂z = (Cox / εsi )(ϕs (z ) − VGS + VFB ) , gives
c1 (z) =
Cox (ϕ (z ) − VGS + VFB ) εsi s
Cox (ϕs (z ) − VGS + VFB ) εsi Wsi
is
(11)
∂z2
of
the
2 −λQG (VGS
ϕc (z) = Ae λQG z + Be−λQG z −
form
qNd . εsi
− VFB ) − boundary conditions:
βQG λQG 2
where
βQG =
Constants A and B can be calculated using the
Potential at source terminal is Vs : ϕc (0) = VS
(14a)
Potential at drain terminal is VD : ϕc (L) = VD
(14b)
(12)
c0 (z), c1 (z), c2 (z) are substituted in the Eq. (3) and from this the center potential can be calculated by putting x = Wsi/2 , gives ∂2 (ϕc (z))
43.986 52.896 57.702 63.882 69.052
length of y-z plane JLDG can be calculated to be λDGyz = 8{Cox /[Hsi (4εsi + Hsi Cox )]} . From Eq. (1) we can calculate the λQG and the solution of Eq. (2)
using Eq. (8) which states that at x = Wsi the electric field can be written as ∂ϕ (Wsi, z)/ ∂z = − (Cox / εsi )(ϕs (z ) − VGS + VFB ) , gives
c2 (z) = −
DIBL (mV/V)
Using Boundary conditions of (14a) and (14b) we get, constants A and B are calculated as:
qN 8Cox (VGS − VFB ) 8Cox − ϕ (z) = − d − εsi wx (4εsi + Wsi Cox ) c wx (4εsi + Wsi Cox ) (13)
From Eq. (13) the characteristic length of z-x plane JLDG is λDGxz = 8{Cox /[Wsi (4εsi + Wsi Cox )]} and similarly characteristic 92
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Fig. 3. (a) ID vs. VGS (b) gm1 vs. VGS (c) ID and gd vs. VDS (d) TGF vs. VGS (e) VEA vs. VGS and (f) AV vs. VGS at VDS = 1 V for different channel length.
A=
B=
βQG ⎞ ⎛ βQG ⎞ ⎛ −λQGL ⎜VD + λ 2 ⎟ − ⎜VS + λ 2 ⎟e QG ⎠ ⎝ QG ⎠ ⎝ e−λQGL(e2λQGL − 1) βQG ⎞ ⎛ βQG ⎞ ⎛ λQGL ⎜VD + λ 2 ⎟ − ⎜VS + λ 2 ⎟e QG ⎠ ⎝ QG ⎠ ⎝ e λQGL(e−2λQGL − 1)
4. Model verification
and
In Fig. 2(a), Center potential variation for different channel lengths (20 nm, 30 nm and 40 nm) has been shown. It is observed that for short channel lengths the analytical values are well matched with the numerically calculated values obtained from Silvaco ATLAS device
(15) 93
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Fig. 4. (a) ID vs. VGS (b) gm1 vs. VGS (c) ID and gd vs. VDS (d) TGF vs. VGS (e) VEA vs. VGS and (f) AV vs. VGS at VDS = 1 V for different channel height (or width).
5. Results and discussion
simulator. In Fig. 2(b) Center potential variation for different heights (10 nm, 12 nm, 14 nm, 16 nm and 18 nm) has been shown for channel length 20 nm. In Fig. 2(c) Center potential variation for different oxide thickness (1 nm, 1.5 nm, 2 nm, 2.5 nm and 3 nm) have been shown for channel length 20 nm. In Fig. 2(d) Center potential variation for different donor concentrations in the channel region (5 × 1018 cm−3, 1 × 1019 cm−3, 1.5 × 1019 cm−3, 2 × 1019 cm−3, 2.5 × 1019 cm−3) have been shown for channel length 20 nm. In Fig. 2(e) Center potential variation for different drain voltages (VDS = 0 V, 0.5 V, 1.0 V) have been shown for channel length 20 nm. In Fig. 2(f) Center potential variation for different gate voltages (VGS = 0 V, 0.25 V, 0.5 V) have been shown for channel length 20 nm. All the results presented show that the developed model is in good agreement with the numerically obtained data.
In this section we present the digital, analog and RF parameter variations based on the results obtained from numerical calculation using the ATLAS device simulator. Appropriate models have been chosen and applied to capture the effects affecting the device performance. Subsections 5.1, 5.2 and 5.3 present the short channel effects, analog and RF performance parameters respectively. 5.1. Short channel effects (SCEs) In this subsection the SCE parameters of JLQG for variations of physical dimensions have been discussed. Table 2 presents the SCE parameters for different channel length of JLQG MOSFET. Subthreshold swing (SS) decreases with increase in the channel length due to increase in the oxide capacitance which increases the control of gate over the channel. ION/IOFF ratio increases with increase in the channel 94
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Fig. 5. (a) ID vs. VGS (b) gm1 vs. VGS (c) ID and gd vs. VDS (d) TGF vs. VGS (e) VEA vs. VGS and (f) AV vs. VGS at VDS = 1 V for different gate oxide thickness.
between them. Table 3 represents the SCE parameters for different heights (or widths) of JLQG. SS is observed to increase with the increase of height (or width) as SS is directly dependent on the depletion capacitance and
length even when there is decrement in due to increase in the resistance of the channel because decrement in IOFF is much more than decrease in ION. DIBL is decreasing as the channel length increases because effect of the drain on the source side barrier is reduced due to increased distance
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Fig. 6. (a) ID vs. VGS (b) gm1 vs. VGS (c) ID and gd vs. VDS (d) TGF vs. VGS (e) VEA vs. VGS and (f) AV vs. VGS at VDS = 1 V for different concentration.
same. Table 4 summarizes the SCEs parameters for different gate oxide thickness (tox). SS increases with increase of gate oxide thickness (tox) due to reduction of gate control over the channel. Also, ION/IOFF decreases because IOFF increases much faster than ION as tox is increased due to the reduction in gate control over channel. DIBL increases
as height is increased the area and hence depletion capacitance also increases which increases Sub-threshold slope. ION/IOFF decreases with increase in the height (or width) even with increase of ION due to increase in the cross sectional area but the IOFF increases faster. DIBL increases with the height (or width) increase because of the fact the control of the top gate reduces whereas the effect of the drain remain 96
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resistance. MOS analog circuits require transistors with lower gd in order to achieve higher gain. Dependence of analog performance on oxide thickness is shown by Fig. 5. Fig. 5(a) shows increase in OFF current with increase of tox since control of gate reduces and lowering of barrier height. Whereas, ON current does not increase in same proportion resulting in decrease of ION/IOFF ratio. So, smaller values of tox should be chosen for higher ION/ IOFF ratio. gm1 for higher oxide thickness is high till VGS = 0.8 V but after that it starts increasing for lower tox and maximum peak is observed at the low tox (1 nm) at VGS = 1.08 V as shown by Fig. 5(b). Also, the peak values of gm1 decrease at higher tox. As tox increases, gd increases (i.e. output resistance decreases) reducing the gain represented by Fig. 5(c). Fig. 5(d–f) show the variation of TGF, early voltage (VEA) and intrinsic gain (AV) as a function of VGS respectively. TGF decreases as oxide thickness increases i.e. gain available per unit power dissipation reduces. Peak value reduces by 14.3% from 1 nm to 3 nm oxide thickness. Early voltage is high for the low oxide thickness but at the middle range of gate voltages high oxide thickness have high early voltage but after VGS = 0.9 V again low oxide thickness value starts increasing and peak value decreases by 15.4% from 1 nm to 3 nm. Gain reduces with gate oxide thickness. For tox = 2 nm the gain is more than tox = 1.5 nm till VGS = 0.4 V after that gain at 1.5 nm is more than that of 2 nm. Peak value of gain reduces by 29% from 1 nm to 3 nm oxide thickness. From Fig. 6(a) it is observed that ID increases as concentration increases because the drain current is directly proportional to free carriers (i.e. concentration). But, ON current does not increase as much as OFF current increases resulting in a decrease of ION/IOFF ratio. So, doping concentration should be kept high for higher drain current and less for higher ION/IOFF ratio. Higher trans-conductance is preferable for analog applications because it increases carrier transport efficiency. But as we increase concentration, trans-conductance increases due to increase in drain current as shown by Fig. 6(b). As concentration increases, gd also increases resulting into decrease in output resistance shown by Fig. 6(c). MOS analog circuits require transistors with lower gd in order to achieve higher gains. Fig. 6(d–f) shows the variation of TGF, VEA and AV respectively. TGF decreases as the concentration increases. The peak value reduces by 22.4% from 5.0 × 1018 cm−3 to 2.5 × 1019 cm−3 doping concentration i.e. gain per unit power deteriorates. Early voltage increases with doping concentration increase and peak value increases by 30% from 5.0 × 1018 cm−3 to 2.5 × 1019 cm−3 doping concentration. Gain at high VGS is high for the low doping concentrations but as VGS is reduced the gain at lower doping concentration starts dominating.
Table 6 Formulae used for calculation of analog and RF parameters. Parameters
Formula used
Transconductance ( gm1)
gm1 =
Transconductance generation factor (TGF) Output conductance ( gd )
TGF =
Intrinsic gain (AV)
AV =
Early voltage (VEA)
VEA =
Cut-off-frequency ( fT )
fT =
gd =
δID δVGS gm1 ID
δID δVDS gm1
gd ID gd gm1
2πCgs 1 + 2
Gain frequency product (GFP) Transconductance frequency product (TFP) Gain transconductance frequency product (GTFP)
GFP = ⎛ ⎝ TFP =
gm1 ⎞ gd ⎠
g ⎛ m1 ⎞ ⎝ gd ⎠
GTFP = ⎛ ⎝
Cgd Cgs
≈
gm1 2π (Cgs + Cgd)
× fT = AV × fT × fT
gm1 ⎞ gd ⎠
×⎛ ⎝
gm1 ⎞ Id ⎠
× fT = AV ×TFP
because influence of drain bias (VDS) increases with tox. SS increases with increase in doping concentration shown by Table 5. ION/IOFF ratio decreases with increase in the concentration even when ION increases due to increase in the doping concentration but IOFF increases even faster. DIBL also increases with increase in concentration. Tables 2–5 demonstrate that for good digital characteristics and lower SCEs; lower channel length, lower channel height (or width), lower gate oxide thickness and lower doping concentrations can be chosen suitably. Looking at the variation of different SCE parameters it is revealed that the doping concentration affects the device performance the most. 5.2. Analog performance Fig. 3 shows variation of analog performance for different channel length. From Fig. 3(a), it is observed that as channel length decreases; drain current increases because the drain current is inversely proportional to channel length. But, OFF current increases more as compared to ON current, results in decrease in ION/IOFF as shown by Table 2. So, lower channel length should be taken for higher drain current and large high ION/IOFF ratio. Higher trans-conductance is preferable for analog applications because it shows higher carrier transport efficiency. Fig. 3(b) shows decrease of trans-conductance with increase in channel length. A decrease of 26% in peak value of gm1 is observed when channel length is increased from 20 nm to 60 nm. As channel length increases, gd decreases resulting into increase in output resistance as shown by Fig. 3(c). MOS analog circuits require transistors with lower gd in order to achieve higher gains. Fig. 3(d–f) show the variations of trans-conductance generation factor (TGF), early voltage (VEA) and intrinsic gain (AV) as a function of VGS respectively. TGF is defined as the available gain per unit value of the power dissipation so its higher value is desirable to get high gain for a given power. VEA is the measure of the output resistance and for higher gain, a higher value of VEA is desired. This also leads to higher intrinsic gain required for amplification. Fig. 4 shows analog performance of JLQG MOSFET by varying channel height (or width). In Fig. 4(a), drain current variation with VGS has been shown for different silicon thickness i.e. channels height. It is observed that as height (or width) increases drain current also increases because drain current is directly proportional to cross section area of channel. But, ON current increment is offset by an increase in OFF current resulting in decrease of ION/IOFF ratio. Fig. 5(b) shows the increase of trans-conductance with height (or width) due to increase in drain current. In Fig. 5(c), drain current and output conductance increases as height (or width) increases resulting into decrease in output
5.3. RF performance In this subsection we present the RF performance of JLQG MOSFETs. The performance parameters have been calculated using the formulae listed in Table 6. In Fig. 7(a), the Cgs and Cgd has been computed numerically setting AC small signal analysis at 1 MHz frequency with DC solutions obtained at VDS = 1 V. Both Cgs and Cgd of device increases with increase of channel length resulting into lower switching speed. But cut-off frequency increases as channel length decreases and 300% increase in fT is observed when channel length is decreased from 60 nm to 20 nm as shown by Fig. 7(b). Other performance parameters like gain frequency product (GFP), trans-conductance frequency product (TFP) and gain trans-conductance frequency product (GTFP) are also essential for amplifiers for high frequency operations with higher values. In Fig. 7(c), the GFP increases with decrease of channel length from 60 nm to 30 nm; but as the channel length is reduced to 20 nm, it reduces due to reduction of intrinsic gain (Fig. 3(f)). The highest value of GFP is obtained around VGS = 0.8 V for 30 nm whereas it is high for 20 nm up to VGS = 0.64 V. At higher gate voltage again GFP of 20 nm channel length start dominating and is higher as compared to other channel lengths because GFP is the product of gain and cut off 97
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Fig. 7. (a) Cgs and Cgd (b) cut-off frequency (c) GFP (d) TFP and (e) GTFP vs. VGS at VDS = 1.0 V for different channel lengths.
increases in peak value is observed for 20 nm to 60 nm change in channel length. This is due to the fact that for higher channel lengths gain is higher and dominates. Fig. 8(a) shows Cgs and Cgd of device to increase with increase in height (or width) due to increase in total gate area. The cut-off
frequency, and intrinsic gain and fT show opposite behavior with the increase of the channel length. TFP in Fig. 7(d) decreases with channel length increase. A decrease of 76% in peak TFP is observed as channel length is increases from 20 nm to 60 nm as inferred from graph. In Fig. 7(e), GTFP increases with channel length increase and 89%
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Fig. 8. (a) Cgs and Cgd (b) cut off frequency (c) GFP d) TFP and (e) GTFP vs. VGS at VDS = 1.0 V for different channel height (or width).
frequency increases as height (or width) is increased because gm increases much more compared to the capacitances; but at higher VGS the cut off frequency for different values of height (or width) tend to approach same value. The peak value of the cut-off frequency reduces by 1.2% from 10 nm to 18 nm height as shown by Fig. 8(b). GFP is more for the higher height (or width) up to VGS = 0.63 V but after that lower height (or width) value start dominating as represented by Fig. 8(c). At
VGS = 0.94 V maximum value of GFP is observed at 10 nm height and a decrement of 34% in peak value from 10 nm to 18 nm as inferred from above plots. This is due to the fact that gain at lower height is more whereas cut off frequency is less at low VGS but at higher VGS the cut off frequency become same. TFP of larger height (18 nm) is large up to VGS = 0.52 V after that lower height values start to dominate and maximum peak is observed at VGS = 0.7 V for 10 nm and the peak value decreases 99
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Fig. 9. (a) Cgs and Cgd vs. gate voltage (b) cut off frequency vs. gate voltage (c) GFP vs. gate voltage (d) TFP vs. gate voltage (e) GTFP vs. gate voltage for different oxide thickness at VDS = 1.0 V.
more till VGS = 0.5 V after that lower height values start dominating it and maximum peak is found at VGS = 0.72 V for 10 nm and peak value reduces by 61% from 10 nm to 18 nm. Fig. 9(a) shows Cgd of device to increase with decrease in the tox. Cgs for large tox (i.e. 3 nm) is low at lower gate voltages up to VGS = 0.18 V
by 30.3% from 10 nm to 18 nm height as shown by Fig. 8(d). This is due to fact that TGF (Fig. 4(d)) is almost constant at lower gate voltages and decreases as the gate voltage increases whereas cut off frequency increases. TGF decreases with increase in the height and cut off frequency increases with height. GTFP shown by Fig. 8(e) of the higher height is 100
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Fig. 10. (a) Cgs and Cgd (b) cut-off frequency (c) GFP (d) TFP and (e) GTFP for different doping at VDS = 1 V.
value is observed at low oxide thickness at VGS = 0.98 V and maximum value reduces by 59.5% from 1 nm to 3 nm. In Fig. 9(d), TFP of high oxide thickness is more for low gate voltage till VGS = 0.58 V after that thin tox starts dominating and maximum value is found at VGS=0.82 V for the tox = 1 nm. The peak value of TFP reduces by 19.5% from 1 nm
after that it is dominated by lower tox up to VGS = 0.74 V and once again thin tox starts dominating and maximum value is found for lower tox. Cut off frequency shown by Fig. 9(b) is higher for large tox due to lower capacitances. In Fig. 9(c), GFP of high tox is more at low voltage till VGS = 0.64 V after that it starts increasing for low tox. Maximum 101
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concentration result in higher cut-off frequency. TFP, GFP and GTFP peak values reduce as the donor concentration increases. In short, for good digital, analog and RF characteristics; lower channel length, lower channel height (or width), lower gate oxide thickness and lower doping concentrations should be chosen. The doping concentration affects the device performance parameters most and should be carefully chosen.
to 3 nm. In Fig. 9(e), peak value of the GTFP reduces by 73.9% from 1 nm to 3 nm oxide thickness; maximum peak value is found for the 1 nm oxide thickness at VGS = 0.82 V. Peak value for the higher oxide thickness shifts toward lower gate voltages. In Fig. 10(a) variation of Cgs and Cgd w.r.t. gate voltage has been shown at VDS = 1 V. The Cgs of device increases with increase in doping concentration resulting into lower switching speed. But cut off frequency increases with doping concentration as represented by Fig. 10(b). In Fig. 10(c) GFP for higher doping concentration is more at the lower VGS but as VGS increases the lower doping concentration GFP starts increasing and maximum value is found at lower concentration and high VGS. This is due to the fact GFP is the product of gain and cut off frequency; gain and cut off frequency is low for low concentration but at high gate voltage gain of the lower concentration dominates and the difference in cut off frequency at different concentration also decreases. Figs. 10(e) and (f) representing TFP and GTFP show unique behavior for different concentrations having peaks at different VGS and peaks are found at higher VGS for lower concentrations. Maximum value of GFP, TFP and GTFP reduces by 40.1%, 38.2% and 59.5% respectively when doping concentration is changed from 5.0 × 10 18 cm−3 to 2.5 × 1019 cm−3.
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6. Conclusion In this work, center potential based on ENG for JLQG MOSFET is developed and its analog/RF performance is investigated for different channel lengths, height (or width), gate oxide thickness and doping concentrations. We report improvement in various parameters such as subthreshold swing, ION/IOFF ratio, IOFF and DIBL with channel length increment, height (or width) decrement, oxide thickness decrement and doping concentration decrement. The ION increases with channel length decrement, height (or width) increment, oxide thickness increment and doping concentration increment. As the channel length increases the analog parameters such as intrinsic gain, TGF, early voltage increases. Increase in channel length results in higher capacitances (Cgs and Cgd) which decreases cut-off frequency, TFP and GFP. But an increase in GFP is observed when channel length is increased from 20 nm to 30 nm. GTFP peak value increases with channel length. As the height (or width) increases the analog parameters such as intrinsic gain and TGF decreases whereas the peak value of the early voltage reduces. Increase in height (or width) result in higher capacitances (Cgs and Cgd) and a high cut-off frequency because gm1 increases much more compared to the capacitances. TFP, GFP and GTFP peak values reduce as the height (or width) increases. With oxide thickness increase, analog parameters such as intrinsic gain and TGF decrease whereas the peak value of the early voltage reduces. Increase in oxide thickness results in lower Cgs and Cgd which gives higher cut-off frequency. TFP, GFP and GTFP peak value reduces with oxide thickness increase. As the oxide thickness increases the analog parameters such as intrinsic gain and TGF decrease whereas the peak value of the early voltage reduces. As the donor concentration increases the analog parameters such as TGF and intrinsic gain decrease whereas early voltage increases. Increase in donor
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