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Practical scheduling and line optimization technology for ASIC manufacturing lines
1964
World abstracts of microelectronics and reliability
applications. The model runs daily at the IBM semiconductor manufacturing plant in Yasu, Japan, where it has been in use for many years, currently on three different semiconductor manufacturing lines.
Multimetal DTAB packages for a 125-MHz computer. RAVI KAW, DAVIDYANAGAand FARID MATTA. IEEE Transactions on Components, Hybrids and Manufacturin9 Technology, 16(1), 95 (February 1993). This paper discusses the challenges in packaging a 430 pin IC chip that operates at 2 V, draws 15 A, with rise times of about 200 ps. A highly optimized 407-pin multilayer ceramic package (PGA) with wirebonds was first evaluated for this application and failed most of the noise specifications. An analysis of the failure mechanisms led to the design of a 2-metal layer 432 pin TAB package. Performance capabilities and limitations of these two packages are compared through detailed simulations and actual measurements. It is concluded that TAB packages meet or exceed the performance goals for low transition times and/or large operating currents. The initial design was modified with the addition of a third metal layer. Performance results of this 3-metal layer TAB are also included.
Surface mounting of very fine pitch components: a new challenge. JEAN JOLY and XAVIERSAINT-MARTIN. IEEE Transactions on Components, Hybrids and Manufacturing Technology, 16(4), 402 (June 1993). The pitch of peripheral surface mounted components is now reaching a range of values below 16 mils (0.4 mm). As VLSI silicon die size and I/O numbers are increasing, a normal trend to enhance miniaturization of components is to reduce the distance between peripheral outer leads. At the same time better electrical, thermal, and reliability performances are required. Based on our experience to develop and to use 16- and 12.5-mil peripheral pitch custom compact single chip packages (CSCP's), we shall analyze the evolution and today's limits of package and board technologies, assembly techniques, with emphasis on manufacturability. Our manufacturing approach, quality, and reliability results when using 16- and 12.5-mil peripheral ceramic leaded packages are presented. A detailed analysis of packaging processes and limitations is due for high pin count ceramic and plastic packages. Competitive packaging methods, PGA, LGA and TAB are compared and we analyze trends for the future.
Organizational learning across critical linkages: the High-speed VLS1 interconnect modelling based on s- case of captive ASIC design and manufacturing. JOHN parameter measurements. YUNGSEONEo and WILLIAM CALLAHAN and PETER DIEDR1CH. Microelectronics R. EISENSTADT. IEEE Transactions on Components, Journal, 24, 463 (1993). Many large electronic systems Hybrids and Manufacturing Technology, 16(5), 555 manufacturers have captive internal ASIC design and (August 1993). A first level metal single conductor IC manufacturing capability. The ASIC environment is interconnect model is developed for high speed and driven by continuous and significant advances in basic high density VLSI circuit design. The model shows design and manufacturing technology, CAD tools, interconnect circuit parameters vary with frequency. and design complexity. This paper introduces a Existing interconnect models include effects such as framework for managers charged with deriving capacitive fringing, and the influence of substrate competitive advantage in this environment. The conductance. This new model represents fine line framework is made up of four parts: strategic interconnect as well as wide line interconnect intent, guideposts; organizational structure: and behavior over a 20-GHz frequency range and includes coordination arrangements. the effects of capacitive fringing and substrate conductance. The model parameters are compared Practical scheduling and line optimization technology to scattering parameter measurements as well as for ASIC manufacturing lines. CHISATOHASHIMOTOet numerical simulations based on PISCES-II. Excellent al. IEEE Transactions on Components, Hybrids and agreement is shown with s-parameter measurements. Manufacturing Technology, 16(4), 407 (June 1993). For application specific integrated circuit (ASIC) manuPackages reflect diverse needs, technologies among facturing lines, quick product turnaround time (TAT) device users. JEE(Japan), 43 (November 1993). as well as high throughput is critical. To achieve both, Manufacturers today have strong needs to improve efficient lot management and line operation are productivity, lower packaging and physical dis- required. A new automatic scheduler and method of tribution costs, cut back on inventory space, customization to increase scheduling efficiency have and expand their capabilities to handle new products. been developed for satisfying this requirement. To accommodate some of these needs, packaging Simulations with the scheduler yielded the new styles for surface-mountable devices (SMDs) are concept of line performance curves (LPC's). Based on diversifying. Many of these packages enable set these techiques, a line management agorithm that makers to improve their device-mounting systems, places emphasis on TAT has been developed. It employs a due date management chart (DMC) accommodate miniature chips, and enhance mounting accuracy. Now other needs are arising, such as and a lot release control chart (LCC). These global environmental protection, resource saving, developments make possible dramatic improvements in the efficiency of ASIC manufacturing lines. and recycling.
World abstracts of microelectronics and reliability
applications. The model runs daily at the IBM semiconductor manufacturing plant in Yasu, Japan, where it has been in use for many years, currently on three different semiconductor manufacturing lines.
Multimetal DTAB packages for a 125-MHz computer. RAVI KAW, DAVIDYANAGAand FARID MATTA. IEEE Transactions on Components, Hybrids and Manufacturin9 Technology, 16(1), 95 (February 1993). This paper discusses the challenges in packaging a 430 pin IC chip that operates at 2 V, draws 15 A, with rise times of about 200 ps. A highly optimized 407-pin multilayer ceramic package (PGA) with wirebonds was first evaluated for this application and failed most of the noise specifications. An analysis of the failure mechanisms led to the design of a 2-metal layer 432 pin TAB package. Performance capabilities and limitations of these two packages are compared through detailed simulations and actual measurements. It is concluded that TAB packages meet or exceed the performance goals for low transition times and/or large operating currents. The initial design was modified with the addition of a third metal layer. Performance results of this 3-metal layer TAB are also included.
Surface mounting of very fine pitch components: a new challenge. JEAN JOLY and XAVIERSAINT-MARTIN. IEEE Transactions on Components, Hybrids and Manufacturing Technology, 16(4), 402 (June 1993). The pitch of peripheral surface mounted components is now reaching a range of values below 16 mils (0.4 mm). As VLSI silicon die size and I/O numbers are increasing, a normal trend to enhance miniaturization of components is to reduce the distance between peripheral outer leads. At the same time better electrical, thermal, and reliability performances are required. Based on our experience to develop and to use 16- and 12.5-mil peripheral pitch custom compact single chip packages (CSCP's), we shall analyze the evolution and today's limits of package and board technologies, assembly techniques, with emphasis on manufacturability. Our manufacturing approach, quality, and reliability results when using 16- and 12.5-mil peripheral ceramic leaded packages are presented. A detailed analysis of packaging processes and limitations is due for high pin count ceramic and plastic packages. Competitive packaging methods, PGA, LGA and TAB are compared and we analyze trends for the future.
Organizational learning across critical linkages: the High-speed VLS1 interconnect modelling based on s- case of captive ASIC design and manufacturing. JOHN parameter measurements. YUNGSEONEo and WILLIAM CALLAHAN and PETER DIEDR1CH. Microelectronics R. EISENSTADT. IEEE Transactions on Components, Journal, 24, 463 (1993). Many large electronic systems Hybrids and Manufacturing Technology, 16(5), 555 manufacturers have captive internal ASIC design and (August 1993). A first level metal single conductor IC manufacturing capability. The ASIC environment is interconnect model is developed for high speed and driven by continuous and significant advances in basic high density VLSI circuit design. The model shows design and manufacturing technology, CAD tools, interconnect circuit parameters vary with frequency. and design complexity. This paper introduces a Existing interconnect models include effects such as framework for managers charged with deriving capacitive fringing, and the influence of substrate competitive advantage in this environment. The conductance. This new model represents fine line framework is made up of four parts: strategic interconnect as well as wide line interconnect intent, guideposts; organizational structure: and behavior over a 20-GHz frequency range and includes coordination arrangements. the effects of capacitive fringing and substrate conductance. The model parameters are compared Practical scheduling and line optimization technology to scattering parameter measurements as well as for ASIC manufacturing lines. CHISATOHASHIMOTOet numerical simulations based on PISCES-II. Excellent al. IEEE Transactions on Components, Hybrids and agreement is shown with s-parameter measurements. Manufacturing Technology, 16(4), 407 (June 1993). For application specific integrated circuit (ASIC) manuPackages reflect diverse needs, technologies among facturing lines, quick product turnaround time (TAT) device users. JEE(Japan), 43 (November 1993). as well as high throughput is critical. To achieve both, Manufacturers today have strong needs to improve efficient lot management and line operation are productivity, lower packaging and physical dis- required. A new automatic scheduler and method of tribution costs, cut back on inventory space, customization to increase scheduling efficiency have and expand their capabilities to handle new products. been developed for satisfying this requirement. To accommodate some of these needs, packaging Simulations with the scheduler yielded the new styles for surface-mountable devices (SMDs) are concept of line performance curves (LPC's). Based on diversifying. Many of these packages enable set these techiques, a line management agorithm that makers to improve their device-mounting systems, places emphasis on TAT has been developed. It employs a due date management chart (DMC) accommodate miniature chips, and enhance mounting accuracy. Now other needs are arising, such as and a lot release control chart (LCC). These global environmental protection, resource saving, developments make possible dramatic improvements in the efficiency of ASIC manufacturing lines. and recycling.