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Precise spice macromodel applied to high-voltage power MOSFET
Microelectronics Reliability 42 (2002) 149–152 www.elsevier.com/locate/microrel
Research note
Precise
SPICE
macromodel applied to high-voltage power MOSFET F.S. Lomeli a, A. Cerdeira b,*
b
a On Semiconductor, Labna 1437, Cd. del Sol 45050, Zapopan, Jal., Mexico Dept de Ingenieria Electrica, SEES - CINVESTAV - IPN, Ave. IPN 2508, AP 14-740, Col. S.P. Zacatenco, 07300 Mexico DF, Mexico
Received 9 April 2001; received in revised form 4 June 2001
Abstract A macromodel for precise S P I C E simulations of high-voltage power MOSFET is presented. The macromodel takes into account basic features of these devices as higher value of the resistance between channel and drain and lower current level though the body diode compared to low-voltage power MOSFET. It also considers that high-voltage power MOSFET work mostly in saturation regime. All required parameters are extracted from direct electrical measurements. Simulations using this and previous macromodels are compared with experimental DC and AC characteristics to demonstrate a much better correspondence with experiment of the macromodel presented. Ó 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction Semiconductor producers develop and distribute models for programs as S P I C E , to allow users simulate their specific applications using the devices they produce. Models to simulate power MOSFET can be found in literature. Usually they consider that both drain and source resistance are small, parameter extraction is made using the linear region of the Id –Vg characteristic, see for example Ref. [1], which describes a macromodel for simulation of power MOSFET and the parameter extraction procedure they recommend. High-voltage power MOSFET, present different features that are taken into account in the macromodel described below. Basic required parameters are extracted from electrical measurements and the rest are taken from the data sheet. Knowledge of technological parameters, usually not accessible to user, is not required. Simulations are compared with the experimental characteristics of the MOSFET MTP3N100E fabricated by On Semiconduc-
*
Corresponding author. Tel.: +52-5747-3780; fax: +52-57477114. E-mail address: [email protected] (A. Cerdeira).
tor (formerly a Division of Motorola), which has maximum voltage of 1000 V, maximum constant current of 3 A and maximum RD resistance of 4 X, and with simulations using the model recommended up to now for this device by the producer, which will be called from now on macromodel A [2].
2. Macromodel The power MOSFET is a vertical transistor formed by thousands of transistor cells connected in parallel. The vertical cross-section of two cells of a high-voltage power MOSFET is shown in Fig. 1. A basic difference with respect to low-voltage power MOSFET is the value of the resistance between the channel and the drain, RD , which in the low-voltage MOSFET is in the order of mX, while in the high-voltage is of several X. In addition, the current through the body diode (BD) physically connected between source and drain, that is, in parallel with the core transistor, flows though the central region, (see Fig. 1), and its level is smaller than the level of the drain current which is part of the vertical MOSFET. For these reasons, we changed the macromodel presented in Ref. [1], and put the drain resistance RD in series to both
0026-2714/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 1 ) 0 0 1 2 7 - 5
150
F.S. Lomeli, A. Cerdeira / Microelectronics Reliability 42 (2002) 149–152
long channel transistor and level 1 uses less parameters and their extraction is more direct.
3. Parameter extraction Since the saturation regime for a high-voltage power MOSFET occurs for voltages much smaller that the maximum permitted, they practically work in saturation all the time. Extraction of parameters KP and VTO from the linear region, will not give good results, so they should be obtained from the Id –Vg characteristic in saturation shown in Fig. 3. The current is given by: Idrain ¼ Fig. 1. Vertical cross-section between two cells of a high-voltage power MOSFET. The flow currents of the core transistor and the BD are shown.
Fig. 2. Schematics of all elements conforming macromodel P.
for Vds > ðVgs VTO Þ;
ð1Þ
where KP ¼
the BD and the core transistor. The BD is placed in parallel with the source and drain of the MOSFET. The proposed macromodel, referred from now on as macromodel P, is shown in Fig. 2 and includes a core MOSFET and a BD. It also includes the overlap capacitance CGD and CGS . Diodes Dmin and Dmax simulate the variable capacitance between gate and drain, as well as the gate charge. Parasitic elements associated with the package LG , LD and LS , represent the inductance of the connectors. The distributed resistance of the gate, RG is also included explicitly in the model. The circuit simulation was performed in P S P I C E . Level 1 was selected for the core transistor since it is a
KP ðVgs VTO Þ2 ; 2
W C0 l0 ; L
ð2Þ
W is the total equivalent channel width; L the channel length of one cell; C0 the gate capacitance per unit area; l0 the maximum channel mobility. As shown in Fig. 2, Vgs ¼ Vgate , while Vds ¼ Vdrain RD Idrain , where Vgate and Vdrain are the external applied voltages. pffiffiffiffiffiffiffiffiffi Form curve Idrain vs. Vgate , for Vdrain ¼ Vgate , the maximum slope S is determined and KP calculated as 2S 2 ; VTO is determined through the intercept of the slope with Y-axis. LAMBDA y RS are taken equal to zero and the rest of the parameters by its default values An important element in this curve is the abrupt reduction of the slope starting from a given gate voltage indicated in Fig. 3 as transition point. This effect is not observed in conventional MOSFET or in low-voltage
Fig. 3. Comparison of measured Id –Vg curve for transistor MTP3N100E with simulated using macromodels A and P. The transition point is indicated.
F.S. Lomeli, A. Cerdeira / Microelectronics Reliability 42 (2002) 149–152
power MOSFET and is caused by resistance RD . As the current increases, the voltage drop in RD increases and differs from the voltage drop between drain and source Vds . When Vdrain Vds equals VTO , transistor is no longer in saturation and from this moment on, the current will be limited by resistance RD . The value of this resistance RD is obtained from the slope in the linear region of the output characteristic. Since RD is a resistance external with respect to the core transistor, you must assign it a temperature coefficient which can be taken from the data sheet of the transistor. Parameters IS , N and RS , corresponding to the BD are obtained in a conventional way through the direct I–V characteristic of the diode between source and drain. For more flexibility, capacitance values present in macromodel P are considered external to the core transistor. The procedure for their extraction is described in Ref. [1] and does not require any knowledge of technological parameter. Parameters CJO , M and VJ of diodes Dmin and BD and CJO of diode Dmax are determined as usually, after measuring input, output and reverse transfer capacitance (Ciss , Coss and Crss ) and the gate load characteristic. The package dependent parasitic inductance at each input (LD , LG and LS ), and the distributed linear resistance of the gate RG are taken from the data sheet. Comparison between simulation and characterization is shown for MOSFET MTP3N100E, which is formed by 17 500 parallel cells.
4. Analysis of results Simulation of the output and Id –Vg characteristics of transistor at 25°C temperature, was done using macromodels P and A. Output and Id –Vg characteristics were measured using a pulse generator of 300 ls, with a duty cycle smaller than 2% to avoid heating of the transistor. Parameters KP , VTO and RD and capacitances, measured as described above, and the parasitic elements for the package TO220 taken from the data sheet are shown in Table 1. Figs. 3 and 4 compare measured Id –Vg and Id –Vd characteristics with simulation with macromodel P for parameters obtained as described above, and with macromodel A using all the parameters given by the producer for a level 3 S P I C E simulation. For macromodel A correspondence with experiment is in the order of 40%, while macromodel P fits within a 10% error. The drain voltage is shown up to 20 V because from this value on the current remains constant, as expected with indicated in the data sheet. Typical AC behavior of power MOSFET can be found in Ref. [3]. Validation of macromodel P under AC
151
Table 1 Extracted values of parameters used in simulation for macromodel P Parameter
Unit
VTO KP RD CGD CGS
V A/V2 X pF pF
3.68 3.59 2.91 38.9 1380
From BD IS RS N CJO VJ M
A X – pF V –
1:19 1011 5.7 1.1 822 0.6 0.46
From Dmin CJO VJ M
pF V –
848 0.71 0.71
pF
4000
nH nH nH X
6 4.5 7.5 5
From Dmax CJO Parasitic LG LD LS RG
behavior was done comparing simulation with the experimental response of the MOSFET to a 10 V pulse 600 ns width and 33 ns rise time. The drain of the transistor was biased through a 39 X resistance up to 40 V. Gate was connected to a 50 X cable as indicated in the data sheet. Results of the transitions times are shown in Table 2. More experimental and simulation details can be found in Ref. [4].
Fig. 4. Comparison of measured Id –Vd curve for transistor MTP3N100E with simulated using macromodels A and P.
152
F.S. Lomeli, A. Cerdeira / Microelectronics Reliability 42 (2002) 149–152
Table 2 Results of transition times from AC simulation with macromodels P and A and from measurement Parameter (ns)
Experimental
Macromodel P
Macromodel A
Turn-on delay Rise time Turn-off delay Fall time
41 74 123 87
57 52 87 78
50 38 102 54
MOSFET. All parameters required for the macromodel can be obtained from direct electrical measurements without knowledge of technological parameters. For the DC regime only parameters KP , VTO and RD are required. Precise simulation is achieved, while using the benefits of a much simple S P I C E level one model for MOSFET than the previous model recommended by manufacturer.
References 5. Conclusions Simulation of DC and AC characteristics of highvoltage power transistors using the new macromodel presented in this work provides much better correspondence with experiment than the obtained when using previous models and can be recommended for the development of new applications of high-voltage power
[1] Kielkowsky RM. S P I C E practical device modeling. New York: McGraw Hill; 1995 [Chapter 6]. [2] Model developed by Analogy, Inc. is available in www.onsemi.com. [3] Baliga BJ. Power semiconductor devices. PWS Publishing Company; 1996. [4] Lomeli FS. El transistor MOS de potencia: caracteristicas, modelo y simulaci on. MS Degree Thesis, CINVESTAV, Mexico, 1999.
Research note
Precise
SPICE
macromodel applied to high-voltage power MOSFET F.S. Lomeli a, A. Cerdeira b,*
b
a On Semiconductor, Labna 1437, Cd. del Sol 45050, Zapopan, Jal., Mexico Dept de Ingenieria Electrica, SEES - CINVESTAV - IPN, Ave. IPN 2508, AP 14-740, Col. S.P. Zacatenco, 07300 Mexico DF, Mexico
Received 9 April 2001; received in revised form 4 June 2001
Abstract A macromodel for precise S P I C E simulations of high-voltage power MOSFET is presented. The macromodel takes into account basic features of these devices as higher value of the resistance between channel and drain and lower current level though the body diode compared to low-voltage power MOSFET. It also considers that high-voltage power MOSFET work mostly in saturation regime. All required parameters are extracted from direct electrical measurements. Simulations using this and previous macromodels are compared with experimental DC and AC characteristics to demonstrate a much better correspondence with experiment of the macromodel presented. Ó 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction Semiconductor producers develop and distribute models for programs as S P I C E , to allow users simulate their specific applications using the devices they produce. Models to simulate power MOSFET can be found in literature. Usually they consider that both drain and source resistance are small, parameter extraction is made using the linear region of the Id –Vg characteristic, see for example Ref. [1], which describes a macromodel for simulation of power MOSFET and the parameter extraction procedure they recommend. High-voltage power MOSFET, present different features that are taken into account in the macromodel described below. Basic required parameters are extracted from electrical measurements and the rest are taken from the data sheet. Knowledge of technological parameters, usually not accessible to user, is not required. Simulations are compared with the experimental characteristics of the MOSFET MTP3N100E fabricated by On Semiconduc-
*
Corresponding author. Tel.: +52-5747-3780; fax: +52-57477114. E-mail address: [email protected] (A. Cerdeira).
tor (formerly a Division of Motorola), which has maximum voltage of 1000 V, maximum constant current of 3 A and maximum RD resistance of 4 X, and with simulations using the model recommended up to now for this device by the producer, which will be called from now on macromodel A [2].
2. Macromodel The power MOSFET is a vertical transistor formed by thousands of transistor cells connected in parallel. The vertical cross-section of two cells of a high-voltage power MOSFET is shown in Fig. 1. A basic difference with respect to low-voltage power MOSFET is the value of the resistance between the channel and the drain, RD , which in the low-voltage MOSFET is in the order of mX, while in the high-voltage is of several X. In addition, the current through the body diode (BD) physically connected between source and drain, that is, in parallel with the core transistor, flows though the central region, (see Fig. 1), and its level is smaller than the level of the drain current which is part of the vertical MOSFET. For these reasons, we changed the macromodel presented in Ref. [1], and put the drain resistance RD in series to both
0026-2714/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 1 ) 0 0 1 2 7 - 5
150
F.S. Lomeli, A. Cerdeira / Microelectronics Reliability 42 (2002) 149–152
long channel transistor and level 1 uses less parameters and their extraction is more direct.
3. Parameter extraction Since the saturation regime for a high-voltage power MOSFET occurs for voltages much smaller that the maximum permitted, they practically work in saturation all the time. Extraction of parameters KP and VTO from the linear region, will not give good results, so they should be obtained from the Id –Vg characteristic in saturation shown in Fig. 3. The current is given by: Idrain ¼ Fig. 1. Vertical cross-section between two cells of a high-voltage power MOSFET. The flow currents of the core transistor and the BD are shown.
Fig. 2. Schematics of all elements conforming macromodel P.
for Vds > ðVgs VTO Þ;
ð1Þ
where KP ¼
the BD and the core transistor. The BD is placed in parallel with the source and drain of the MOSFET. The proposed macromodel, referred from now on as macromodel P, is shown in Fig. 2 and includes a core MOSFET and a BD. It also includes the overlap capacitance CGD and CGS . Diodes Dmin and Dmax simulate the variable capacitance between gate and drain, as well as the gate charge. Parasitic elements associated with the package LG , LD and LS , represent the inductance of the connectors. The distributed resistance of the gate, RG is also included explicitly in the model. The circuit simulation was performed in P S P I C E . Level 1 was selected for the core transistor since it is a
KP ðVgs VTO Þ2 ; 2
W C0 l0 ; L
ð2Þ
W is the total equivalent channel width; L the channel length of one cell; C0 the gate capacitance per unit area; l0 the maximum channel mobility. As shown in Fig. 2, Vgs ¼ Vgate , while Vds ¼ Vdrain RD Idrain , where Vgate and Vdrain are the external applied voltages. pffiffiffiffiffiffiffiffiffi Form curve Idrain vs. Vgate , for Vdrain ¼ Vgate , the maximum slope S is determined and KP calculated as 2S 2 ; VTO is determined through the intercept of the slope with Y-axis. LAMBDA y RS are taken equal to zero and the rest of the parameters by its default values An important element in this curve is the abrupt reduction of the slope starting from a given gate voltage indicated in Fig. 3 as transition point. This effect is not observed in conventional MOSFET or in low-voltage
Fig. 3. Comparison of measured Id –Vg curve for transistor MTP3N100E with simulated using macromodels A and P. The transition point is indicated.
F.S. Lomeli, A. Cerdeira / Microelectronics Reliability 42 (2002) 149–152
power MOSFET and is caused by resistance RD . As the current increases, the voltage drop in RD increases and differs from the voltage drop between drain and source Vds . When Vdrain Vds equals VTO , transistor is no longer in saturation and from this moment on, the current will be limited by resistance RD . The value of this resistance RD is obtained from the slope in the linear region of the output characteristic. Since RD is a resistance external with respect to the core transistor, you must assign it a temperature coefficient which can be taken from the data sheet of the transistor. Parameters IS , N and RS , corresponding to the BD are obtained in a conventional way through the direct I–V characteristic of the diode between source and drain. For more flexibility, capacitance values present in macromodel P are considered external to the core transistor. The procedure for their extraction is described in Ref. [1] and does not require any knowledge of technological parameter. Parameters CJO , M and VJ of diodes Dmin and BD and CJO of diode Dmax are determined as usually, after measuring input, output and reverse transfer capacitance (Ciss , Coss and Crss ) and the gate load characteristic. The package dependent parasitic inductance at each input (LD , LG and LS ), and the distributed linear resistance of the gate RG are taken from the data sheet. Comparison between simulation and characterization is shown for MOSFET MTP3N100E, which is formed by 17 500 parallel cells.
4. Analysis of results Simulation of the output and Id –Vg characteristics of transistor at 25°C temperature, was done using macromodels P and A. Output and Id –Vg characteristics were measured using a pulse generator of 300 ls, with a duty cycle smaller than 2% to avoid heating of the transistor. Parameters KP , VTO and RD and capacitances, measured as described above, and the parasitic elements for the package TO220 taken from the data sheet are shown in Table 1. Figs. 3 and 4 compare measured Id –Vg and Id –Vd characteristics with simulation with macromodel P for parameters obtained as described above, and with macromodel A using all the parameters given by the producer for a level 3 S P I C E simulation. For macromodel A correspondence with experiment is in the order of 40%, while macromodel P fits within a 10% error. The drain voltage is shown up to 20 V because from this value on the current remains constant, as expected with indicated in the data sheet. Typical AC behavior of power MOSFET can be found in Ref. [3]. Validation of macromodel P under AC
151
Table 1 Extracted values of parameters used in simulation for macromodel P Parameter
Unit
VTO KP RD CGD CGS
V A/V2 X pF pF
3.68 3.59 2.91 38.9 1380
From BD IS RS N CJO VJ M
A X – pF V –
1:19 1011 5.7 1.1 822 0.6 0.46
From Dmin CJO VJ M
pF V –
848 0.71 0.71
pF
4000
nH nH nH X
6 4.5 7.5 5
From Dmax CJO Parasitic LG LD LS RG
behavior was done comparing simulation with the experimental response of the MOSFET to a 10 V pulse 600 ns width and 33 ns rise time. The drain of the transistor was biased through a 39 X resistance up to 40 V. Gate was connected to a 50 X cable as indicated in the data sheet. Results of the transitions times are shown in Table 2. More experimental and simulation details can be found in Ref. [4].
Fig. 4. Comparison of measured Id –Vd curve for transistor MTP3N100E with simulated using macromodels A and P.
152
F.S. Lomeli, A. Cerdeira / Microelectronics Reliability 42 (2002) 149–152
Table 2 Results of transition times from AC simulation with macromodels P and A and from measurement Parameter (ns)
Experimental
Macromodel P
Macromodel A
Turn-on delay Rise time Turn-off delay Fall time
41 74 123 87
57 52 87 78
50 38 102 54
MOSFET. All parameters required for the macromodel can be obtained from direct electrical measurements without knowledge of technological parameters. For the DC regime only parameters KP , VTO and RD are required. Precise simulation is achieved, while using the benefits of a much simple S P I C E level one model for MOSFET than the previous model recommended by manufacturer.
References 5. Conclusions Simulation of DC and AC characteristics of highvoltage power transistors using the new macromodel presented in this work provides much better correspondence with experiment than the obtained when using previous models and can be recommended for the development of new applications of high-voltage power
[1] Kielkowsky RM. S P I C E practical device modeling. New York: McGraw Hill; 1995 [Chapter 6]. [2] Model developed by Analogy, Inc. is available in www.onsemi.com. [3] Baliga BJ. Power semiconductor devices. PWS Publishing Company; 1996. [4] Lomeli FS. El transistor MOS de potencia: caracteristicas, modelo y simulaci on. MS Degree Thesis, CINVESTAV, Mexico, 1999.