A macro model in SMART SPICE to study MOSFET degradations with the CP technique

Microelectronics Journal ELSEVIER

Microelectronics Journal 29 (1998) 805-811

A macro model in SMART SPICE to study MOSFET degradations with the CP technique F. D j a h l i a, L . K a a b i b aUniversit~ Ferhat Abbas, Institut d'Electronique, 19000 S~tif Algeria bLaboratoire de Physique de la Matikre, URA-CNRS 358, bdt. 502, INSA Lyon, 20 avenue Albert Einstein, 69621 Villeurbanne Cedex, France

Abstract

In this work, we have s:imulated the experimental charge pumping technique by the development and implementation of a macro model in the electrical simulator S]~M~T SPICE on a personal computer. This macro model takes into account all of the geometrical and electrical parameters of the studied transistor and gives their mathematical expressions. It also gives the different curves of the charge pumping current, which can be obtained experimentally by this technique for different parameters, before or after different ageing stresses. The results obtained are compared with recent experimental results. © 1998 Published by Elsevier Science Ltd. All rights reserved. Keywords: MOSFET degradation; Charge pumping technique; Macro model

1. I n t r o d u c t i o n

The charge pumping technique, originally developed by Brugler and Jespers [1], is a very useful tool to study the oxide/silicon interface of MOS structures and especially submicronic MOSFETs. This technique is used widely not only in research but also in industry, because it can easily be integrated into an industrial process to control all technological steps. The standard charge pumping technique [2-11] allows one to obtain, with very great sensitivity, the mean value of interface state density, its spatial distribution along the channe]l of the transistor and its energetic distribution on a large energy scale in the silicon bandgap. More recent developments of this technique have been proposed in previous years. Some of these methods modify the gate voltage pulses by applying a three-level periodic signal to the gate of the transistor [12-17], while others use a spectroscopic technique similar to DLTS (deep level transient spectroscopy) by varying the transistor temperature [18]. This technique, coupled with measurements of static characteristics [19,20], allows the study of transistor ageing and subsequent prediction of its behaviour. However, being relatively recent, the charge pumping technique is not taken into account in electrical simulators such as SPICE or ESACAP. In this work we implemented a macro model in the simulator SMART SPICE on a personal computer, in order to simulate the charge pumping technique. An electrical circuit with different mathematical expressions for

some parameters are proposed. The simulated results are in good agreement with recent and different experimental results.

2. T h e m a c r o m o d e l

It is well known that modelling of an electrical circuit consists in establishing an electrical description of its function by means of analytical expressions and schemes. The mathematical model chosen is then a compromise between the reality and the approximation, taking into account the physical and electrical effects of the circuit. However, when analytical models are not available or are impossible or difficult to develop, then macro modelling, which is the approximation of some complex components, is then necessary. The macro models are established by dividing the circuit logically into several groups of components; the circuit is then reconstituted by using the models of the conventional library of these components organized as a circuit. Many models of the MOSFET transistor, with different complexity and sensitivity, are included in SMART SPICE. To develop our m a c r o model, we used the MOSFET LEVEL 1 of SMART SPICE and added to it a current source to simulate the charge pumping current. To consider all the geometrical and electrical parameters, we added several other components as shown in the electrical circuit

0026-2692/98/$19.00 © 1998 Published by Elsevier Science Ltd. All rights reserved PII S0026-2692(97)00022-0

806

F. Djahli, L. Kaabi/Microelectronics Journal 29 (1998) 805-811

,T;

Gate

Source

Drain

t-

M2

VdFB

T

Ef

E GL

E GH

R1

Substrate

--C

D5

C4

02 Fig. 1. The electrical circuit of the macro model. of the macro model in Fig. 1. These different parameters were introduced as explained below.

AV~ = -- N q -Dit - k T In (

2.1. Threshold and flatband voltages

where N = +1 for positive charge and - 1 for negative charge, q is the electron charge (C), Dit is the interface trap density (cm -2 eV-1), Cox is the gate oxide capacitance per unit area (F cm-2), k is the Boltzmann constant (C K-l), T is the absolute temperature (K), NA is the acceptor doping concentration (cm-3), V~ is thermal carrier velocity (cm s-l), an and ap are respectively the capture crosssections for electrons and holes (cmZ), ni is the intrinsic concentration (cm-3), tem,e is the emission time for electrons (s) and tem,his the emission time for holes (s). The variations of Vx and V~ due to the oxide charge are:

To generate the charge pumping current Icp, we must respect two conditions: VGL < VFB and Van > VT, where VGL and Van are respectively the base and the top levels of the gate pulse, V~ is the flatband voltage and VT is the threshold voltage of the transistor to study. As shown in Fig. 1, these two conditions are realized by two switches in series with the voltage sources. The first one (M2) is an n-channel MOSFET, it works only if the gate voltage is greater than its threshold voltage VT2. Then, VT2 is the threshold voltage of the macro model. The second switch (M3) is a p-channel MOSFET, it works only if the gate voltage is lower than its threshold voltage VT3. Then, VT3 is the flatband voltage of the macro model. The gate voltage Van is detected by the diode D1 and the capacitance Cb while VGL is detected by the diode D2 and the capacitance C2. The effects of the oxide and interface charges on VT and VFB are simulated by two voltage sources, VaT and V~B. The variations of VT and V~ due to interface states are obtained by substituting the energy levels corresponding respectively to the emission end of electrons and holes, Eme and Er~, given by [21], into the expressions for AVT and AV~ [3]:

AVT= --Nq DitkTln( Cox

.~2

~

~, Vthapni/em, hJ

(1)

Cox

NA ~

.~

(2)

\ Vthanni tern,e.]

AVT = AVFB = - N q ~ ( 1

- toX~-)

(3)

where No, is the oxide charge number (cm-3), tox is the oxide width (tzm) and X = tox/2, for a uniform charge, is the gravity's centre abscissa of the trapped charges (t~m). The global variations of VT and VFB are then:

AVT=--Nq t°x %x

,aV

+DitkTln{

rNox =-Nqt°XlT+Oi,krln Eoxl.

~ ~] ~ Vthapni/em, h] J

v / ' a NA n \

"X] Jj

th n item, e/

(4)

(5)

By substituting the values of q, Cox,kT and Vtb at 300 K into Eqs. (4) and (5) and by taking an = ap = 10 -16 cm 2, we can calculate the two voltage sources VdT and Va~ from the

F. Djahli, L. Kaabi/MicroelectronicsJournal 29 (1998) 805-811

807

OVR = 0 . 1 V [] VR = 0.3 V ~V

R =0.5

V

VGL = -2 V

z 1

i t i i

~

...........

~. . . . . . . . . . . . . . . . . . . . . . . . . .

,,i. . . . . . . . . . . . . . . . .

2

4

TOP LEVEL OF THE GATE PULSE Vc,H(V) Fig. 2. Charge pumping current Lp versus the top gate pulse level VCHat a base gate pulse level V~L ------2 V, with reverse voltage VR as parameter.

following equations:

VdFB-------4.63

VdT = -- 4.63 × 10-7Ntox

×

10-7Ntox

× - I ~ ° x q-0.025Dit l n (-4 . 7 5 × 10 -12

× [~oxq_0.025Ditln(4.75×10-12

NAIAVGI "~] I~ti] ] (6)

[~TT~--~It;jNABAVG] ~]j (7)

where t r and tf are respectively the rise time and the fall time

of gate pulses (s) and AVG = V~L -- VGH.

OVR = 0.1 V Vg = 0.3 V

[]VR=0.5V VGu= 2 V Z

c~

i

J

-4

-2

BASE LEVEL OF THE G A T E PULSE

VGL(V)

Fig. 3. Charge pumping current lq, versus the base gate pulse level VGLat a top gate pulse level VGH= 2 V, with reverse voltage

V R as

parameter.

808

F. Djahli, L. Kaabi/Microelectronics Journal 29 (1998) 8 0 5 - 8 l l

l~lVl~=01 V oVR - 0 . 3 V

i~Vr~ =0.5 V i AVe= 4 V ,, i i i i

z

LJ

[3

t.I

LA L9

z

c~ t~ L9

J

L)

I

-4

-3

-2

-1

0

LOW GATE PULSE LEVEL VGLFOR A CONSTANT AMPLITUDE AVe (V) Fig. 4. Charge pumping current lop versus the low gate pulse level VGL for a constant amplitude AVe = 4 V and for different values of reverse voltage VR.

2.2. Frequency The voltage source used is the sum of three controlled sources (Fig. 1): EGH, EOL and El, controlled respectively by the voltages VCH, VOL and V(C4). Ef depends on the frequency. The frequency is detected firstly by the

voltage divider (C3, R3), amplified with a gain of 50 (El = 50V(R3)) and detected secondly by (Ds, C4). To avoid the influence of the input signal amplitude on the frequency detection, a voltage limiter (D3, D4, V1, V2, R2) was used.

2.3. Channel length and width and interface state's density The channel length and width (Leffand W) and the interface state's density (Dit) have a direct influence on the charge pumping current. By substituting the values of tem,e and tem,hinto the expression for the charge pumping current Icp [2] and by taking (7n = O'p = 1016 c m 2 , f = 100 kHz, Vth = 10 7 cm s- 1, ni(Si) = 1.45 × 10 10 c m - ,3 q = 1.6 × 10 -19 C and kT = 25 mV at T = 300 K, we obtain:

,._.,

Z

6.

O L9

4-

Icp= 8.256 × 10-16DitLeffW In [14.5 IVFB~VG ] - VTIV/ tr -- tf J/-'--]

(8) L)

To take into account the three parameters Leff, W and Dit, we have inserted a resistance R1 with the voltage source to control the charge pumping current. The current of the macro model will then be:

2-

I

1

I

I

200

400

600

800

Iep =

Ef + EOH + EGL -- VR RI

(9)

FREQUENCY f (KHz) Fig. 5. Maximum charge pumping current lcprnax as a function of the frequency f, for reverse voltage VR = 0.5 V.

with E~H = 0.25VGH, EGL = --0.25VGL and Ef = 4.1 Vat f = 100 kHz.

F. Djahli, L. Kaabi/Microelectronics Journal 29 (1998) 805-811 i

I

l

809 i n

6. <

VR = 0.5 V

I~ Dit = 2.77 101° eV "1

AVc~= 4 V

x Dit = 6.38 101° eV q , Nox= 1 36 1012 cm "2(first stress

f = 100 KHz

(virgin)

[] Dit = 1.16 1011 eV q , Nox=2 1012 em-2 (second stres,, 3

Z 4

2

l

2

?

g

i

....

1

/N

i

,, 1

1 1

-4

-3

-

-2

-1

LOW GATE PULSE LEVEL VGL FOR A CONSTANT AMPLITUDE AVo (V) Fig. 6. Effect of two ageing stresses on charge pumping current Icp(VoL), creating a positive charge at the interface and in the oxide: (a) for a virgin transistor; (b) after a first stress; (c) alter a second stress.

Finally, the charge pumping current will be: Icp----

0"25(V~H-VCL)-V R - [ - 4 " I

for the resistance R 1:

0"25AVG-- VR-F4"I R

R1

R1

R1 (10)

0.25AVe -- VR+ 4.1 I V r - VF.I ~ - l 8.256 X lO-16OitLeffWln 14.5 ]-AV~ X/tr--tf/ (11)

B y e q u a l i z i n g E q s . (8) a n d ( 1 0 ) w e c a n o b t a i n a n e x p r e s s i o n

Va = 0 5 V

20

ODit = 2.77 10 m eV "l 11

(virgin)

I

e V ,Nox=5.53:10 II cm-2 (first stress)

bVc; = 4 V

[~Dit=4.1610

f = 100 KI-Iz

n Dit = 4.7 10 u eV l , No~ = 1.56 10 n cm2 (second stress) i

3 i

,

'

2

10

~a. . . . . . . .

t

r~ o

~. . . . .

,,

/L

i

_4

¸

-2

LOW GATE PULSE LEVEL VtL FOR A CONSTANT AMPLITUDE/SV(~ (V) Fig. 7. Effect of two ageing stresses on charge pumping current Icp(VcL), creating a negative charge at the interface and in the oxide: (a) for a virgin transistor; (b) after a first stress; (c) after a second stress.

F. Djahli, L. Kaabi/Microelectronics Journal 29 (1998) 805-811

810

5 (A)

I'

3

0 -5

-4

-3

-2

-1

0

GATE PULSE BASE LEVEL VOL (V)

20 (B)

b 10

0 oS

-4

-3

-2

-1

0

1

GATE PULSE BASE LEVEL V ~ (V) Fig. 8. Effect of two ageing stresses on experimental charge pumping current Iep(VGL), for uniform Fowler-Nordheim injection. (a) Stress with gate voltage of - 12 V. (b) Stress with gate voltage of + 12 V. Curves a, virgin transistor; curves b, after 100 s; curves c, after 500 s. The charge pumping conditions are VR = 0.5 V, AVG = 4 V , f = 100 kHz. After Here-

roans et al. [3].

3. Results The results obtained are described in Figs. 2 - 7 . Fig. 2 (Icp v e r s u s VGH at VGL = - 2 V) and Fig. 3 (Icp v e r s u s V~L at VoH = 2 V) were obtained for an input triangular pulse at a frequency f = 100 kHz, VR = 0.1 V, 0 . 3 V and 0.5V. These curves show the effect of VR on Icp. We see that Icpmax and Vx decrease when VR increases, but V ~ does not change. The curves of Fig. 4 (/cp v e r s u s VOL at AV~ = 4 V) are obtained for the same values of f and VR. In the macro model, for VR = 0.5 V, we fixed VFB (that is, VT of the TMOS M3) to be - 0 . 4 V, VT (that is, VT of the TMOS M2) to 0.6 V and R1 = 4.57 GfL This value of R1 is calculated from Eq. ( l l ) , with LW = 4 0 0 / . t m 2 and Dit = 2.77 × 10 l° eV -1 cm -2. We also see from these curves that, when VR changes, VT changes but not VFB. Fig. 5 (Icpmaxversus frequency) is obtained for VR = 0.5 V. We show that when the frequency increases, the maximum charge pumping current increases with the same quantity. This seems obvious when we see the mathematical expression of I~p [2].

Figs. 6 and 7 (Icp versus VGL), for a positive and negative charge at the interface and in the oxide respectively, show the effect of two ageing stresses on charge pumping current. The curves (6.1) and (7.1) correspond to a virgin transistor (Dit = 2.77 × 10 l° e V -1 c m -2) with the same conditions used for Fig. 4, but for VR = 0.5 V. The curve (6.2) corresponds to a first stress creating additional charges at the interface and in the oxide (Dit = 6.38 × 101° eV -1 cm -2 and Nox = 1.36 × 1012 cm-2). The parameters of the macro model in this case are R I = 1.99Gfl, VdT = --0.4 V and VdFB = --0.4 V. The curve (6.3) corresponds to a second stress giving Dit = 1.16 x 1011 eV -1 cm -2 and No× = 2 × 1012 cm -2. The macro model parameters are R1 = 1.09 Gfl, VdT = --0.6 V and VdFa = -- 0.6 V. The curves (7.2) and (7.3) also correspond to two different stresses. The first curve (7.2) gives Dit = 4.16 × 1011 eV -1 cm -2 and Nox : 5.53 × 1011 cm -2 for R1 = 0.305 Gfl, VdT = 0.3 V and VdFB -----0.3 V. The parameters of the macro model in this case are R1 = 1.99 Gfl, VdT = -- 0.4 V and VdFB = --0.4 V. The second curve (7.3) corresponds to Dit : 4.7 × 1011 eV -t cm -2 and Nox = 1.56 × 1012 cm -2. The macro model parameters are R1 = 0.2695 Gfl, VdT = 0.6 V and Vd~ = 0.6 V. These results are in good agreement with experimental results of Heremans et al. [3], given in Fig. 8(a) and Fig. 8(b). They also use two different stresses with positive and negative additional charges and their experimental results are closely similar to our simulated results.

4. Conclusion The charge pumping technique being relatively recent, it is not taken into account in electrical simulators such as SPICE or ESACAP. In this paper we have implemented a macro model in the simulator SMART SPICE on a personal computer, in order to simulate this technique. We have proposed an electrical circuit with different mathematical expressions for some parameters. This macro model takes into account all geometrical and electrical parameters of the studied transistor and gives their mathematical expressions. It also gives the different curves of the charge pumping current, which can be obtained experimentally by this technique versus different parameters, before or after different ageing stresses. The results obtained are in good agreement with recent experimental results. This macro model working on personal computer, coupled with experimental results, can be a very good tool for the rapid investigation of degradation in micronic MOS structures.

References [1] J.S. Brugler, G.A. Jespers, Charge pumping in MOS devices IEEE Transactions on Electron Devices 16 (1969) 297-302. [2] G. Groeseneken, H.E. Maes, N. Beltran, R.F. De Keersmaecker, A

F. Djahli, L. Kaabi/Microelectronics Journal 29 (1998) 805-811

reliable approach tc. charge pumping measurements in MOStransistors IEEE Tranaactions on Electron Devices 31 (1984) 42-53. [3] P. Heremans, J. Witters, G. Groeseneken, H.E. Maes, Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation 1EEE Transactions on Electron Devices 36 (1989) 1318-1335. [4] R.G.-H. Lee, J.-S. Su, S.S. Chung, A new method for characterizing the spacial distributions of interface states and oxide-trapped charges in LDD n-MOSFET's IEEE Transactions on Electron Devices 43 (1996) 81-89. [5] C.H. Ling, S.E. Tan, D.S. Ang, A study of hot carrier degradation in NMOSFET's by gate capacitance and charge pumping current IEEE Transaction on Electron Devices 42 (1994) 1321-1328. [6] F. Djahli, J.L. Autran, C. Plossu, B. Balland, Use of the charge pumping technique to understand non-uniform n-channel MOSFET degradation Materials Sciences and Engineering B B23 (1994) 120122. [7] J.L. Autran, F. Djahli, B. Balland, C. Plossu, L.M. Gaborieau, Three level charge pumping; on submicronic MOS transistors Solid-State Communications 84 (1992) 607-611. [8] F. Djahli, C. Plossu, B. Balland, Caract&isation des d6gradations non uniformes dans les MOSFET par la technique de pompage de charge. In: Proceedings of Mediterranean Conference on Electronics and Automatic Control, Grenoble, France, 1995, pp. 531-535. [9] J.L. Autran, F. Seigneur, C. Plossu, B. Balland, Chacterization of Si-SiO 2 interface states: comparison between different charge pumping and capacitance measurements Journal of Applied Physics 74 (1993) 3932-3935. [10] J.L. Autran, B. Ballaad, A new 3-level charge pumping method for accurate determination of interface trap parameters in metal-oxidesemiconductor field-effect-transistors Review of Scientific nstrumentation 65 (1994) 2141-2142. [11] R.E. Paulsen, M.H White, Theory and application of charge

[12] [13]

[14]

[15]

[16] [17]

[18]

[19]

[20]

[21]

811

pumping for the characterization of Si-SiO2 interface and nearinterface oxide traps IEEE Transactions on Electron Devices 41 (1994) 1213-1216. W.L. Tseng, A new charge pumping method of measuring Si-SiO2 interface states Journal of Applied Physics 62 (1987) 591-599. F. Hofmann, W.H. Krautschneider, A simple technique for determining the interface-trap distribution of submicron metal-oxidesemiconductor transistors by the charge pumping method Journal of Applied Physics 65 (1989) 1358-1360. J.E. Chung, R.S. Muller, The development and application of a SiSiO2 interface-trap measurement system based on the staircase charge pumping technique Solid-State Electronics 32 (1989) 867-882. N.S. Saks, M.G. Ancona, Determination of interface trap capture cross sections using three-level charge pumping IEEE Electron Device Letters 11 (1990)339-341. M.G. Ancona, N.S. Saks, Numerical simulation of 3-level charge pumping Journal of Applied Physics 71 (1992) 4415-4421. N.S. Saks, M.G. Ancona, Evaluation of 3-level charge pumping for characterizing intrface traps Applied Physics Letters 60 (1992) 22612263. G. Van Den Bosch, G. Groeseneken, P. Heremans, H.E. Maes, Spectroscopic charge pumping: a new procedure for measuring interface trap distributions on MOS transistors IEEE Transactions on Electron Devices 38 (1991) 1820-1831. F. Djahli, C. Plossu, B. Balland, Micronic N-channel MOSFET's degradation under strong and short time hot-carrier stress Materials Science and Engineering B15 (1992) 164-168. F. Djahli, C. Plossu and B. Balland, Etude des drfauts dans les transistors MOS par les caracteristiques statiques et le pompage de charge. In: Proceedings of 4th International Meeting on Material Sciences, Tlemcen, Algeria, 1993, pp. 216-219. S.M. Sze, Physics of Semiconductor Devices, Wiley and Sons, New York, 1981.