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Predicting reliability of LSI printed circuit carriers
582
World Abstracts on Microelectronics and Reliability
Designing for zero-defect soldering. M. WEINHOLD. Circuit Wld 12 (4), 5 (1986). This paper describes how PCB designers must adjust their approach to take into account the new requirements for the production of high technology printed circuit boards using the latest plated-through hole and surface mounting techniques. It also describes how the correct use of dry film solder masks is contributing towards the achievement of zero-defect soldering~
CMOS test chip design for process problem debugging and yield prediction experiments. W. LUKASZEK,W. YARBROUGH, Z. WALKER and J. MEINDL. Solid St. Technol., 87 (March 1986). A test chip developed for the purpose of direct, unambiguous process problem diagnosis and yield prediction for a two-layer metal, single poly N-well CMOS process is described. Particular attention is devoted to the selection of a complete set of test structures, with special emphasis on defect density monitors. The application of the data obtained to yield prediction experiments is also briefly discussed.
Predicting reliability of LSI printed circuit carriers. J. J. TOMAIN'E. Circuit Wld 12 (3), 14 (March 1986). The arrival of Large Scale Integration (LSI) devices forced the development of products which could reliably package these high density chip carriers. Until LSI, printed circuit technology designers were only moderately challenged to make high density products. This change occurred in the early 1970s at IBM with the printed circuit packaging for the IBM 4300 models. This was the first system application of LSI chip carriers. Since then, numerous LSI printed circuit carrier designs have been used in IBM systems. The methods to predict reliability of the LSI printed circuit carriers have not kept up with the hardware technology. This paper will describe an enhanced method of prediction which more closely represents the performance of today's LSI printed circuit cards and mother boards. Computer processed algorithms will be used to estimate the failure rates of a particular printed circuit carrier and the effects of this estimate on the complete system will be discussed. The estimation algorithms are contained in programmes resident on floppy diskettes and run on an IBM Personal Computer. The flexibility and ease of use of the PC allows the user to make any necessary additions or changes to the algorithms quickly. The algorithms are derived from standard Weibull reliability techniques but include internally derived factors which enhance the accuracy of the Weibull predictions. Data from extensive field reporting of any defects and detailed failure analysis are used to enhance the accuracy of the algorithms. Using the enhanced algorithms, one can generate new estimates easily. Quick access and fast turnaround times result in a convenient and cost effective technique to provide these estimates to system users on a timely basis. Design changes to the carrier which could affect the reliability are quickly modelled in the algorithms and new reliability estimates are provided allowing the final user to make the required system trade-offs easily. These design changes and new reliability projections can be presented to management in a timely manner and allow them to make the cost/performance decisions which result in the optimum marketable product.
Benefits of integrated-circuit burn-in to obtain high reliability parts. DRAGAN PANTIC. IEEE Trans. Reliab. R-35, 3 (1986). The technique of integrated circuit (IC) burn-in is applied industry-wide with the assumption that burned-in ICs have a much lower failure rate during operating life than ICs which are not burned-in. Several years ago this approach was valid for all ICs, but today burn-in procedures for some ICs provide little, if any, benefit. However, some customers still request burned-in ICs, assuming that this will produce better reliability.
This paper provides historical data for linear ICs and presents a procedure to help the user determine if burn-in is worthwhile. An example for linear ICs where minimum benefit produced from burn-in is provided. By repeating this exercise with any other parts, the user can decide whether burn-in will decrease the failure rate appreciably for his application. This article deals specifically with decreases in failure rates through burn-in. It is not within the scope of this paper to describe general factors that could decrease failure rates.
Pb Sn solder for die bonding of silicon chips. HIROKAZU INOUE, YASUTOSHIKURIHARAand HIROAKI HACHINO. IEEE Trans. Compon. Hybrids mfq Technol. CHMT-9, 190 0986). The thermal fatigue life of silicon devices die bonded with lead tin (Pb-Sn) alloys of 14 different compositions, from Pb 3%Sn to Pb 95~oSn was investgated. A silver-plated silicon chip and a nickel-plated copper substrate were soldered together using a piece of thin foil (100tim t) solder. Soldered silicon devices were exposed to thermal cycling tests of - 55 to 150°C (1 cycle h - 1). The thermal fatigue life of a device was defined as the number of thermal cycles when the heat resistance of the device reached 1.5 times its original value. The maximum thermal fatigue life was observed for Pb-50%Sn and was about 9 times that for Pb-5%Sn. Solder grain growth during the thermal cycling was also observed, and scanning electron microscope (SEM) measurements showed that cracks in the solder propagated selectively in the :~ (Pb-rich) region.
Maintenance matters. Electrical fault finding on soldering machines. Part 2. JOHN EDMONDSON. Electron. Prodn, 27 (August 1986). Part l of this article, published in last month's EP, examined the electrical control circuitry and the heating elements employed in soldering machines. This concluding part looks at the motors, relays, contactors, etc.
Corrosion failure of AI-Mg alloy bonding wires in plastic packages. T. H. RAMSEY,J. PETERSON,P. DOUGLASand B. L. GEHMAN. Solid St. Technol., 181 (June 1986). Bonding wire made from A1 alloyed with Mg is normally used to make the electrical interconnections inside hermetic semiconductor packages. The use of AI wire as a replacement for gold in nonhermetic plastic packages would be a considerable economic advantage. An automated ball-bonding process with electronic flame-off and initally designed with A1/Mg wire has been developed; however, intergranular corrosion of the wire was discovered after testing of plastic encapsulated devices in a pressure cooker environment. Theories of the galvanic cell corrosion mechanism are proposed and corrosion failure examples are presented. Proposals for alternative alloys are also discussed.
Reliability assessment of integrated circuits through reverse engineering techniques. M. BAFLEUR and J. Buxo. Microelectron. J. 17 (4), 11 (1986). Scaling down the dimensions of an integrated circuit should be carried out with two main concerns in mind in order to keep high reliability standards: better quality control throughout the fabrication procedure; new circuit architectures compatible with the constraints that prevail at such a high integration level. Reverse engineering techniques can be very useful in order to face these challenges. In this paper, it is shown that the two main techniques: de-layering and microsectioning, are very efficient in controlling the quality of the technology of a circuit. The paper also shows how the lifetime of a circuit showing a defect can be estimated. In addition, examples of circuits that have been reverse engineered in order to obtain the electrical schematic are described. A particular emphasis is given to the circuit information which is most helpful to the designer and which is obtained with such a technique.
World Abstracts on Microelectronics and Reliability
Designing for zero-defect soldering. M. WEINHOLD. Circuit Wld 12 (4), 5 (1986). This paper describes how PCB designers must adjust their approach to take into account the new requirements for the production of high technology printed circuit boards using the latest plated-through hole and surface mounting techniques. It also describes how the correct use of dry film solder masks is contributing towards the achievement of zero-defect soldering~
CMOS test chip design for process problem debugging and yield prediction experiments. W. LUKASZEK,W. YARBROUGH, Z. WALKER and J. MEINDL. Solid St. Technol., 87 (March 1986). A test chip developed for the purpose of direct, unambiguous process problem diagnosis and yield prediction for a two-layer metal, single poly N-well CMOS process is described. Particular attention is devoted to the selection of a complete set of test structures, with special emphasis on defect density monitors. The application of the data obtained to yield prediction experiments is also briefly discussed.
Predicting reliability of LSI printed circuit carriers. J. J. TOMAIN'E. Circuit Wld 12 (3), 14 (March 1986). The arrival of Large Scale Integration (LSI) devices forced the development of products which could reliably package these high density chip carriers. Until LSI, printed circuit technology designers were only moderately challenged to make high density products. This change occurred in the early 1970s at IBM with the printed circuit packaging for the IBM 4300 models. This was the first system application of LSI chip carriers. Since then, numerous LSI printed circuit carrier designs have been used in IBM systems. The methods to predict reliability of the LSI printed circuit carriers have not kept up with the hardware technology. This paper will describe an enhanced method of prediction which more closely represents the performance of today's LSI printed circuit cards and mother boards. Computer processed algorithms will be used to estimate the failure rates of a particular printed circuit carrier and the effects of this estimate on the complete system will be discussed. The estimation algorithms are contained in programmes resident on floppy diskettes and run on an IBM Personal Computer. The flexibility and ease of use of the PC allows the user to make any necessary additions or changes to the algorithms quickly. The algorithms are derived from standard Weibull reliability techniques but include internally derived factors which enhance the accuracy of the Weibull predictions. Data from extensive field reporting of any defects and detailed failure analysis are used to enhance the accuracy of the algorithms. Using the enhanced algorithms, one can generate new estimates easily. Quick access and fast turnaround times result in a convenient and cost effective technique to provide these estimates to system users on a timely basis. Design changes to the carrier which could affect the reliability are quickly modelled in the algorithms and new reliability estimates are provided allowing the final user to make the required system trade-offs easily. These design changes and new reliability projections can be presented to management in a timely manner and allow them to make the cost/performance decisions which result in the optimum marketable product.
Benefits of integrated-circuit burn-in to obtain high reliability parts. DRAGAN PANTIC. IEEE Trans. Reliab. R-35, 3 (1986). The technique of integrated circuit (IC) burn-in is applied industry-wide with the assumption that burned-in ICs have a much lower failure rate during operating life than ICs which are not burned-in. Several years ago this approach was valid for all ICs, but today burn-in procedures for some ICs provide little, if any, benefit. However, some customers still request burned-in ICs, assuming that this will produce better reliability.
This paper provides historical data for linear ICs and presents a procedure to help the user determine if burn-in is worthwhile. An example for linear ICs where minimum benefit produced from burn-in is provided. By repeating this exercise with any other parts, the user can decide whether burn-in will decrease the failure rate appreciably for his application. This article deals specifically with decreases in failure rates through burn-in. It is not within the scope of this paper to describe general factors that could decrease failure rates.
Pb Sn solder for die bonding of silicon chips. HIROKAZU INOUE, YASUTOSHIKURIHARAand HIROAKI HACHINO. IEEE Trans. Compon. Hybrids mfq Technol. CHMT-9, 190 0986). The thermal fatigue life of silicon devices die bonded with lead tin (Pb-Sn) alloys of 14 different compositions, from Pb 3%Sn to Pb 95~oSn was investgated. A silver-plated silicon chip and a nickel-plated copper substrate were soldered together using a piece of thin foil (100tim t) solder. Soldered silicon devices were exposed to thermal cycling tests of - 55 to 150°C (1 cycle h - 1). The thermal fatigue life of a device was defined as the number of thermal cycles when the heat resistance of the device reached 1.5 times its original value. The maximum thermal fatigue life was observed for Pb-50%Sn and was about 9 times that for Pb-5%Sn. Solder grain growth during the thermal cycling was also observed, and scanning electron microscope (SEM) measurements showed that cracks in the solder propagated selectively in the :~ (Pb-rich) region.
Maintenance matters. Electrical fault finding on soldering machines. Part 2. JOHN EDMONDSON. Electron. Prodn, 27 (August 1986). Part l of this article, published in last month's EP, examined the electrical control circuitry and the heating elements employed in soldering machines. This concluding part looks at the motors, relays, contactors, etc.
Corrosion failure of AI-Mg alloy bonding wires in plastic packages. T. H. RAMSEY,J. PETERSON,P. DOUGLASand B. L. GEHMAN. Solid St. Technol., 181 (June 1986). Bonding wire made from A1 alloyed with Mg is normally used to make the electrical interconnections inside hermetic semiconductor packages. The use of AI wire as a replacement for gold in nonhermetic plastic packages would be a considerable economic advantage. An automated ball-bonding process with electronic flame-off and initally designed with A1/Mg wire has been developed; however, intergranular corrosion of the wire was discovered after testing of plastic encapsulated devices in a pressure cooker environment. Theories of the galvanic cell corrosion mechanism are proposed and corrosion failure examples are presented. Proposals for alternative alloys are also discussed.
Reliability assessment of integrated circuits through reverse engineering techniques. M. BAFLEUR and J. Buxo. Microelectron. J. 17 (4), 11 (1986). Scaling down the dimensions of an integrated circuit should be carried out with two main concerns in mind in order to keep high reliability standards: better quality control throughout the fabrication procedure; new circuit architectures compatible with the constraints that prevail at such a high integration level. Reverse engineering techniques can be very useful in order to face these challenges. In this paper, it is shown that the two main techniques: de-layering and microsectioning, are very efficient in controlling the quality of the technology of a circuit. The paper also shows how the lifetime of a circuit showing a defect can be estimated. In addition, examples of circuits that have been reverse engineered in order to obtain the electrical schematic are described. A particular emphasis is given to the circuit information which is most helpful to the designer and which is obtained with such a technique.