Process alternative: SOI for heterogeneous systems

ELSEVIER

Microelectronic

Process alternative:

SO1 for heterogeneous

Engineering

54 (2000) 49-62

systems

D. Flandre Microelectronics

Laboratory,

Place du Levant 3, 1348 Louvain-la-Neuve,

1. INTRODUCTION SOI stands for Silicon-on-Insulator. The basic difference with conventional bulk silicon indeed lies in the starting material (Fig. 1): - in bulk Si, the active devices are built atop the surface of a wafer of monocristalline silicon. - in SOI, the top Si active layer is separated from the mechanical substrate by a thick underlying insulating layer, which leads to a number of advantageous device and circuit properties when compared to bulk Si. Eased CMOS processing, excellent device scalability, better device and circuit performance and potentially lower cost are among the reasons why SOI technology is considered as a serious contender for the fabrication of future integrated circuits [I].

Belgium

In the present paper, a review of the evolution of the material, devices and circuit applications will first demontrate that SO1 has now reached maturity. SOI technology has indeed evolved from a mere laboratory curiosity in the early ’80s to a technology in which large circuits such as 16 Mbit DRAMS [2, 31 or a 550 MHz 1.8 V Power PC microprocessors [4] have been realized. Since August 1998, IBM and other major semiconductor IC suppliers have of their SOI announced the industrialisation processes [5]. We will then focus on a number of particular application fields for which SOI has proved very promising: i.e. low-power, high-performance, hightemperature, digital, analog and microwave circuits. For each domain we will discuss the SOI capabilities and possible problems.

Bulk CMOS

SO1 CMOS

Fig. 1: Cross-sections of bulk and SOI CMOS inverters pointing out major advantages of SO1 over bulk: (a) reduced parasitic capacitance, (b) increased radiation hardness against single events, (c) reduced junction leakage at high temperatures, (d) easier inter-device isolation without latch-up structures and subsequent increase of integration density, (e) inherent shallow junction structure without Al spiking effects.

SO

2. EVOLUTION AND CIRCUITS.

D. Flandre

OF

MATERIAL,

I Microelectronic

DEVICES

2.1. SOI substrates.

Early SOI research was devoted to finding replacement material for the costly and poor-quality Silicon-on-Sapphire or SOS substrates, primarily used in military and aerospace applications since the 70s for their excellent radiation-hardness. Three main techniques eventually reached industrial maturity and commercial availability, namely SIMOX, BESOl and more recently, Smart-Cut, according to defect, reproducibility or manufactu-rability issues [I]. SIMOX (Separation by IMplantation of Oxygen) material is produced by an implantation of a high dose of oxygen ions (typically 1.8 1018 cmm2)into a silicon wafer, followed by annealing at very high temperature (1325’C) to finally form a very welldefined buried silicon dioxide layer beneath a singlecrystal silicon overlayer (Fig. 2.A). Large SIMOX wafers (up to 8”) with low defect densities have been commercially available since a number of years and already used to fabricate high-performance circuits. Bonding and Etch-back SO1 or BESOI consists in the bonding of two thermally-oxidized standard Si wafers, followed by the thinning of one side by mechanical, chimical or plasma etching (Fig. 2.B). In principle BESOl can provide defect-free Si overlayer. However a quality of the SIMOX material which BESOl is missing is the relatively wellcontrolled thickness of the top Si film (down to f 1 nm) which is required for the fabrication of very thin-film SOI devices (thickness < 100 nm). BESOI therefore remains mainly devoted to very thick film applications, e.g. smart power. Smart-Cut material was developed recently out of an original combination of ion implantation and bonding techniques (Fig. 2.C) [6]. In order to solve the control problem of thin film thicknesses in BESOI, a starting wafer A is implanted with hydrogen ions at a low depth below a previously grown oxide. In a second step it is bonded to oxidized wafer B. After activation, the assembly can be accurately split at the level of the hydrogen implant since hydrogen ions have the property to weaken the Si atoms bonds. Smart-Cut features

Engineering

S4 (2000)

49-62

many advantages with regards to SIMOX and BESOI considering throughput and film thickness control. After just a few years of development, 8inch Smart-Cut wafers already achieve the same quality and cost as SIMOX material does after twenty years. The future also looks very bright since the technique can be easily extended to 300-mm wafers. Smart-Cut material is commercialized in large volumes by SOITEC, Grenoble, which opened a dedicated facility with I million wafers per year production capability. 2.2. SO1 CMOS processes. Partially-depleted (PD) SOS or SOI MOSFETs (Fig. 3) are long-known to feature degraded electrical characteristics due to floating substrate effects (FBE) [I], originating from the quasi-neutral region which is sandwiched between the isolation oxides and the front/back interface and source/drain space charge regions and hence left unconnected or floating. Under normal operating conditions, the potential of this quasi-neutral region is defined by the currents of forward-biased source and reverse-biased drain junctions and therefore remains close to the source voltage, so that the device behaves similarly to a conventional bulk MOSFET. However, for drain voltages large enough to generate significant impact ionization in the pinch-off region, a phenomenon known as the kink effect occurs (Fig. 3). Impact ionization creates excess electron-hole pairs. In a nMOSFET, the electrons flow to the drain, whereas the holes flow towards the lowest potential node. In a bulk Si device, the excess holes are evacuated by the substrate or well contact, whereas in a PD SOI MOSFET, they have to be recombined at the source junction, thus forward biasing it. The quasi-neutral region potential increases, leading to a reduction of the threshold voltage which, in turn, yields an increase of the drain current and hence of the impact ionization hole current . . . until this positive feedback mechanism is limited when the source junction forward bias achieves 0.6-0.7 V. FBEs in PD SO1 MOSFETs do not restrict to a static degradation of the output conductance in saturation which is detrimental for analog applications, they also lead to a number of dynamic phenomena which may alter the functionality or timing of digital circuits [4, 71.

D Handre

1 Oxrn

ionimplarion

I Microelectronic

Engineering

-74 (2000)

49-62

1 S~hcon overlayer

Silicon substrate

I

Si wafer

I

I

I

Polishing/etching VlUSSVV

(future SO1layer) Z//f//W///////i )SiO2

//y///////////L

r""'*'/""'l Si-handle wafer H+ implant

C

+j++ij+_ Wafer A

,,/,

Wafer A / ,,,/, Wafer B

~

Wafer bonding

.

Wafer A splitting igure 2: Fabrication process for SIMOX (A), BESOI (B) and Smart-Cut (C) SO1 w Fers

On the contrary, MOS transistors realized on SO1 films thin enough to allow the depletion region to extend accross the whole film (Fig. 5) feature dramatically reduced FBEs due to the reduction of the source barrier. Furthermore they even exhibit superior device characteristics over bulk MOSFETs as will be discussed later. The main drawback of fully-depleted or FD devices is the sensivity of the threshold voltage to the film thickness and buried oxide parameters, the latter ruling out the use of thin-film FD SO1 devices for total-dose radiationhard applications. Threshold voltage dependence on the film thickness can however be minimized holding the film total dose constant rather than the doping concentration [S]. Threshold voltage standard deviations similar to bulk devices have been achieved for FD SO1 MOSFETs.

The use of thin-film SO1 substrates, in which, by definition, the lateral isolation field oxide extends down to the buried oxide providing complete dielectric isolation of neighbour devices, considerably eases the fabrication of deep-submicron MOS devices either FD or PD. When compared to conventional bulk process, threshold voltage roll-off is indeed minimized, reliable ultra-shallow junctions are easily processed, wells and latch-up ate suppressed and complicated lateral isolation process can be avoided. In addition, although defect densities may still be higher in SIMOX films than in bulk substrates, SOI process yield may actually be higher than that of bulk since SOI devices and circuits are much more tolerant to defects [ 11.

D. Flandre 1 Microelectronic Engineering S4 (2000) 49-62

52 2.3. Perspectives.

In August 1998 IBM announced plans to rampup its SO1 technology towards, firstly, the fabrication of commercial high-speed microprocessors [5]. IBM choosed to rely on its ownfabricated SIMOX material and on a PD SO1 CMOS process which at that time, at the industrial level, proved to be more reliable to scale below 0.2 pm channel lengths than FD devices requiring very thin SO1 films in order to control the short-channel effects. Inherent PD floating-substrate effects are controlled at the design level by proper simulation and timing of critical digital paths [9]. Nevertheless FD processing has proved the best option for 0.25 pm and above and its controllability is improving at a rapid pace. Scalability towards sub-O.13 l.trn dimensions has now been demonstrated on 30 nm-thin SO1 films [lo]. The cost issue may then be the last problem delaying the use of SOI for industrial applications. SIMOX or Smart-Cut substrates are indeed still about 3 times more expensive than identical size and comparable quality bulk Si wafers. Nevertheless a Sematech study demonstrated that if the higher starting cost could be reduced to a factor of 2, the revenues to be made from mass production of 64 Mb SRAM could be substantially higher using a SOI instead of a bulk CMOS process for reasons such as fewer processing steps, better fabrication yield,

smaller chip size and enhanced performance [l I]. More recently, IBM claimed that, even considering the present cost of their SIMOX substrates, the total “SO1 wafer + CMOS process” fabrication is only 10 % more expensive than the corresponding bulk Si CMOS process. Furthermore SO1 material cost decrease could be driven by the development of a high-volume application such as DRAMS. SOI implementation of DRAMS was only considered with the advent of stacked memory capacitors built atop the cell transistors, DRAMS on SO1 have been tested and showed considerable improvements over bulk counterparts in cell area and access time [ 121. The challenges for LVLP analog and microwave SOI CMOS circuits, however, have not been as widely investigated so far. Preliminary results nevertheless show that SOI properties may lead to the future development of single-chip mixed digital/analog/microwave solutions, as will be discussed in detail hereafter. A last evolution of Sol applications is related to the field of integrated sensors. High-precision thin membranes can indeed be easily processed on SO1 substrates owing to the good control of the film and buried oxide thicknesses. High-performance pressure sensors [ 131 as well as accelerometers have already been produced.

VGf

Kink effect r--------..,

I

VGb

Drain

voltage

Figure 3: Typical PD SOI MOSFET structure and ID-VD curves for various gate biases.

D. Flnndre

3. LOW-POWER

DIGITAL

I Microelectronic

APPLICATIONS.

SOI CMOS is considered as a very attractive technology for the realization of low-voltage lowpower (LVLP) digital ULSI circuits [14]. The power and speed performance of simple logic gates are usually characterized by means of the following relationships: Power =: F * C * (Vdd)2 and Delay =: (C*Vdd)/(K*(Vdd-Vto)2), where F is the frequency, C the capacitance, Vdd the supply voltage, Vto the threshold voltage and K a constant which is in particular inversely proportional to the body factor. The simultaneous reduction of power and delay can then only be achieved by reducing the capacitance which is a long-known advantage of SOI. Another way to preserve the speed performance while reducing the supply voltage is to decrease the threshold voltage. In bulk, this can only done at the expense of an increase of the leakage current and hence of static power dissipation. FD SOI offers the opportunity to limit that degradation as will be discussed hereafter [15]. These characteristics all add up to significantly increase the power.delay capability, in particular for reduced supply voltages. 3.1. Capacitance

reduction.

It has long been recognized that the SOI dielectric isolation provides much reduced parasitic capacitances when compared to bulk CMOS. In the

Engineering

.54 (2000)

49-Q

53

latter case, the source/drain loads indeed correspond to junction capacitances which depend on substrate or well doping and bias voltage. The technological trend towards scaled dimensions and supply voltages inherently leads to an increase of the source/drain junction capacitances per unit area. In thin-film SOI, the source/drain capacitances are now mainly defined by the buried oxide thickness and hence tremendously reduced when compared to bulk, both regarding the bottom area and sidewall components (Fig. 4). The parasitic capacitances of polysilicon and metal interconnection layers will also be reduced in SOI due to the presence of the thick buried oxide, but in a lesser extend depending on the technological metal stack height. 3.2. Fully-depleted

SO1 MOSFETs.

One interesting feature of FD SOI MOSFETs is the low value of the body-effect coefficient, noted n, which is an image of the ideality of the coupling between gate voltage and surface potential. Using the intuitive model of Fig. 5, in a bulk transistor, n is given by %i

n=l+

Cox Xdmax ’ where Xdmax is the maximum depletion width in strong inversion. In a I pm (resp. 0.25) bulk CMOS, n is equal to I .4 -1.6 typically (resp. 1.2 1 3).

Bulk CMOS cjn = 0.18 / C& = 0.4 EF/& cjswn = OA ! Cjswp 2 0.5 fF/Rm

SO1 CMOS % = 0.061 cjp

= 0.06 m/&m2

Cjswn * 0.05 I Cj,+rp t 0.05 m/pm %lY C,,ll

bulk I SOI = 1.5 bulk / SO1 = 1.3

Figure 4: Comparison of bulk and SOI junction capacitances for a typical I pm CMOS process (Cj and Cjsw denote the bottom area and sidewall peripheral junction components at zero bias).

D. Flandre I Microelectronic

54

Bulk Si MOSFET

Engineering .54 (2000) 49-62

Fully-depleted SOI MOSFET vG ‘-C

cd .*".'.'.'.:.;*:~~::~:::: I T -Cot lG

Ifs2

Cat

wsl

03

cd

I

VB

VB Figure 5: Comparison of bulk and SO1 MOSFET space charge regions and body effect models.

In a SO1 FD MOS transistor, on the other hand, the body effect is given by

n=l+*,Y

G I .05 to 1.I typically for a 1 urn process (about 1.02 for 0.25 urn process), where Coxb and tsi am the buried oxide capacitance and the silicon film thickness, respectively. The influence of the body-effect coefftcient on the current drive of the device can best be understood by using a simple model of the saturation drain current: lDsat = &

P Cox ;(VGS-VTH)2

9

u being the effective mobility, VCS the gate-tosource bias, VTB the threshold voltage and W and L the width and length of the device resp. From the above equations, it follows that the saturation drain current may be 30-40% higher in a FD SOI device than in a bulk device with similar parameters. The subthreshold swing (inverse subthreshold slope) of a MOSFET is also affected by the body effect as follows:[ I] S (mV/dec) = n y

ln(lO),

if the influence of the interface traps is neglected. The low value of n in FD SO1 yields an improvement of the subthreshold slope over bulk devices. Almost ideal subthreshold swings of 60 mV/dec at room temperature have indeed been

experimentally demonstrated for optimally designed FD SO1 MOSFETs with channel lengths down to 0.2 urn [l6]. As a result, a lower threshold voltage can be used in SOI devices without jeopardizing the OFF leakage current (Fig. 6), and ON drive current much higher than in bulk devices can be obtained, in particular for reduced supply voltage (Fig. 7).

3.3. High-performance

circuits.

The impact of the improved FD SOI CMOS characteristics on speed and power consumption has already received a lot of attention in digital circuitry. ASICs and gate arrays have been realized showing speed improvement factors over bulk counterparts up to a factor of 1.7, under 3 V power supply [ 171. 1M gate array built on a 0.5 urn FD SOI CMOS showed twice the speed or half the power consumption of similar bulk CMOS circuits when operated at 2 V supply voltage [ 171. It can be evaluated that around 40 % of the improvement results from the capacitance reduction and the other 60 % from the drive current increase. A threefold enhancement of the power times speed figure of merit has been demonstrated for 1 V supply voltage, in particular in the case of a 5 12K SRAM [ 181. A 0.25 pm 625 Mhz 1.5 V fully-depleted SOI CMOS 64-b microprocessor recently demonstrated simultaneous increase of speed by 30 % and decrease of power by a factor of 3.3 when compared to the bulk equivalent [191.

D. Flandre I Microelectronic Engineering S4 (2000) 49-62

-14 -0.5

1.0 0.0

Fig. 6: Subthreshold

4. High-performance

1.0 0.5 Gate Voltage (V)

1.5

2.0

curves of bulk and FD MOSFETs.

0123456 Supply

voltage

(V)

Figure 7 : Ratio of FD to bulk saturation

currents

analog applications.

Although SO1 properties such as the reduction of parasitic capacitances or the feasibility of diffusion resistors free of junction effects could have long been of interest for analog applications, these have not been widely investigated in the past, mainly because the degradation of the PD SOI MOSFET output characteristics by floating-substrate effects strongly limited analog performances. In the next paragraphs, we will briefly present the impact of the major FD SOI MOSFET analog characteristics on the performance of the main analog building blocks.

and still remains higher in FD SOI than in comparable bulk MOSFETs (Fig. 8). The combination of this gm/ID improvement with the reduction of the parasitic capacitances can be exploited to boost the performances of SO1 CMOS amplifiers over bulk implementations by a factor between 3 to 10, in terms of either the transition (unity-gain) frequency, the circuit area, the dc open-loop gain or the stand-by current [ 151.

4.1. Amplifiers.

.:

The transconductance-to-drain current ratio (gm/]D) directly conditions the open-loop gain and transition frequency of operational amplifiers [ 151. The largest value of gm/]D is obtained in the weak inversion regime for MOS transistors [20]: ln(10) gm ZZ-= dtD_ S =&. ID dVG i;;5

The low body-effect coefficient of SOI devices thus allows for obtaining near-optimal micropower designs (gm/ID values of 35 V-l are obtained close to the maximum physical value at room temperature, while gm/tD reaches only values of 25 V-l in bulk MOSFETs) (Fig. 8). In strong inversion, the gm/lD becomes (for long-channel devices):

n

I

v -6 10

.;

~ ‘: I

I_._ \

1o-4 I~~.Co,.W/L)

1o-2 +:,

q loo

Figure 8: Experimental (symbols) and modeled (lines) Transconductance over drain current ratios vs. Normalized drain current in saturation: (a) Bulk (x) and SO1 (0) measurements, (b) EKV model [21] with n = 1.1 (---) or I S (-).

56

D. Flundre

/ Microelectronic

4.2. The CMOS analog switch. The CMOS analog switch combining parallel nMOS and pMOS transistors with complementary inverted gate signals is a key block of sampled-data analog circuits. A well-known problem of this structure is that the switch on-resistance increases when the supply voltage is lowered. It may even peak to very high values for mid-range input signals when VDD is decreased below a value which can be estimated by 2VTH/(2-n), assuming identical threshold voltage and body effect parameters for nand p-MOSFETs [22]. FD SO1 CMOS featuring reduced values for these parameters clearly allows for correct switch operation at much lower voltages than in bulk [ 151 (Table 1). Techno

n

VW

V dd.

Bulk

1.5

0.7

3.0

so1

1.1

0.7

1.7

so1

1.1

0.4

1.0

Table 1: Minimum

Vdd = 2.VTH/(2-n).

5. MICROWAVE

APPLICATIONS.

Engineering

54 (2000)

49-62

The microwave performance can be characterized in terms of the current gain, H21, maximum available gain, MAG, and unilateral gain, ULG, obtained as a function of frequency (Fig. IO). Unitycurrent gain frequency, fT (defined by H2] = 0 dB), and maximum oscillation frequency, fmax (defined by ULG = 0 dB), may achieve 12.9 GHz and 30 GHz, respectively, under a supply voltage of 1 V only, even for 0.75 urn-long FD SOI MOSFETs. Such devices show an excellent “fmax / (length x power)” figure of merit (Table 2) and are therefore suitable for low-voltage, low-power communication applications. Please also note from Table 2 that the noise figure and associated gain values at 2 GHz are competitive with other technologies.

min

The possibility to realize SOI wafers on highresistivity Si substrates (5,000 or 10,000 R.cm) yields both active and passive devices which offer very interesting microwave performances [23,24].

Fis microwaie

SO1 MOS tr&sistor.

5.1. Device characteristics. Microwave devices require silicidation of the gate, source and drain regions to lower the access For example, using nickel series resistances. silicidation, the gate sheet and total source/drain series resistances of FD devices fabricated on only 80-nm thick SO1 film can be as low as 2.9 Q/square and 550 Q.um, respectively [25]. For comparison, similar devices processed with TiSi2 and CoSi2 silicides show gate sheet resistances of 6.2 Q/square and 4.4 Q/square resp., and source/drain resistances of 700 Q.um and 290 Q.pm resp. In order to obtain optimized high-frequency performances, a multiple-fingers comb-like gate structure has to be used in the microwave MOSFET design (Fig. 9).

1 10 Frequency (GHz) Figure 10: Current gain (H21), maximum available gain (MAG) and unilateral gain (ULG) in a FD SOI nMOSFET (W/L=lOx24um/0.75um) with Nisi.

Il. Flandrp

/ Microelectrr~nic

ID (m@

3 0.2 0.75

2 1.5 -i-

The potential of SOI CMOS technology on high-resistivity substrate has been demonstrated by the implementation of operational amplifier classical architectures with transition frequencies above 1 GHz, without the need for extra compensation technique (e.g. feed forward) to boost the frequency performances [30]. Such wideband amplifiers may be used for analog signal processing at intermediate RF frequencies in communication systems.

fT (GHz)

34 12.9

Furthermore, the use of high-resistivity substrates reduces the source/drain-to-substrate parasitic capacitances and substrate crosstalk to very small values, especially when above a certain relaxation frequency, neither the minority nor the majority carriers may respond to the HF excitation (Fig. 11) [29]. This important transition occurs for much lower frequencies in high-resistivity substrates than for standard-resistivity. Accurate SO1 substrate capacitance modelling can be achieved from the series combination of the imaginary part of the admittance corresponding to the MOS capacitance with the substrate characterized by its thickness, permittivity and resistivity parameters (Fig. I I).

The SOI implementation of RF LNA amplifiers has also been investigated, e.g. [31]. In addition to the better SOI device characteristics, the improvement of the quality factor of integrated inductors thanks to the buried oxide has lead to the realization of l-4 GHz LNAs with higher gain, lower noise and power supply figures in SOI than in bulk CMOS. On another hand, simulations have shown that, in FD I urn SOI CMOS, balanced resistive mixers may be used with LO frequencies as high as 10 GHz [28]. Preliminary measurement results confirmed the exceptional linearity of the SOI resistive cell. Resistive mixers are expected to feature very low levels of intermodulation distortion, but the very low body effect of FD SOI MOSFETs may still enhance the linearity when compared to bulk CMOS. This is a capital advantage for the implementation of receivers for mobile environments in which perturbations may cause substantial signal fading, thus requiring the receiver to have large dynamic range.

6. HIGH-TEMPERATURE

10

10

10

57

49-62

5.2. Circuit implementations.

23.6 24 6.5

54 (2000)

These different properties are of tremedous interest for microwave circuit applications.

Table 2: Performances and characteristics of microwave n-channel SO1 MOSPETs (from top to bottom: [23], [26], [27], [28])

“D W)

Engineering

10

10

10

IO9

Frequency (Hz) Figure I I : Measured (0) and simulated source/dminto-substrate capacitances per unit area for nMOSFETs realized on 8 Qcm (--) and 200 Qcm (-) SIMOX substrates,

APPLICATIONS.

A large number of applications may benefit from the development of electronics systems capable of operation in harsh environments featuring ambient temperatures up to several hundreds degrees Celsius [32]. Considering that conventional electronic circuits are, in the best case, rated for operation up to 150°C only, the need for the development of specific high-temperature semiconductor technolo-gies, devices and circuits arises, Silicon-on-Insulator

58

D. Flandre

I Microelectronic

emerging as the most serious contender for operation in the range 200-400% 6.1. MOS devices at high temperature The correct operation of Si MOS circuits is significantly affected by the drift of current-voltage curves with temperature. Typical static device characteristics (Fig. 12) clearly show that on the contrary to SOI, bulk Si MOSFETs present, above 2OO”C,drastically reduced ON-to-OFF current ratios and threshold voltage values which are not compatible with acceptable noise margins in digital circuits or with bias stability in analog. In bulk Si and PD SOI MOSFETs, threshold voltage Vth decreases with depletion width by 2 to 5 mV/“C [33], whereas the junction leakage current 1. is proportional to drain junction area (AjD) and ni4 since dominated by diffusion mechanisms of excess caniers in the quasi-neutral transition regions (Fig 13). We have observed that typical bulk Ijs rises to about 0.1 uA per urn of device width at 250°C. In PD SOI, thanks to dielectric isolation, AjD is typically two orders of magnitude smaller than in bulk and so is ljs. In FD SOI, the depletion extension being equal to the film thickness, it remains constant with temperature and Vth shifts ate reduced to 0.7 to 1.5 mV/‘C [34]. Furthermore, as quasi-neutral regions are suppressed, only generation

1o-4 3

1o-5 1o-6

I

I

Engineering

10

-4 7

-6 10 z Z'O

-8 -

!i 3 -10 c IO 'a b

-12

\ Ileak

Gate Vdtage (V) Figure 12: Drain current vs gate voltage curves of SOI (solid line) and bulk (dashed) 2015 p-MOSFETs with Vd=3V.

I

2 -

3 10.’ t -8 5 10 0 -9 0 10 -10 2

49-62

mechanisms may contribute to Ijs which is then proportional to ni and the depletion region volume and hence, almost three orders of magnitude lower than in bulk at 300°C.

8’

-

S4 (2ooO)

I

I

I

I

1.2

G$ 10 s

10 -11 -

.E lo -12 CI 10 -13_ 10 -140

100

200

300

Figure 13: Ijs and Vth evolutions with temperature for bulk (+) and FD SO1 (0) MOSFETs (W = 20 pm).

D Flandre I Microelectronic Engineering S4 (2000) 49-62

59

6.2. Digital HTE circuits

6.3. Analog HTE circuits

Bulk CMOS logic gates show a large degradation of their static switching characteristics at high temperature : logic levels and noise margins are considerably degraded due to leakage current increase and threshold voltage decrease. Furthermore total non-functionality can be observed due to the induction of latch-up by thermally generated leakage currents. In all SOI CMOS digital cells, stand-by power dissipation remains within acceptable levels as a result of unique layout considerations in addition to the device behaviour [34], since there is no leakage to substrate. The leakage current flows within each device from drain to source so that there is only one leakage path. For example, the measured standby currents of bulk Si and PD SOI CMOS 64 kb SRAMs [35 increase with temperature following a ni1 dependency, the latter being almost two orders of magnitude lower than the former due to drain junction area reduction (Fig. 14). However extrapolating these values for a IMb SRAM of interest for future VLSI applications, we end up with a static power dissipation under 5 V operation larger than I W at 300°C even with PD SOI technology ! This seems to definitely prevent the use of bulk Si and even PD SOI CMOS for VLSI integration at elevated temperature, on the contrary to FD SOI.

In operational amplifiers (opamps) and other analog implementations in which correct circuit operation requires an almost constant bias current to flow in series-device branches, the development of large leakage currents from device terminals towards the substrate alters the branch bias and hence the circuit properties. This phenomenon occurs in junction isolated technologies such as bulk Si CMOS. Gate leakage in MESFET or JFET-type technologies causes similar problems. Design solutions have been proposed to compensate leakage and maintain bias by adding compensation diodes, balancing n- and p-type device leakages . . . [36]. Such complicated design tricks lead to increases of area, power consumption and complexity to such an extent that the dynamic performance of bulk Si CMOS opamps may be severely compromised. On the contrary, dielectric isolation such as in SOI CMOS offers a direct process solution, since leakage currents always flow from drain to source. It follows that classical opamp architectures and design techniques do not have to be adapted for hightemperature SOI CMOS operation. Based on gm/lD measurement and design technique, a number of FD SOI CMOS OTAs (Operational Transconductance Amplifier) have been realized and successfully tested up to more than 300°C [37, 381.

64

150

200

Kb

I MbSRAM

250

Temperature (“C) Figure 14: Bulk Si and PD SO1 CMOS 64 Kb SRAM standby current dissipation vs temperature and extrapolation of standby power dissipation for I Mb SRAM under 5 V supply operation.

60

D. Flandre

I Microelectronic

Engineering

S4 (2000)

49-62

6.4. One-chip HTE systems

7. CONCLUSION

The implementation of high-temperature electronics systems using only a few VLSI chips is needed to increase the reliability and decrease the weight and space, the fabrication, installation and maintenance costs, the power consumption.. . of complex applications. An interesting example is the Actuator Control Electronics Module targeted for completely distributed control in future All Electrical Aircrafts and operation up to 200°C for the wings and empennage, 315°C for the engines [39]. ACE modules will require high-speed data bus interface, large memories, powerful microprocessor, precision analog functions as well as power drivers [40]. The development of such systems is still years ahead but a few circuits already aim in this direction, such as an integrated solenoid driver developed in a 1.2 urn PD SOI CMOS technology [41], as well as an integrated precision pulse-width controlled current source also developed in PD SOI CMOS [42]. It is interesting to note that when considering fairly complex circuits, the technology choice limits to SOI. However the two previous examples use PD SO1 CMOS which may not achieve the million of transistors on a chip for power dissipation considerations as discussed above.

SOI CMOS is now regarded as a very attractive and mature technology for the realization of lowvoltage low-power (LVLP) digital ULSI circuits for a number of well-known advantages over conventional bulk Si CMOS : - dielectric isolation provides reduced parasitic capacitances and leakage currents when compared to junction isolation. - full-depletion (FD) operation of thin-film SOI MOSFETs may yield quasi-ideal device properties such as sharper subthreshold slope, lower body effect and smaller vertical field mobility degradation. Improved subthreshold slopes in turn allow for the use of lower threshold voltages for identical subthreshold leakage current values. These characteristics all add up to significantly increase the drive capability, in particular for reduced supply voltages. - thinned films and dielectic isolation result in simplified submicron CMOS processes : threshold voltage roll-off is minimized, reliable ultra-shallow junctions are easily obtained, wells and latch-up are suppressed and complicated lateral isolation process can be avoided.

In addition to the high-temperature VLSI compatibility of FD SO1 CMOS digital gates and opamps reported above, other analog components paving the way towards the integration of a full sensing chain at 300-350°C have been presented in this technology, in particular: - first- and second-order MOSFET-C continuoustime filter sections [43]. The cut-off frequencies can be tuned in the audio band controlling the gate voltage of the MOSFET resistors, so that nominal cut-off can be maintained in the temperature range up to 300°C. - a second order SIGMA-DELTA analog to digital modulator with switched capacitor integrator showing a maximum SNR of 60dB and a dynamic range of I I bits at room temperature [44]. Resolution at 250°C is still 9 bits. The circuit shows functionality up to 35O’C.

Over the years, many circuit developments have confirmed the technology benefits, i.e. - digital components with enhanced speed and static and dynamic power performance; - analog components with enhanced speed, precision, power, swing and noise performance; - and microwave components with enhanced gain, frequency, linearity and power performance over bulk counterparts. An interesting example concerns the feasibility of realizing smart card ICs with improved performance in SOI technology as demonstrated in [45]. Smart cards have indeed recently evolved towards very complex systems-on-a-chip, thereby opening new opportunities and creating new demands on fabrication technologies for higher integration density as well as lower power, lower voltage and in a near future contactless operation. Based on the analysis of the structure of a smart card chip and the literature, we concluded that CPU, clock generation circuits based on PLL and the three

61

D. Flandre I Microelectronic Engineering S4 (2000) 49-62 required

types

non-volatile

of memory

EEPROM

(i.e.

or

ROM,

Flash

already been demonstrated in performance compatible with application CMOS

and significantly

counterparts.

increased over bulk-Si

Furthermore,

and supply

voltage

required

analog

random

number

regulation

been reported in SOI [45]. The most properties voltage

for smart

without

potential

cards are the lower

SOI

helps

improve

allowing

is made more difficult. less

recognized

easy.

in

under

high

three

internal

SOI

PI

PI

ways. power external

circuits

are

and radiations,

and digital

functions

temperature CMOS large

the

system

be required for high-

implementations,

only

may fit the needs. The major Si

CMOS

circuits

for

SOI

limitation

of

high-temperature

VLSI

Technology

(Kyoto,

http://www.eet.com/news/98/1020news/ ibmtakes.html

bl

M.

IEE Electronics

Bruel,

Lett.,

31 (1995)

1201.

[71 D. Flandre, IEEE Trans. on Electron Devices, 40 (1993) 1789-1796. PI M.J. Sherony et al, IEEE Electron Device Letters, I6 (1995) 100. [91 C.T.

large range of analog

that will

on

[51

[lo] considering

H.S. Kim et al, in Digest of Technical Papers,

Symposium

[31 J.W. Park et al, IEEE Journal of Solid-State Circuits, 34 (1999) 1446. [41 A.G. Aipperspach et al, IEEE Journal of SolidState Circuits, 34 (I 999) 1430.

already considered for attacks. Finally,

J.P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Aca. Publ., 199 I.

Japan), 1995, pp. 143-144

and

in harsh environments,

temperatures

REFERENCES

probing

reducing

SOI makes their Finally,

RF

attacks

algorithms

Secondly,

to operate well

especially

operating

against

security

for denser layouts,

and current consumption, probing

SOI

loss of speed, the simultaneous

and the enhanced security

Firstly,

have also

attractive

aiming to decode their secret internal data.

and have

SOI, exhibiting the smart card

blocks such as charge pump circuits, generator

RAM

EEPROM)

(USA, [ll]

Chuang,

P.F.

Lu

and

C.J.

Anderson,

Proceedings of the IEEE, vol. 86, no4 C. Raynaud et al, Proc. IEEE Int. SOI Conf. T.D.

1999) 86-87. Stanley,

Electrochemical [12] T. Eimori

Proceedings Society,

et al., Technical

volume

93-29,

the

p. 303, 1993. Digest of IEDM,

p.

45, 1993.

operation

has been linked to static power dissipation

[13] M. lshida et al., Electronics Letters, 26 (1990)

and

conclude

775. [I41 Z.J. Lemnios and K.J. Gabriel, IEEE Design and Test of Computers, I I (I 994) 8. [ 151 D. Flandre et al, Int. Journal of Analog Integrated Circuits and Signal Processing, 2 1 (1999) 213. [I63 S. Krishnan et al, in Proceedings of the IEEE International SOI Conference, pp. 10-I 1, 1995. [I73 T. Iwamatsu et al, in IEDM Technical Digest

we

from

the

investigation

leakage current phenomenon

of

in Si CMOS

devices

and circuits that, regarding

the limits of integration,

- bulk

be

Si

components

CMOS

and temperatures

and require complex -

may

to

SSI/LSI

l75-225°C

design procedures;

partially-depleted

LSINLSI

limited of about

the

SOI

components

CMOS

operating

may

provide

up to 250-300°C

but still require specific design techniques: - whereas potential

fully-depleted for very

SOI

large-scale

operating above 300°C techniques.

CMOS integration

and designed

shows

the

of circuits

using standard

(Washington

DC), 1993, pp. 475-478

et al, in Extended Abstracts of the I994 Int. Conf on Solid State Devices and Materials (Japan), 1994, pp. 265-267. [I91 S.B. Park et al, IEEE Journal of Solid-State Circuits, 34 (1999) 1436. [20] E.A. Vittoz, in IEEE Int. Solid-State Circuits Conf (San Francisco CA), 1994, pp. l4- 18. [2l] C. Enz, F. Krummenacher and E.A. Vittoz, Analog Integrated Circuit and Signal Processing, 8 ( 1995) 83. [22] E.A. Vittoz, in Proc. 23rd ESSDERC (Grenoble, France), 1993, pp. 927-934 [I81 G.G.

Shahidi

62

D. Flarzdre I Microelecrronic Engineering 54 (2000) 49-62

[23] M.H. Hanes et al, IEEE Electron Device Letters, 7 (I 993) 2 19. [24] A.L. Caviglia et al, IEEE Electron Device Letters, I2 (1991) 26. [25] J. Chen et al, Journal of Electrochemical Sociely, 144 ( 1997) 2437-2442. [26] A. Hiirrich et al, Proc. IEEE Int. SO/ Conference, p. 130, 1996.

[27] LETI, private communication, 1997. [28] L. DemeQs et al, URSf Int. Symp. on Signals, Systems and Electron. (Italy, act. 1998) 134. [29] J.P Raskin et al, IEEE Trans. on Electron Devices, 44 (I 997) 2252 [30] J.-P. Eggermont et al, IEEE Journal of SolidState Circuits, 33 (1998) 640. [31] W. Jin, P. Chan and C. Hai, Proc. IEEE Int. SOI Conf. (1999) 16-17. [32] Shorthouse G. and Lande S, Proc. 3rd Int. High Conf. Temperature Electronics (Albuquerque, USA), pp. 1.3-8, June 1996. [33] Shoucair F.S et al, Microelectron. Reliab., 24 (1984) 465 and 487. [34] D. Flandre, Materials Science & Engineering B, 29 (1995) 7. [35] Brusius P. et al, 3rd Int. High Temp. Electron.

Conf. (USA), pp. X1.3-8, June 1996. [36] F.S. Shoucair, IEEE Trans. on Comp. Hybrids and ManujY Tech., 9 (I 986) 242. [37] J.-P. Eggerrnont et al, /EEE Journal of SolidState Circuits, 3 I (I 996) 179. [38] B. Gentinne et al, Materials Science and Enginneering - B, 46 (I 997) I.

[39] K. Reinhardt and M. Marciniak, Proc. 3rd Int. Conf. High Temperature Electronics (Albuquerque, USA), pp. 1.9-15, June 1996. [40] C.M. Carlin et al, 2nd Int. High Temp. Electron. Conf. (USA), pp.]. 19-26, June 1994. [41] J.B. McKitterick et al, Proc. 3rd Int. High Temp. Electron. Conf. (USA, 1996), pp. XV. 17-22. [42] M. Verbeck and H.-L. Fiedler, Proc. 3rd lnt. Conf. High Temperature Electronics (Albuquerque, USA), pp. Xl.2 1-26, June 1996. [43] V. Dessard et al, IEEE lnt. SO1 Conf. (Fort Myers, USA), pp. 24-25, October 1996. [44] A. Viviani, D. Flandre, P. Jespers, IEE Electronics Letters., 35 ( 1999) 749-75 1. [45] A. N&e, D. Flandre, J.-J. Quisquater, USENLY workshop on smartcard technology (USA, June 1999) l-7.