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SOI wafer flow process for stencil mask fabrication
IVIICIE)~gi~ON1¢ ELSEVIER
Microelectronic Engineering 46 (1999) 4 7 3 - 4 7 6
SOI Wafer Flow Process for Stencil Mask Fabrication* J. Butschke, A. E h r m a n n a, B. H6ffiinger, M. Irmscher, R. K/ismaier a, F. Letzkus, H. L6schner b, J. Mathuni a, C. Reuter, C. Schomburg, R. Springer Institut fiir Mikroelektronik Stuttgart, Allmandring 30a, 70569 Stuttgart, G e r m a n y a Siemens AG, Otto-Hahn-Ring 6, 81739 Miinchen, Germany b Ionen Mikrofabrikations Systeme GmbH, Schreygasse 3, 1020 Wien, Austria Phone +49 711 685 5882, Fax +49 711 685 5930
A high yield fabrication process for stencil m a s k using SOI material is presented. Membranes and masks from different base materials have been fabricated. The stress of the membrane, depending on the doping level, has been determined. Initial pattern displacement m e a s u r e m e n t s have been performed.
1. I N T R O D U C T I O N As optical lithography seems to come to an end, a new lithography generation has to be developed for the future. For the new exposure tools, it will also be necessary to develop a new generation of masks. Concerning the Ion Projection Lithography (IPL) which is designed for a 100nm technology and below, so called stencil m a s k s are needed [1]. These m a s k s consist of a thin silicon m e m b r a n e where the t r a n s p a r e n t pattern are openings in this foil. As the IPL technology works with a 4x reduction, the minimum feature size on the m a s k is 400nm for 100nm on the wafer plane. In general, the fabrication processes of stencil masks can be divided into two main concepts: the Membrane Flow Process (MFP) and the Wafer Flow Process (WFP). Running the MFP, as a first step a membrane will be formed as a kind of m a s k blank. All process steps for p a t t e r n definition then have to be done on the membrane. Running the WFP, the m e m b r a n e etching is the last step which
means that all significant steps of p a t t e r n definition take place on a solid wafer. This means that all steps can be done using standard process tools and standard Si wafer fabrication processes. There is also a clear separation between the "microelectronical" part (pattern definition) and the "micromechanical" part (membrane etching) which minimizes the risk of contamination. There are also some flows mixing both concepts [2]. The advantage of using SOI material for stencil mask fabrication is the insulator layer acting as a stop layer for the p a t t e r n etching and the membrane etching. This allows separation of both steps and running a full WFP.
2. P R O C E S S F L O W Base materials for this process are SOI wafers which m a y be SIMOX~, SDB or Poly SOI. Properties such as thickness, conductivity or mechanical stress of the membrane are directly determined by the properties of the SOI layer.
• This work is supported by the Bundesministerium fiir Bildung, Wissenschaft, Forschung und Technologie (01 M 2983 B). The authors alone are responsible for the contents.
0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved. PII: S0167-9317(99)00043-X
J. Butschke et al. / Microelectronic Engineering 46 (1999) 473-476
474
2.1 B a s e Material As the quality of the SOI material used directly determines the properties of the membrane, it is necessary to use high-end wafers. Simulations show t h a t the thickness uniformity of the SOI layer has to be _+1%. A second point of importance is the shape of the entire SOI wafer concerning bow, w a r p and total thickness variation. 2.2 S t r e s s E n g i n e e r i n g To obtain a flat m e m b r a n e on the one hand and minimize the distortion on the other hand, it is necessary to adjust the internal mechanical stress to a optimal value. This can be done by doping the SOI layer [3]. Depending on the different atomic ratio compared to silicon (1.18A), the implantation of boron (0.80~,) and phosphorus (1.10A) will create tensile stress while arsenic (1.22A) will create compressive stress. By choosing the right dose and heat treatment, stress can be varied over a wide range.
SOl wafer
~
~
.
Nitride and SiON deposition
E-beam lithography ,lli=lnigllnl
Hardmask structuring
IIIIIII
,lilill,uilnll
Figure 1: SOI WFP.
,
~ -:
Trench etching and patterning back side window
Deposition of protection layer
Membrane etching
Removal of all remaining layers
Figure 1: SOI W F P (cont.).
2.3 F a b r i c a t i o n S t e p s Figure 1 shows the main process steps of the SOI WFP. At first, a nitride layer is deposited on the backside of the wafer which will later act as a wet etch mask. Then a layer of SiONy acting as hard mask is deposited on the front side. The stress of this layer m u s t be chosen carefully to keep the bow of the wafer as small as possible. The lithography then is done using a Hitachi HL700D electron beam direct writer and TSI resist technology [4]. By plasma etching, the p a t t e r n is transferred into the hard mask. After removing the resist, a silicon trench etching process is used to transfer the hard m a s k pattern into the 3pm thick SOI layer. A special demand of IPL is the need of stencil structures with retrograde openings which could be achieved by a special trench etching process (Fig. 2). This will ensure that during ion illumination, the ions do not scatter at the sidewalls, which would lead to unacceptable image degradation. The next step is to open a backside window in the nitride, defining the size of the later membrane. The process flow on the wafer is finished after the deposition of a protection
J. Butschke et al. / Microelectronic Engineering 46 (1999) 473-476
475
layer onto the stencil pattern. The following m e m b r a n e wet etch process is a two step process using KOH etch solution and an etch cell for the first step. The second step runs without an etch cell using tetra methyl ammonium hydroxide as etching solution. This combination guarantees a high reliability of the membrane etching process [5]. During the last process step, all layers are removed. The result is a patterned membrane foil surrounded by a wafer ring. For the use with an ion projector, an additional layer has to be deposited on top of the membrane to protect it against ion irradiation damage. For helium ions, this can be a sputtered carbon film [6].
3. M E A S U R E M E N T S For measurement, several structured and also unstructured membranes have been taken out of the manufacturing process. 3.1 M e m b r a n e S t r e s s A horizontally mounted membrane will sag due to gravitation. The value itself depends on the intrinsic stress of the membrane. By measuring this distance and comparing it to a finite element (FE) simulation, a value can be determined. The m e a s u r e m e n t has been done with an optical long-scan profiler [7].
Figure 3: P a t t e r n of the test mask. 3.2 R e g i s t r a t i o n a n d CD Based on 150mm SOI wafers, test stencil m a s k s are fabricated with a m e m b r a n e diameter of 126mm and a patterned area of 60mmx60mm (Fig. 3). With exception of the areas A and B, the field is filled with square holes of 50pm x 501~m separated by 50pm which results in an open area of 25%. Area A is filled with a test design consisting of square holes in sizes ranging between 0.5 ]lm and 2 pm. Area B is filled with a 5mm x 5mm standard design with linewidths down to 0.7 pm. A support grid to prevent the loss of structures due to doughnut problems is supplemented (Fig. 4). For registration and CD uniformity m e a s u r e m e n t with Leica LMS IPRO, a grid of 13 x 13 crosses of nominal linewidth of l p m and a size of 11 x 11 1Llm2 is also implemented. During the measurement, the m a s k has been placed on a quartz glass substrate.
4. R E S U L T S A N D D I S C U S S I O N
Figure 2: Trench on SOI with retrograde shape.
4.1 M e m b r a n e S t r e s s The bow values b of five SOI m e m b r a n e s are listed in Table 1. As a result of the FE
476
J. Butschke et al. / Microelectronic Engineering 46 (1999) 473-476
SOI Material SDB SDB Poly Poly Poly
No.
1 2
i3 4 5
Dope none 5E15~ B none le16, P 2e16, P
Bow [pan] 9 <1 180 45 12
Stress [MPa] 2.6 >23 (compr.) 0.5 2
Table 1: Membrane Stress vs. Doping. simulation, the stress of such a membrane without perforation can easily be calculated according to Eq. 1. Comparing the stress values of m e m b r a n e 1 and 2, the effect of increasing the internal stress by doping is obvious. It is even possible to change the stress from compressive to tensile (No. 3 to 5). 233 MPa
o" = T
(i)
4.2 R e g i s t r a t i o n a n d CD For all measurements, a stencil mask with an internal stress similar to membrane 1 has been used. The m e a s u r e d repeatability of this m a s k is approximately as good as it is for chromium masks. Ten measurements cycles were executed. The m a x i m u m value was 4nm, the 3~ value was 2nm. The repeatability measurements are done without touching the mask during the entire measuring period.
Figure 4: Structure with support grid.
Accuracy however, is defined as the maximum or 3~ deviation of m e a s u r e m e n t s before and after turning the m a s k by 90 ° . The values are calculated after introducing a scaling and angle correction. For a stencil membrane, a 3~ of 24nm has resulted. This is a value similar to values received by standard wafer measurements. Concerning the registration m e a s u r e m e n t of a stencil mask, a m a x i m u m 3~ of 176nm has resulted. As the e-beam writing tool used for pattering has a specification of 150nm registration 3~, up to now we can only see that the contribution of the e-beam writer is the most important factor for this distortion measuring result. Also first CD linewidth results have been obtained. The maximum values for repeatability are 27nm in the x direction and 20nm in the y direction. This is not as good as for chromium masks. The reason is t h a t the vibrations of the mask in the airflow lead to a larger inaccuracy of the single m e a s u r e m e n t images.
REFERENCES [1] H. L6schner, G. Gross, I. L. Berry, "Ion Projection Lithography", White Paper submitted to SEMATECH, Sept. 1997 [2] I. W. Rangelow et al., "PN-junction Based Wafer Flow Process for Stencil Mask Fabrication", EIPBN'98 [3] F. Shi, "Na~chemische ,~tzprozesse z. Mikrostrukturierung des Siliziums fiir die Mikromechanik", Diss., Kassel, 1994 [4] M. Irmscher et al., '~rsI Process at and below Quarter Micron Resolution and Pattern Transfer into Metal", E I P B N '97, 27 - 30 May 1997 [5] Patent IMS Chips [6] J . R . Wasson et al., "Ion absorbing stencil mask coatings for ion beam lithography", J. Vac. Sci. Technol. B15, Nov/Dec 1997 [7] UBM GmbH, Ettlingen, G e r m a n y
Microelectronic Engineering 46 (1999) 4 7 3 - 4 7 6
SOI Wafer Flow Process for Stencil Mask Fabrication* J. Butschke, A. E h r m a n n a, B. H6ffiinger, M. Irmscher, R. K/ismaier a, F. Letzkus, H. L6schner b, J. Mathuni a, C. Reuter, C. Schomburg, R. Springer Institut fiir Mikroelektronik Stuttgart, Allmandring 30a, 70569 Stuttgart, G e r m a n y a Siemens AG, Otto-Hahn-Ring 6, 81739 Miinchen, Germany b Ionen Mikrofabrikations Systeme GmbH, Schreygasse 3, 1020 Wien, Austria Phone +49 711 685 5882, Fax +49 711 685 5930
A high yield fabrication process for stencil m a s k using SOI material is presented. Membranes and masks from different base materials have been fabricated. The stress of the membrane, depending on the doping level, has been determined. Initial pattern displacement m e a s u r e m e n t s have been performed.
1. I N T R O D U C T I O N As optical lithography seems to come to an end, a new lithography generation has to be developed for the future. For the new exposure tools, it will also be necessary to develop a new generation of masks. Concerning the Ion Projection Lithography (IPL) which is designed for a 100nm technology and below, so called stencil m a s k s are needed [1]. These m a s k s consist of a thin silicon m e m b r a n e where the t r a n s p a r e n t pattern are openings in this foil. As the IPL technology works with a 4x reduction, the minimum feature size on the m a s k is 400nm for 100nm on the wafer plane. In general, the fabrication processes of stencil masks can be divided into two main concepts: the Membrane Flow Process (MFP) and the Wafer Flow Process (WFP). Running the MFP, as a first step a membrane will be formed as a kind of m a s k blank. All process steps for p a t t e r n definition then have to be done on the membrane. Running the WFP, the m e m b r a n e etching is the last step which
means that all significant steps of p a t t e r n definition take place on a solid wafer. This means that all steps can be done using standard process tools and standard Si wafer fabrication processes. There is also a clear separation between the "microelectronical" part (pattern definition) and the "micromechanical" part (membrane etching) which minimizes the risk of contamination. There are also some flows mixing both concepts [2]. The advantage of using SOI material for stencil mask fabrication is the insulator layer acting as a stop layer for the p a t t e r n etching and the membrane etching. This allows separation of both steps and running a full WFP.
2. P R O C E S S F L O W Base materials for this process are SOI wafers which m a y be SIMOX~, SDB or Poly SOI. Properties such as thickness, conductivity or mechanical stress of the membrane are directly determined by the properties of the SOI layer.
• This work is supported by the Bundesministerium fiir Bildung, Wissenschaft, Forschung und Technologie (01 M 2983 B). The authors alone are responsible for the contents.
0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved. PII: S0167-9317(99)00043-X
J. Butschke et al. / Microelectronic Engineering 46 (1999) 473-476
474
2.1 B a s e Material As the quality of the SOI material used directly determines the properties of the membrane, it is necessary to use high-end wafers. Simulations show t h a t the thickness uniformity of the SOI layer has to be _+1%. A second point of importance is the shape of the entire SOI wafer concerning bow, w a r p and total thickness variation. 2.2 S t r e s s E n g i n e e r i n g To obtain a flat m e m b r a n e on the one hand and minimize the distortion on the other hand, it is necessary to adjust the internal mechanical stress to a optimal value. This can be done by doping the SOI layer [3]. Depending on the different atomic ratio compared to silicon (1.18A), the implantation of boron (0.80~,) and phosphorus (1.10A) will create tensile stress while arsenic (1.22A) will create compressive stress. By choosing the right dose and heat treatment, stress can be varied over a wide range.
SOl wafer
~
~
.
Nitride and SiON deposition
E-beam lithography ,lli=lnigllnl
Hardmask structuring
IIIIIII
,lilill,uilnll
Figure 1: SOI WFP.
,
~ -:
Trench etching and patterning back side window
Deposition of protection layer
Membrane etching
Removal of all remaining layers
Figure 1: SOI W F P (cont.).
2.3 F a b r i c a t i o n S t e p s Figure 1 shows the main process steps of the SOI WFP. At first, a nitride layer is deposited on the backside of the wafer which will later act as a wet etch mask. Then a layer of SiONy acting as hard mask is deposited on the front side. The stress of this layer m u s t be chosen carefully to keep the bow of the wafer as small as possible. The lithography then is done using a Hitachi HL700D electron beam direct writer and TSI resist technology [4]. By plasma etching, the p a t t e r n is transferred into the hard mask. After removing the resist, a silicon trench etching process is used to transfer the hard m a s k pattern into the 3pm thick SOI layer. A special demand of IPL is the need of stencil structures with retrograde openings which could be achieved by a special trench etching process (Fig. 2). This will ensure that during ion illumination, the ions do not scatter at the sidewalls, which would lead to unacceptable image degradation. The next step is to open a backside window in the nitride, defining the size of the later membrane. The process flow on the wafer is finished after the deposition of a protection
J. Butschke et al. / Microelectronic Engineering 46 (1999) 473-476
475
layer onto the stencil pattern. The following m e m b r a n e wet etch process is a two step process using KOH etch solution and an etch cell for the first step. The second step runs without an etch cell using tetra methyl ammonium hydroxide as etching solution. This combination guarantees a high reliability of the membrane etching process [5]. During the last process step, all layers are removed. The result is a patterned membrane foil surrounded by a wafer ring. For the use with an ion projector, an additional layer has to be deposited on top of the membrane to protect it against ion irradiation damage. For helium ions, this can be a sputtered carbon film [6].
3. M E A S U R E M E N T S For measurement, several structured and also unstructured membranes have been taken out of the manufacturing process. 3.1 M e m b r a n e S t r e s s A horizontally mounted membrane will sag due to gravitation. The value itself depends on the intrinsic stress of the membrane. By measuring this distance and comparing it to a finite element (FE) simulation, a value can be determined. The m e a s u r e m e n t has been done with an optical long-scan profiler [7].
Figure 3: P a t t e r n of the test mask. 3.2 R e g i s t r a t i o n a n d CD Based on 150mm SOI wafers, test stencil m a s k s are fabricated with a m e m b r a n e diameter of 126mm and a patterned area of 60mmx60mm (Fig. 3). With exception of the areas A and B, the field is filled with square holes of 50pm x 501~m separated by 50pm which results in an open area of 25%. Area A is filled with a test design consisting of square holes in sizes ranging between 0.5 ]lm and 2 pm. Area B is filled with a 5mm x 5mm standard design with linewidths down to 0.7 pm. A support grid to prevent the loss of structures due to doughnut problems is supplemented (Fig. 4). For registration and CD uniformity m e a s u r e m e n t with Leica LMS IPRO, a grid of 13 x 13 crosses of nominal linewidth of l p m and a size of 11 x 11 1Llm2 is also implemented. During the measurement, the m a s k has been placed on a quartz glass substrate.
4. R E S U L T S A N D D I S C U S S I O N
Figure 2: Trench on SOI with retrograde shape.
4.1 M e m b r a n e S t r e s s The bow values b of five SOI m e m b r a n e s are listed in Table 1. As a result of the FE
476
J. Butschke et al. / Microelectronic Engineering 46 (1999) 473-476
SOI Material SDB SDB Poly Poly Poly
No.
1 2
i3 4 5
Dope none 5E15~ B none le16, P 2e16, P
Bow [pan] 9 <1 180 45 12
Stress [MPa] 2.6 >23 (compr.) 0.5 2
Table 1: Membrane Stress vs. Doping. simulation, the stress of such a membrane without perforation can easily be calculated according to Eq. 1. Comparing the stress values of m e m b r a n e 1 and 2, the effect of increasing the internal stress by doping is obvious. It is even possible to change the stress from compressive to tensile (No. 3 to 5). 233 MPa
o" = T
(i)
4.2 R e g i s t r a t i o n a n d CD For all measurements, a stencil mask with an internal stress similar to membrane 1 has been used. The m e a s u r e d repeatability of this m a s k is approximately as good as it is for chromium masks. Ten measurements cycles were executed. The m a x i m u m value was 4nm, the 3~ value was 2nm. The repeatability measurements are done without touching the mask during the entire measuring period.
Figure 4: Structure with support grid.
Accuracy however, is defined as the maximum or 3~ deviation of m e a s u r e m e n t s before and after turning the m a s k by 90 ° . The values are calculated after introducing a scaling and angle correction. For a stencil membrane, a 3~ of 24nm has resulted. This is a value similar to values received by standard wafer measurements. Concerning the registration m e a s u r e m e n t of a stencil mask, a m a x i m u m 3~ of 176nm has resulted. As the e-beam writing tool used for pattering has a specification of 150nm registration 3~, up to now we can only see that the contribution of the e-beam writer is the most important factor for this distortion measuring result. Also first CD linewidth results have been obtained. The maximum values for repeatability are 27nm in the x direction and 20nm in the y direction. This is not as good as for chromium masks. The reason is t h a t the vibrations of the mask in the airflow lead to a larger inaccuracy of the single m e a s u r e m e n t images.
REFERENCES [1] H. L6schner, G. Gross, I. L. Berry, "Ion Projection Lithography", White Paper submitted to SEMATECH, Sept. 1997 [2] I. W. Rangelow et al., "PN-junction Based Wafer Flow Process for Stencil Mask Fabrication", EIPBN'98 [3] F. Shi, "Na~chemische ,~tzprozesse z. Mikrostrukturierung des Siliziums fiir die Mikromechanik", Diss., Kassel, 1994 [4] M. Irmscher et al., '~rsI Process at and below Quarter Micron Resolution and Pattern Transfer into Metal", E I P B N '97, 27 - 30 May 1997 [5] Patent IMS Chips [6] J . R . Wasson et al., "Ion absorbing stencil mask coatings for ion beam lithography", J. Vac. Sci. Technol. B15, Nov/Dec 1997 [7] UBM GmbH, Ettlingen, G e r m a n y