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Quick and exhaustive descrambling methodology for high-density static random access memories using voltage contrast
ELSEVIER
Microelectronic
Engineering
25 (1994) 35-48
Quick and exhaustive descrambling methodology for highdensity static random access memories using voltage contrast F. Marc, Laboratoire ML,
H. Fremont,
P. Jounet,
Y. Danto
Universitt de Bordeaux I, 351 tours de la Libtration,
F-33405
Talence cedex, France
Abstract The external test previous to any failure analysis of a static RAM provides the logical address of each failure. We developed a methodology allowing a fast mapping of SRAMs, passivated or not, by voltage contrast in a scanning It uses voltage coding and the phase-selective voltage electron microscope, with minimum initial information. contrast. The first observations permit to distinguish the row bits from the column bits, and to sort the address bits according to the order of geometrical binary weight. The second part of the mapping consists in determining the symmetries associated with each address bit. Voltage coding observation needs only a few images. The second method requires at least as many images as address bits, but can be efficiently used with buried lines. This methodology was designed to be efficient whatever the matrix map may be. It was applied successfully on 64 kbit to 1 Mbit passivated CMOS SRAMs. Keywords:
Voltage
contrast,
SRAM;
Descrambling;
Descrambling
methodology
1. Introduction The increasing complexity in VLSI circuits leads to a need for new external and internal testing techniques. Electron beam tester (EBT) appears as an attractive tool for failure analysis, and many techniques associated with the potential contrast phenomenon have been developed [l-3]. Faced with a real case failure analysis, the analyst has to choose more adapted techniques to be sure to localize the failure as rapidly as possible. After an external testing, the analyst should be able to define a small number of possible faulty functions. The aim of the following internal test is to geometrically localize them. Some comparison methods have been described [4,5] but these methods need either a “golden” device or information about the layout of the circuit. In the situation where these elements are not available, we propose a location methodology taking only into account the function of the circuit. In a static random access memory (SRAM), the functions considered to be faulty after an external test can often be associated with a group of logical addresses. Therefore the location of the failure can be done through the map of the memory cells matrix. The matrix structure 0167-9317/94/$07.00 0 1994 Elsevier SSDI 0167-9317(94)00004-E
Science
B.V. All rights reserved
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F. Marc et al. I Microelectronic
Engineering
25 (1994) X-48
of SRAMs leads to a good discrimination between the location of the decoding function on the one hand and of the memorizing function in the memory cells on the other hand. Observation by means of an optical microscope allows to count the number of row lines and column lines for example by following tracks from the connection pad corresponding to data pins of the the device. Thanks to assumptions described later concerning the regularity of the correspondence between logical addresses (at the level of the pins of the device) and physical addresses
Frangois Marc was born in 1966 in France. He received the Electronics Engineer Diploma from ENSERB in 1989. He is currently working for his Ph.D. on failure analysis through electron beam testing, in the failure analysis and reliability group in the IXL Laboratory (University of Bordeaux, France).
HCICne Frbmont was born in 1963 in France. She received the Electronics Engineer Diploma from ENSERB in 1986. From 1986 to 1988 she worked in the Texas Instrument France failure analysis laboratory and received the Ph.D. at the University of Bordeaux in 1988. After a Post-Dot at the University of Hannover (Germany), she joined the failure analysis and reliability group in IXL, Laboratory of Microelectronics (University of Bordeaux. France) in 1989: her basic research topic is Electron Beam Testing.
Paul Jounet was born in 1947. He received the Ph.D. from the department of Electronics. at the University Pierre and Marie Curie, Paris (France) in 1978. Since 1988, he joined the failure analysis and reliability group in IXL, Laboratory of Microelectronics (University of Bordeaux, France). His research topics include technological and comportemental analysis.
Yves Danto was born in 1942 in France. After his studies at the university where he obtained his Ph.D. and his “Doctorat d’etat”, he joined the University of Bordeaux (France), where he has been Professor since 1982. He is in charge of the failure analysis and reliability group in IXL, Laboratory of Microelectronics.
F. Marc et al. / Microelectronic Engineering
25 (1994) 35-48
37
(corresponding to the effective location of the memory cells in the chip), the mapping process consists in the following steps: - determination of the address bits associated either with the row lines or with the column lines; - inside these two groups, classification of the address bits according to the areas they allow to reach. We define a geometrical weight of an address bit as the mean distance between lines or columns corresponding to two addresses whose bits are all identical to zero except for the one we want to evaluate; - when the data bus consists of several bits, determination of the matrix areas (blocks) associated with each of these bits; - finally, determination of the isometry (symmetry or shift) associated with the state changing of each address bit. Among the many observation techniques available in scanning electron microscopy, we have essentially retained two imaging techniques: voltage coding and phase-selective voltage contrast. According to its features, each technique is used depending on the quality of the image and the amount of observations investigated. Fig. 1 shows the different steps of the developed methodology as well as the imaging techniques used. After a justification of the choice of the two imaging techniques, this paper sets out a fast VLSI SRAM descrambling methodology using voltage contrast on a scanning electron microscope (SEM). Practical case studies, on a large range of passivated SRAMs from different manufacturers, prove the efficiency of the method.
2. Choice of the observation
techniques - Application
to SRAMs
The aim of the presented methodology is to descramble static RAMS with an electron beam tester using only image mode. To choose the observation techniques, we have taken advantage of the structural properties of SRAMs, that is to say: - matrix organisation of the memory cells, with two perpendicular axes of parallel trips; - primarily combinational functionality as soon as the device is fixed either in read or in write mode (the R/W control bit is constant). The possible presence of a passivation layer was also taken into account. We chose imaging rather than measurement techniques because they are easier to implement and they give much more general information. The layout of the circuit before any observation was unknown. The combinational functionality of the memories permitted to first leave aside some techniques devoted to temporal behaviour, such as frequency mapping or tracing. For the same reasons, stroboscopic methods have not been used, especially because they are difficult to use on passivated devices without multisampling systems, due to charging effects. Voltage coding (VC) is sensitive to charging effects similarly to the stroboscopic method: the beam reaches each point of the circuit at a constant level of the signal. However, as the beam is continuously scanned over the device, the signal can be observed near its transitions in a satisfactory way. Moreover, information given by a VC image is very rich, and well adapted to the matrix structure of the memories.
F. Marc et al. I Microelectronic
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2-5 (1994) 35-48
columns & rows
if several data bits columns _________________________ 1 determination I of blocks j distribution i among data i bits ~--_-_-___________________ _________I columns
voltage co&ast
& rows
determination of isometries
quality ? bad
goodf
choice of the analyst : reliability or urgence ? + exhaustive m
ep Fig. 1. Principle
+ g&&C e
\ “auick” a
of the memory 1 of the methodology.
Contrary to the previous methods, the phase-selective voltage contrast (PSVC) method [3] is not sensitive to charging effects, because no synchronism exists between the applied signal and the beam scanning. PSVC can be used because SRAMs can be considered as combinatorial circuits. (It may be somewhat complicated on sequential circuits because it involves patterns of two vectors.) It has been considered as an alternative to VC when the latter has reached its limits: if VC images provide more than 30 logical states of the memory on a single image, it may be difficult to distinguish between the electrical signal and the topography. PSVC permits to obtain a better display. This is especially true for buried conductors. Unfortunately, PSVC provides information concerning only two logical states on a single image.
F. Marc et al. I Microelectronic Engineering
3. The methodology
for descramhling
25 (1994) 35-48
39
SRAMs
3.1. General principles
The purpose of the methodology is to establish a correspondence between the logical (external) address and the geometrical location of each cell. We first assumed that: (1) One part of the address bits is devoted to the rows (word lines), the other one to the columns (data bit lines). (2) The correspondence between the logical address and the geometrical location is built by successive dichotomies (see Fig. 2), that is to say: (a) For each group (columns, or rows) one bit Ai divides the whole group (columns or rows) into two related sets, the first one with Ai = 0, the second one with Ai = 1. (b) These two sets are either symmetrical in relation to their common boundary, or shifted. (c) In each set, another bit Aj plays the same role. (d) And so on, until there is no bit left (row, or column). The first assumption is always verified. On the numerous examples we dealt with, the second one was true, excepted sometimes on a few rows or columns, easy to distinguish. Thus the mapping of a SRAM with the E-beam tester will be done in three steps: (1) Discrimination between row and column bits and estimation of geometrical weight of each bit (see Fig. 3). During this first step, it is also possible to locate the data bits, but only in their whole (not bit per bit). (2) Determination of the distribution of blocks among data bits. (3) Determination of the isometries associated with each address bit (shift or symmetry).
f
I
A,=0 A
Ai=1 A
I
A.=1 1 A.=0 ' ~11_,'~~A-,l~~~-,'~-~-,
A.=0
'
Aj=l
\
symmetry t
&_a shift
Fig. 2. Hypothesis
concerning
the regularity
of the addresses.
F. Marc et al. I Microelectronic
40
Engineering 2.5 (lYY4) _X-4X
Address A=0 A=lA=2
-
A=4
-
A=8
-
A=16- . .
-
. A=512 A=lO; -
Fig. 3. Determination of the column distance between the track of address switched to 1. If one track appears contrasted track is an estimate of its probably a row bit. In this example, according to their geometrical weight
3.2.
I
bits and evaluation of their geometrical weight (defined for a bit A, as the 2k and the track of address 0) with VC. For each successive state one bit is contrasted, the corresponding bit is a column bit, and the position of the geometrical weight. If no track appears contrasted, the corresponding bit is the bits A,,, A,, A ~, A, and A, are column bits, and the new arrangement is A?, A,, A,,, A,, A ,,.
Preliminary operations
Before every E-beam observation, it is of course necessary to open the package either by chemical etching (for plastic packages) or by a mechanical process (for ceramic ones). If the passivation layer thickness does not exceed a few micrometers, this layer has not to be removed. Otherwise, it must be partially removed, either by chemical or by plasma etching, in level (1 pm or less) while preserving the original order to reduce the thickness at a “proper” functionality of the device. The optical observation which follows must be used to prepare the electron beam observation: - the arrangement different blocks of the memory of the main structures (decoders, matrix. . .) ; - the arrangement of the number of column strips or row strips; as well as - the orientation of the buried lines of the cell matrix are determined at this step. Some areas where their voltage can be easily observed by voltage contrast (areas where buried lines are not under other lines) can also be shown. The memory is assumed to have N address bits and D data bits.
F. Marc et al. I Microelectronic
3.3. 3.3.1.
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25 (1994) 35-48
41
Estimate of the geometrical weight of each address bit Overall study: voltage coding
Thanks to the matrix arrangement of the memory cells, two axes are privileged: rows are parallel to the scanning axis, whereas columns are perpendicular to it’. So, VC permits to point out the columns by synchronizing the beam scanning with the frame synchronization of the video signal, and the rows by synchronizing the beam scanning with the line synchronization of the video signal. 3.3.1.1. Column bits. In order to estimate the geometrical weight of the columns bits (Fig. 4), the beam scanning is synchronized with the frame scanning of the video signal. So, a single image allows to distinguish between the row bits and the column bits, and to estimate the geometrical weight of the column bits. In order to do that, the following pattern is applied to the device under test (DUT): - The device is enabled: E control bit is reset to 0. - The device is in write mode: R/q control bit is reset to 0. - The data word is constant, either equal to 0 or to 2O - 1. - The address word is successively: 0, 1,2,4, . . . , 2N-‘. The duration of each state is chosen to have the whole sequence on one image and is synchronized with the frame scanning*.
Fig. 4. Estimate of the geometrical weight of the row bits using VC on a 64k SRAM. (a) the address word is successively 0,2’, 2l, 2*, 23, . , 215. A, to A, are row bits; first estimate of the geometrical weight of A 8 to A 15. (b) Partial sequence involving the bits A, to A II rearranged according to their geometrical weight: the bit equal to 1 is successively A R, A 12, A 14, A 15, A 13, A 11, A 9, A 1o. The different tracks are contrasted according to a geometric progression (factor 2). The track related to A,, does not appear because it is out of the image. 1 For the clarity of the demonstration, we assume that the device under test is placed in the chamber of the SEM such that columns are vertical and rows horizontal, which is not always the case. Yet, the principles and the methodology remain the same. ‘In fact, when the density of the memory is too high, it may be necessary to use two or more images to get the information. In that case the address word is first switched from 0 to 2” (a
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Case D = 1. The successive states appear on the video monitor as horizontal strips. For certain values of the address, one track appears contrasted (white): it is the track associated with this address. The states which do not contrast any track are a priori associated to line bits (Fig. 4a). The distance between the track of address 0 (first strip) and the track of address 2k (all bits equal to zero, excepted Ak) is an estimate of the geometrical weight of A k. It is consequently possible to rearrange the column bits according to their geometrical weight. A new pattern is applied to the DUT: the address is now 0, 1, 2,4, . . . ,2’, according to the geometrical weight. From now on, this will be named “geometrical address”. The VC image allows the different tracks to appear contrasted, according to a geometric progression (Fig. 4b). Case D > 1. In this case, the process is the same as previously described. However, on the VC image, for every value of the address, D tracks appear contrasted instead of one. The estimate of the geometrical weight is made in the same way, considering the assumption 2b of Section 3.1. 3.3.1.2. Row bits. The principle used to estimate the geometrical weight of the row bits is the same as described above. However, the beam scanning is synchronized with the line scanning of the video signal. As row bits have been determined from an elimination assumption during the previous operation, the address word is now 0, 1, 2AJ, 2Al, . . . , 2Ah, where A ;, A,, . . , A k are the assumed row bits. The remaining pattern is the one previously described. On the video monitor, the successive states appear as vertical strips. Processing and conclusions are similar as in Section 3.3.1.1. 3.3.2. Phase-selective voltage contrast: a bit-per-bit method If it is difficult to distinguish between the electrical signal and the topography, which is often true on buried conductors, then PSVC permits the analyst to obtain a better display. However, PSVC provides information concerning only two logical states on a single image. To estimate the geometrical weights, it is thus necessary to build a view for every address bit. For each Ai the following pattern is applied: - The device is enabled: E control bit is reset to 0. - The device is in write mode: R/E control bit is reset to 0. - The data word is constant, either equal to 0 or to 2” - 1. - The address word is alternately 0 and 2’, and signal on the bit Ai is used as reference signal for PSVC. On the video monitor, two tracks appear, one bright, one dark (see Fig. 5). As described in the overall study, the distance between the two tracks is an estimate of the geometrical weight of the bit A i. Two successive images have one track in common, the one of address 0.
.3.3.3. At - The one
Results the end of this first sequence, the following results are obtained: address bits are divided into two groups, the first one concerning the columns.
the rows, the second
F. Marc et al. I Microelectronic
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25 (1994) 35-48
Fig. 5. Estimation of the geometrical weight of the row bits using PSVC on the same 64k SRAM. the geometrical weight of the bit A, is pointed out.
43
On this image,
-
In each group, the bits can be rearranged according to their geometrical weight, and so the geometrical address is defined. - Data columns have been pointed out, without anticipating their arrangement. 3.4. Determination of blocks distribution among data bits The D parts of the cell matrix associated with the D data bits are always composed of entire columns. Thus one has to determine how the memory cells are distributed among the data bits. As mentioned before, on VC images used to estimate the weight of the column address bits, D columns appear contrasted (either all dark or all bright depending on the level of the selection) for each state; similarly, D columns appear dark and D columns appear bright on a PSVC image (one for each of the two addresses). These columns are easy to distinguish because of the small number of data bits (see Fig. 6). To determine to which data bit a particular block is associated (which is impossible on the previous images), one can use the following method: the address word is constant, and the data word is alternately 0 and 2k. On a PSVC image using the bit k as a reference, two neighbouring columns appear contrasted, one dark and one bright, corresponding to the writing of a 1 and a 0 in the cells of the column involved. Repeating this observation with every data bit, the entire distribution can be known. 3.5.
Determination
of isometries associated with each address bit
To determine the isometries associated with each address bit, it is possible to choose one of the three following methods, according to (1) the quality of the contrast: VC possible or not; (2) the urgency of the analysis and the degree of confidence needed. The first two methods use VC; the third one uses PSVC.
44
F. Marc et al. I Microelectronic
Fig. 6. PSVC image on a 1 Mbit SRAM. of the two addresses 0 and 2’.
3.5.1.
Engineering
Eight pairs of columns
2-5 (1994) 35-48
are contrasted,
corresponding
to the eight data bits
Methods using VC
Exhaustive method. Although it is exhaustive, this method only needs an acceptable number of images: a maximum of 32 for a 512-lines memory. For the first image, the following pattern is applied: R/F= 0; E = 0 (validation of the circuit in the write mode); data word constant (for instance equal to 0); the geometrical to determine the addresses are successively 0, 1,2,3,4, . . . , 15”. The first image permits isometries associated to bits 0 to 3, as described on Fig. 7. The pattern for the second image is the same except for the geometrical addresses: of this second image with the first one provides the 16,17,18, . . . ,31. The comparison isometries associated with bit 4. For the third and fourth images. The same pattern is applied except for the addresses. The isometries associated with bit 5 are determined by comparison of these two images with the first two ones. This procedure is repeated until there is no address left. Rapid method. If the assumptions 2 and especially 2b are verified (the correspondence between the logical address and the geometrical location is built by successive dichotomies; for each group (columns, or rows) one bit Ai divides the whole group (columns, or rows) into two related sets which are either symmetrical in relation to their common boundary or shifted; in each set, another bit Aj plays the same role; and so on, until there is no bit left (row, or column)), the information provided by the previous images is redundant: every image is either shifted or symmetrical relative to each other. ‘If necessary, the address can go up to 31. But the readability of the image is then reduced. In this case, the isometry associated with bit 4 is also shown, and the number of images necessary to scan the whole memory is divided by a factor two.
F. Marc et al. I Microelectronic
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Fig. 7. Determination of isometries using VC for column bits. The geometrical address C of the written column is successively 0, 1,2,3, . . . , 15. The first four lines permit to determine the isometry associated with bit C,. In this case, it is a symmetry as shown by the white arrows. Comparison between lines 4 to 7 and lines 0 to 3 shows that C, is associated with a shift. In the same way, comparison between lines 8 to 1.5 and lines 0 to 7 shows that C, is associated with a shift.
So, supposing that 2 is true, the first image is the same as previously, but the second image will be built with the following addresses: 0 (kept as a reference), f&16,24,32, . . . , 15 x 8 = 120. In that case, the comparison of this second image with the first one provides the isometries associated with bits 4 to 6. The third image is built in order to provide the isometries associated with bits 7 to 9; the following addresses are thus applied: 0, 64, 2 X 64, 3 x 64, . . . , 15 x 64. In this case, the number of needed images is drastically reduced (3 instead of 32 for a 512-line memory). But possible irregularities cannot be pointed out. 3.5.2. Method using PSVC As PSVC provides information concerning only two logical states on a single image, it is difficult to use an exhaustive method since for a 512-lines memory this method would need 256 images! Moreover locating every image should be done with a high precision to enable the comparison between these images. However an adaptation of the rapid method using VC is relatively easy. In that case, for a 512~line memory this method requires only 16 images. The pattern to apply is the following: For the first image: R/W = 0; E = 0 (validation of the circuit in the write mode); data word constant (for instance equal to 0); the geometrical addresses are successively: 0,l. The pattern for the second image is the same except for the geometrical addresses: 2,3. Magnification and location must be maintained constant, in order to make possible the comparison between the two images. As previously, the comparison permits to determine the isometry associated with bit 1 (see Fig. 8). For the third and fourth images, the pattern is the same except for the geometrical addresses, which are 0,2 and 4,6, respectively. The comparison between these two images provides the isometry associated with bit 2.
F. Murc et al. I Microelectronic Engineering 2.~ (1994) 35-48
36
Fig. 8. Determination of isometries using PSVC for row bits. The written rows L2 and L, are switched between 00 and 01 (a) and between 10 and 11 (b). The dotted lines represent the image obtained with L2 and L, switched between 10 and 11. The comparison between these two images shows that L, is associated with a shift.
This procedure is repeated until the (2n + 1)th image, same pattern, geometrical addresses: 0,2”, and the 2(n + 1)th image, same pattern, geometrical addresses: 2 x 2”, 3 x 2”. Comparison between these two images provides the isometry associated with the bit (n + 1).
4. Conclusion The methodology for fast descrambling of VLSI SRAMs, passivated or not, described above is based on some regularity assumptions concerning the architecture of the line and row decoders. Although some memories do not agree with these assumptions, the irregularities we discovered are essentially related to the rules 2(a) and 2(b), namely: Rule 2a. For each group (columns or rows) one bit A, divides the whole group into two related sets, the first one for A, = 0, the second one for A, = 1. For one or several bits we have sometimes noted that the two subsets were not connected. In the correspondence table this irregularity alters the position of the rows by some places inside a block of 2” rows. Rule 2b. These two sets are either symmetrical in relation to their common boundary or shifted. Some irregularities have been observed where this symmetry rule was not respected; for example if we represent the values of the bits A,, A,, A i, in the memory cells they allow to reach, we observe the following configuration:
A, A, A
h-
00001111 0 0 1
1
1
1
0
0
1
1
0
1
0
1
0
0
F. Marc et al. I Microelectronic
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47
where the bit Ai divides the eight bits into two groups, and Aj and A, are not associated with the same isometry: Aj symmetry; A, shift. Only the exhaustive method allows a reliable detection of an irregularity of one of the two types described above. Nevertheless the non-exhaustive method leads to a great probability of detection of an irregularity if the number of successive geometrical addresses on an image is equal to or greater than eight. This methodology was designed to allow an analyst unexperienced with E-beam testing to perform the mapping of every SRAM within a few hours. It was successfully applied on 64 Kbit to 1 Mbit passivated CMOS SRAMs. In the case of the 1 Mbit memory (Fig. 9), the complete descrambling was performed in 4 hours. So, this allows to consider descrambling as a systematic preliminary step in SRAM failure analysis. The set-up of the correspondence table between logical addresses and physical locations can give different kinds of information: - In design verification it provides information on the logical function of some parts of the device. - For the external testing it allows to optimize the test patterns taking into account the physical architecture of the device and not only its logical architecture (e.g. influence of cells on their neighbours). - In failure analysis it provides the geometrical location of a faulty function detected during an external testing. It is one of the possible solutions to relate the component structuralfunctional description and geometrical description in a fault location process when CAD is not available [8].
AO=O
AO=l
I I I
\\
\
\ \
’ 2 ’ 1 ’ 0’
AlO-11-9-8-13-15-16-14-12
(rows> Fig. 9. Complete
mapping
of a 1 Mbit CMOS SRAM
(128k X 8) showing
row, column
and data word arrangement.
48
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References [l] E. Menzel, Electron beam techniques, Microelectron. Eng. 16 (1992) 3-14. [2] E. Wolfgang, Electron beam testing, Microelectron. Eng. 4 (1986) 77-106. [3] J.P. Collin and T. Viacroze, E-beam testing: Image and signal processing for the failure analysis of VLSI components, ZSTFA (1985) 89-97. [4] M. Vanzi, VLSI failure analysis by automated DDVC, Microelectron. Eng. 16 (1992) 139-156. [5] T.C. May, G.L. Scott, E.S. Meieran, P. Winer and V.R. Rao, Dynamic fault imaging of VLSI random logic devices, IEEE Znt. Rel. Phys. Symp. (1984) 95-108. [6] P. Perdu, C. Dupe and M. Dupire, Decoding CMOS static random access memories through static voltage contrast, ESREF (1991) 807-814. [7] J.P. Pierrel, D. May and L. Primot, Efficient tool for failure analysis using E-beam testing: Waveform comparison module, ESREF (1991) 791-798. [8] M. Barre, Fault localization methodology, ESREF (1992) 245-263.
Microelectronic
Engineering
25 (1994) 35-48
Quick and exhaustive descrambling methodology for highdensity static random access memories using voltage contrast F. Marc, Laboratoire ML,
H. Fremont,
P. Jounet,
Y. Danto
Universitt de Bordeaux I, 351 tours de la Libtration,
F-33405
Talence cedex, France
Abstract The external test previous to any failure analysis of a static RAM provides the logical address of each failure. We developed a methodology allowing a fast mapping of SRAMs, passivated or not, by voltage contrast in a scanning It uses voltage coding and the phase-selective voltage electron microscope, with minimum initial information. contrast. The first observations permit to distinguish the row bits from the column bits, and to sort the address bits according to the order of geometrical binary weight. The second part of the mapping consists in determining the symmetries associated with each address bit. Voltage coding observation needs only a few images. The second method requires at least as many images as address bits, but can be efficiently used with buried lines. This methodology was designed to be efficient whatever the matrix map may be. It was applied successfully on 64 kbit to 1 Mbit passivated CMOS SRAMs. Keywords:
Voltage
contrast,
SRAM;
Descrambling;
Descrambling
methodology
1. Introduction The increasing complexity in VLSI circuits leads to a need for new external and internal testing techniques. Electron beam tester (EBT) appears as an attractive tool for failure analysis, and many techniques associated with the potential contrast phenomenon have been developed [l-3]. Faced with a real case failure analysis, the analyst has to choose more adapted techniques to be sure to localize the failure as rapidly as possible. After an external testing, the analyst should be able to define a small number of possible faulty functions. The aim of the following internal test is to geometrically localize them. Some comparison methods have been described [4,5] but these methods need either a “golden” device or information about the layout of the circuit. In the situation where these elements are not available, we propose a location methodology taking only into account the function of the circuit. In a static random access memory (SRAM), the functions considered to be faulty after an external test can often be associated with a group of logical addresses. Therefore the location of the failure can be done through the map of the memory cells matrix. The matrix structure 0167-9317/94/$07.00 0 1994 Elsevier SSDI 0167-9317(94)00004-E
Science
B.V. All rights reserved
36
F. Marc et al. I Microelectronic
Engineering
25 (1994) X-48
of SRAMs leads to a good discrimination between the location of the decoding function on the one hand and of the memorizing function in the memory cells on the other hand. Observation by means of an optical microscope allows to count the number of row lines and column lines for example by following tracks from the connection pad corresponding to data pins of the the device. Thanks to assumptions described later concerning the regularity of the correspondence between logical addresses (at the level of the pins of the device) and physical addresses
Frangois Marc was born in 1966 in France. He received the Electronics Engineer Diploma from ENSERB in 1989. He is currently working for his Ph.D. on failure analysis through electron beam testing, in the failure analysis and reliability group in the IXL Laboratory (University of Bordeaux, France).
HCICne Frbmont was born in 1963 in France. She received the Electronics Engineer Diploma from ENSERB in 1986. From 1986 to 1988 she worked in the Texas Instrument France failure analysis laboratory and received the Ph.D. at the University of Bordeaux in 1988. After a Post-Dot at the University of Hannover (Germany), she joined the failure analysis and reliability group in IXL, Laboratory of Microelectronics (University of Bordeaux. France) in 1989: her basic research topic is Electron Beam Testing.
Paul Jounet was born in 1947. He received the Ph.D. from the department of Electronics. at the University Pierre and Marie Curie, Paris (France) in 1978. Since 1988, he joined the failure analysis and reliability group in IXL, Laboratory of Microelectronics (University of Bordeaux, France). His research topics include technological and comportemental analysis.
Yves Danto was born in 1942 in France. After his studies at the university where he obtained his Ph.D. and his “Doctorat d’etat”, he joined the University of Bordeaux (France), where he has been Professor since 1982. He is in charge of the failure analysis and reliability group in IXL, Laboratory of Microelectronics.
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37
(corresponding to the effective location of the memory cells in the chip), the mapping process consists in the following steps: - determination of the address bits associated either with the row lines or with the column lines; - inside these two groups, classification of the address bits according to the areas they allow to reach. We define a geometrical weight of an address bit as the mean distance between lines or columns corresponding to two addresses whose bits are all identical to zero except for the one we want to evaluate; - when the data bus consists of several bits, determination of the matrix areas (blocks) associated with each of these bits; - finally, determination of the isometry (symmetry or shift) associated with the state changing of each address bit. Among the many observation techniques available in scanning electron microscopy, we have essentially retained two imaging techniques: voltage coding and phase-selective voltage contrast. According to its features, each technique is used depending on the quality of the image and the amount of observations investigated. Fig. 1 shows the different steps of the developed methodology as well as the imaging techniques used. After a justification of the choice of the two imaging techniques, this paper sets out a fast VLSI SRAM descrambling methodology using voltage contrast on a scanning electron microscope (SEM). Practical case studies, on a large range of passivated SRAMs from different manufacturers, prove the efficiency of the method.
2. Choice of the observation
techniques - Application
to SRAMs
The aim of the presented methodology is to descramble static RAMS with an electron beam tester using only image mode. To choose the observation techniques, we have taken advantage of the structural properties of SRAMs, that is to say: - matrix organisation of the memory cells, with two perpendicular axes of parallel trips; - primarily combinational functionality as soon as the device is fixed either in read or in write mode (the R/W control bit is constant). The possible presence of a passivation layer was also taken into account. We chose imaging rather than measurement techniques because they are easier to implement and they give much more general information. The layout of the circuit before any observation was unknown. The combinational functionality of the memories permitted to first leave aside some techniques devoted to temporal behaviour, such as frequency mapping or tracing. For the same reasons, stroboscopic methods have not been used, especially because they are difficult to use on passivated devices without multisampling systems, due to charging effects. Voltage coding (VC) is sensitive to charging effects similarly to the stroboscopic method: the beam reaches each point of the circuit at a constant level of the signal. However, as the beam is continuously scanned over the device, the signal can be observed near its transitions in a satisfactory way. Moreover, information given by a VC image is very rich, and well adapted to the matrix structure of the memories.
F. Marc et al. I Microelectronic
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2-5 (1994) 35-48
columns & rows
if several data bits columns _________________________ 1 determination I of blocks j distribution i among data i bits ~--_-_-___________________ _________I columns
voltage co&ast
& rows
determination of isometries
quality ? bad
goodf
choice of the analyst : reliability or urgence ? + exhaustive m
ep Fig. 1. Principle
+ g&&C e
\ “auick” a
of the memory 1 of the methodology.
Contrary to the previous methods, the phase-selective voltage contrast (PSVC) method [3] is not sensitive to charging effects, because no synchronism exists between the applied signal and the beam scanning. PSVC can be used because SRAMs can be considered as combinatorial circuits. (It may be somewhat complicated on sequential circuits because it involves patterns of two vectors.) It has been considered as an alternative to VC when the latter has reached its limits: if VC images provide more than 30 logical states of the memory on a single image, it may be difficult to distinguish between the electrical signal and the topography. PSVC permits to obtain a better display. This is especially true for buried conductors. Unfortunately, PSVC provides information concerning only two logical states on a single image.
F. Marc et al. I Microelectronic Engineering
3. The methodology
for descramhling
25 (1994) 35-48
39
SRAMs
3.1. General principles
The purpose of the methodology is to establish a correspondence between the logical (external) address and the geometrical location of each cell. We first assumed that: (1) One part of the address bits is devoted to the rows (word lines), the other one to the columns (data bit lines). (2) The correspondence between the logical address and the geometrical location is built by successive dichotomies (see Fig. 2), that is to say: (a) For each group (columns, or rows) one bit Ai divides the whole group (columns or rows) into two related sets, the first one with Ai = 0, the second one with Ai = 1. (b) These two sets are either symmetrical in relation to their common boundary, or shifted. (c) In each set, another bit Aj plays the same role. (d) And so on, until there is no bit left (row, or column). The first assumption is always verified. On the numerous examples we dealt with, the second one was true, excepted sometimes on a few rows or columns, easy to distinguish. Thus the mapping of a SRAM with the E-beam tester will be done in three steps: (1) Discrimination between row and column bits and estimation of geometrical weight of each bit (see Fig. 3). During this first step, it is also possible to locate the data bits, but only in their whole (not bit per bit). (2) Determination of the distribution of blocks among data bits. (3) Determination of the isometries associated with each address bit (shift or symmetry).
f
I
A,=0 A
Ai=1 A
I
A.=1 1 A.=0 ' ~11_,'~~A-,l~~~-,'~-~-,
A.=0
'
Aj=l
\
symmetry t
&_a shift
Fig. 2. Hypothesis
concerning
the regularity
of the addresses.
F. Marc et al. I Microelectronic
40
Engineering 2.5 (lYY4) _X-4X
Address A=0 A=lA=2
-
A=4
-
A=8
-
A=16- . .
-
. A=512 A=lO; -
Fig. 3. Determination of the column distance between the track of address switched to 1. If one track appears contrasted track is an estimate of its probably a row bit. In this example, according to their geometrical weight
3.2.
I
bits and evaluation of their geometrical weight (defined for a bit A, as the 2k and the track of address 0) with VC. For each successive state one bit is contrasted, the corresponding bit is a column bit, and the position of the geometrical weight. If no track appears contrasted, the corresponding bit is the bits A,,, A,, A ~, A, and A, are column bits, and the new arrangement is A?, A,, A,,, A,, A ,,.
Preliminary operations
Before every E-beam observation, it is of course necessary to open the package either by chemical etching (for plastic packages) or by a mechanical process (for ceramic ones). If the passivation layer thickness does not exceed a few micrometers, this layer has not to be removed. Otherwise, it must be partially removed, either by chemical or by plasma etching, in level (1 pm or less) while preserving the original order to reduce the thickness at a “proper” functionality of the device. The optical observation which follows must be used to prepare the electron beam observation: - the arrangement different blocks of the memory of the main structures (decoders, matrix. . .) ; - the arrangement of the number of column strips or row strips; as well as - the orientation of the buried lines of the cell matrix are determined at this step. Some areas where their voltage can be easily observed by voltage contrast (areas where buried lines are not under other lines) can also be shown. The memory is assumed to have N address bits and D data bits.
F. Marc et al. I Microelectronic
3.3. 3.3.1.
Engineering
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41
Estimate of the geometrical weight of each address bit Overall study: voltage coding
Thanks to the matrix arrangement of the memory cells, two axes are privileged: rows are parallel to the scanning axis, whereas columns are perpendicular to it’. So, VC permits to point out the columns by synchronizing the beam scanning with the frame synchronization of the video signal, and the rows by synchronizing the beam scanning with the line synchronization of the video signal. 3.3.1.1. Column bits. In order to estimate the geometrical weight of the columns bits (Fig. 4), the beam scanning is synchronized with the frame scanning of the video signal. So, a single image allows to distinguish between the row bits and the column bits, and to estimate the geometrical weight of the column bits. In order to do that, the following pattern is applied to the device under test (DUT): - The device is enabled: E control bit is reset to 0. - The device is in write mode: R/q control bit is reset to 0. - The data word is constant, either equal to 0 or to 2O - 1. - The address word is successively: 0, 1,2,4, . . . , 2N-‘. The duration of each state is chosen to have the whole sequence on one image and is synchronized with the frame scanning*.
Fig. 4. Estimate of the geometrical weight of the row bits using VC on a 64k SRAM. (a) the address word is successively 0,2’, 2l, 2*, 23, . , 215. A, to A, are row bits; first estimate of the geometrical weight of A 8 to A 15. (b) Partial sequence involving the bits A, to A II rearranged according to their geometrical weight: the bit equal to 1 is successively A R, A 12, A 14, A 15, A 13, A 11, A 9, A 1o. The different tracks are contrasted according to a geometric progression (factor 2). The track related to A,, does not appear because it is out of the image. 1 For the clarity of the demonstration, we assume that the device under test is placed in the chamber of the SEM such that columns are vertical and rows horizontal, which is not always the case. Yet, the principles and the methodology remain the same. ‘In fact, when the density of the memory is too high, it may be necessary to use two or more images to get the information. In that case the address word is first switched from 0 to 2” (a
42
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et al.
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Case D = 1. The successive states appear on the video monitor as horizontal strips. For certain values of the address, one track appears contrasted (white): it is the track associated with this address. The states which do not contrast any track are a priori associated to line bits (Fig. 4a). The distance between the track of address 0 (first strip) and the track of address 2k (all bits equal to zero, excepted Ak) is an estimate of the geometrical weight of A k. It is consequently possible to rearrange the column bits according to their geometrical weight. A new pattern is applied to the DUT: the address is now 0, 1, 2,4, . . . ,2’, according to the geometrical weight. From now on, this will be named “geometrical address”. The VC image allows the different tracks to appear contrasted, according to a geometric progression (Fig. 4b). Case D > 1. In this case, the process is the same as previously described. However, on the VC image, for every value of the address, D tracks appear contrasted instead of one. The estimate of the geometrical weight is made in the same way, considering the assumption 2b of Section 3.1. 3.3.1.2. Row bits. The principle used to estimate the geometrical weight of the row bits is the same as described above. However, the beam scanning is synchronized with the line scanning of the video signal. As row bits have been determined from an elimination assumption during the previous operation, the address word is now 0, 1, 2AJ, 2Al, . . . , 2Ah, where A ;, A,, . . , A k are the assumed row bits. The remaining pattern is the one previously described. On the video monitor, the successive states appear as vertical strips. Processing and conclusions are similar as in Section 3.3.1.1. 3.3.2. Phase-selective voltage contrast: a bit-per-bit method If it is difficult to distinguish between the electrical signal and the topography, which is often true on buried conductors, then PSVC permits the analyst to obtain a better display. However, PSVC provides information concerning only two logical states on a single image. To estimate the geometrical weights, it is thus necessary to build a view for every address bit. For each Ai the following pattern is applied: - The device is enabled: E control bit is reset to 0. - The device is in write mode: R/E control bit is reset to 0. - The data word is constant, either equal to 0 or to 2” - 1. - The address word is alternately 0 and 2’, and signal on the bit Ai is used as reference signal for PSVC. On the video monitor, two tracks appear, one bright, one dark (see Fig. 5). As described in the overall study, the distance between the two tracks is an estimate of the geometrical weight of the bit A i. Two successive images have one track in common, the one of address 0.
.3.3.3. At - The one
Results the end of this first sequence, the following results are obtained: address bits are divided into two groups, the first one concerning the columns.
the rows, the second
F. Marc et al. I Microelectronic
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25 (1994) 35-48
Fig. 5. Estimation of the geometrical weight of the row bits using PSVC on the same 64k SRAM. the geometrical weight of the bit A, is pointed out.
43
On this image,
-
In each group, the bits can be rearranged according to their geometrical weight, and so the geometrical address is defined. - Data columns have been pointed out, without anticipating their arrangement. 3.4. Determination of blocks distribution among data bits The D parts of the cell matrix associated with the D data bits are always composed of entire columns. Thus one has to determine how the memory cells are distributed among the data bits. As mentioned before, on VC images used to estimate the weight of the column address bits, D columns appear contrasted (either all dark or all bright depending on the level of the selection) for each state; similarly, D columns appear dark and D columns appear bright on a PSVC image (one for each of the two addresses). These columns are easy to distinguish because of the small number of data bits (see Fig. 6). To determine to which data bit a particular block is associated (which is impossible on the previous images), one can use the following method: the address word is constant, and the data word is alternately 0 and 2k. On a PSVC image using the bit k as a reference, two neighbouring columns appear contrasted, one dark and one bright, corresponding to the writing of a 1 and a 0 in the cells of the column involved. Repeating this observation with every data bit, the entire distribution can be known. 3.5.
Determination
of isometries associated with each address bit
To determine the isometries associated with each address bit, it is possible to choose one of the three following methods, according to (1) the quality of the contrast: VC possible or not; (2) the urgency of the analysis and the degree of confidence needed. The first two methods use VC; the third one uses PSVC.
44
F. Marc et al. I Microelectronic
Fig. 6. PSVC image on a 1 Mbit SRAM. of the two addresses 0 and 2’.
3.5.1.
Engineering
Eight pairs of columns
2-5 (1994) 35-48
are contrasted,
corresponding
to the eight data bits
Methods using VC
Exhaustive method. Although it is exhaustive, this method only needs an acceptable number of images: a maximum of 32 for a 512-lines memory. For the first image, the following pattern is applied: R/F= 0; E = 0 (validation of the circuit in the write mode); data word constant (for instance equal to 0); the geometrical to determine the addresses are successively 0, 1,2,3,4, . . . , 15”. The first image permits isometries associated to bits 0 to 3, as described on Fig. 7. The pattern for the second image is the same except for the geometrical addresses: of this second image with the first one provides the 16,17,18, . . . ,31. The comparison isometries associated with bit 4. For the third and fourth images. The same pattern is applied except for the addresses. The isometries associated with bit 5 are determined by comparison of these two images with the first two ones. This procedure is repeated until there is no address left. Rapid method. If the assumptions 2 and especially 2b are verified (the correspondence between the logical address and the geometrical location is built by successive dichotomies; for each group (columns, or rows) one bit Ai divides the whole group (columns, or rows) into two related sets which are either symmetrical in relation to their common boundary or shifted; in each set, another bit Aj plays the same role; and so on, until there is no bit left (row, or column)), the information provided by the previous images is redundant: every image is either shifted or symmetrical relative to each other. ‘If necessary, the address can go up to 31. But the readability of the image is then reduced. In this case, the isometry associated with bit 4 is also shown, and the number of images necessary to scan the whole memory is divided by a factor two.
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45
Fig. 7. Determination of isometries using VC for column bits. The geometrical address C of the written column is successively 0, 1,2,3, . . . , 15. The first four lines permit to determine the isometry associated with bit C,. In this case, it is a symmetry as shown by the white arrows. Comparison between lines 4 to 7 and lines 0 to 3 shows that C, is associated with a shift. In the same way, comparison between lines 8 to 1.5 and lines 0 to 7 shows that C, is associated with a shift.
So, supposing that 2 is true, the first image is the same as previously, but the second image will be built with the following addresses: 0 (kept as a reference), f&16,24,32, . . . , 15 x 8 = 120. In that case, the comparison of this second image with the first one provides the isometries associated with bits 4 to 6. The third image is built in order to provide the isometries associated with bits 7 to 9; the following addresses are thus applied: 0, 64, 2 X 64, 3 x 64, . . . , 15 x 64. In this case, the number of needed images is drastically reduced (3 instead of 32 for a 512-line memory). But possible irregularities cannot be pointed out. 3.5.2. Method using PSVC As PSVC provides information concerning only two logical states on a single image, it is difficult to use an exhaustive method since for a 512-lines memory this method would need 256 images! Moreover locating every image should be done with a high precision to enable the comparison between these images. However an adaptation of the rapid method using VC is relatively easy. In that case, for a 512~line memory this method requires only 16 images. The pattern to apply is the following: For the first image: R/W = 0; E = 0 (validation of the circuit in the write mode); data word constant (for instance equal to 0); the geometrical addresses are successively: 0,l. The pattern for the second image is the same except for the geometrical addresses: 2,3. Magnification and location must be maintained constant, in order to make possible the comparison between the two images. As previously, the comparison permits to determine the isometry associated with bit 1 (see Fig. 8). For the third and fourth images, the pattern is the same except for the geometrical addresses, which are 0,2 and 4,6, respectively. The comparison between these two images provides the isometry associated with bit 2.
F. Murc et al. I Microelectronic Engineering 2.~ (1994) 35-48
36
Fig. 8. Determination of isometries using PSVC for row bits. The written rows L2 and L, are switched between 00 and 01 (a) and between 10 and 11 (b). The dotted lines represent the image obtained with L2 and L, switched between 10 and 11. The comparison between these two images shows that L, is associated with a shift.
This procedure is repeated until the (2n + 1)th image, same pattern, geometrical addresses: 0,2”, and the 2(n + 1)th image, same pattern, geometrical addresses: 2 x 2”, 3 x 2”. Comparison between these two images provides the isometry associated with the bit (n + 1).
4. Conclusion The methodology for fast descrambling of VLSI SRAMs, passivated or not, described above is based on some regularity assumptions concerning the architecture of the line and row decoders. Although some memories do not agree with these assumptions, the irregularities we discovered are essentially related to the rules 2(a) and 2(b), namely: Rule 2a. For each group (columns or rows) one bit A, divides the whole group into two related sets, the first one for A, = 0, the second one for A, = 1. For one or several bits we have sometimes noted that the two subsets were not connected. In the correspondence table this irregularity alters the position of the rows by some places inside a block of 2” rows. Rule 2b. These two sets are either symmetrical in relation to their common boundary or shifted. Some irregularities have been observed where this symmetry rule was not respected; for example if we represent the values of the bits A,, A,, A i, in the memory cells they allow to reach, we observe the following configuration:
A, A, A
h-
00001111 0 0 1
1
1
1
0
0
1
1
0
1
0
1
0
0
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47
where the bit Ai divides the eight bits into two groups, and Aj and A, are not associated with the same isometry: Aj symmetry; A, shift. Only the exhaustive method allows a reliable detection of an irregularity of one of the two types described above. Nevertheless the non-exhaustive method leads to a great probability of detection of an irregularity if the number of successive geometrical addresses on an image is equal to or greater than eight. This methodology was designed to allow an analyst unexperienced with E-beam testing to perform the mapping of every SRAM within a few hours. It was successfully applied on 64 Kbit to 1 Mbit passivated CMOS SRAMs. In the case of the 1 Mbit memory (Fig. 9), the complete descrambling was performed in 4 hours. So, this allows to consider descrambling as a systematic preliminary step in SRAM failure analysis. The set-up of the correspondence table between logical addresses and physical locations can give different kinds of information: - In design verification it provides information on the logical function of some parts of the device. - For the external testing it allows to optimize the test patterns taking into account the physical architecture of the device and not only its logical architecture (e.g. influence of cells on their neighbours). - In failure analysis it provides the geometrical location of a faulty function detected during an external testing. It is one of the possible solutions to relate the component structuralfunctional description and geometrical description in a fault location process when CAD is not available [8].
AO=O
AO=l
I I I
\\
\
\ \
’ 2 ’ 1 ’ 0’
AlO-11-9-8-13-15-16-14-12
(rows> Fig. 9. Complete
mapping
of a 1 Mbit CMOS SRAM
(128k X 8) showing
row, column
and data word arrangement.
48
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References [l] E. Menzel, Electron beam techniques, Microelectron. Eng. 16 (1992) 3-14. [2] E. Wolfgang, Electron beam testing, Microelectron. Eng. 4 (1986) 77-106. [3] J.P. Collin and T. Viacroze, E-beam testing: Image and signal processing for the failure analysis of VLSI components, ZSTFA (1985) 89-97. [4] M. Vanzi, VLSI failure analysis by automated DDVC, Microelectron. Eng. 16 (1992) 139-156. [5] T.C. May, G.L. Scott, E.S. Meieran, P. Winer and V.R. Rao, Dynamic fault imaging of VLSI random logic devices, IEEE Znt. Rel. Phys. Symp. (1984) 95-108. [6] P. Perdu, C. Dupe and M. Dupire, Decoding CMOS static random access memories through static voltage contrast, ESREF (1991) 807-814. [7] J.P. Pierrel, D. May and L. Primot, Efficient tool for failure analysis using E-beam testing: Waveform comparison module, ESREF (1991) 791-798. [8] M. Barre, Fault localization methodology, ESREF (1992) 245-263.