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Yield enhancement techniques for 3-dimensional random access memories
Microelectronics Reliability 52 (2012) 1065–1070
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Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Yield enhancement techniques for 3-dimensional random access memories Shyue-Kung Lu ⇑, Tin-Wei Chang, Han-Yu Hsu Dept. of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan
a r t i c l e
i n f o
Article history: Received 18 August 2011 Received in revised form 15 December 2011 Accepted 15 December 2011 Available online 5 January 2012
a b s t r a c t As the advances of process technology keep growing, three-dimensional (3D) integration with through silicon vias is a new alternative solution to extend Moore’s law especially for random access memories (RAMs). In general, the reliability and fabrication yield of the traditional 2D memories can be improved by the incorporation of some form of redundancy. However, for 3D integration, the scenarios for the repair process are totally different. The redundancy exclusively added in a memory tier can also be reused to repair defects in the other memory tier after the bonding process. That is, the concept of inter-tier redundancy can be exploited to further increase the yield of 3D memories. Die-to-die and die-to-wafer bonding can be adopted. In this paper, we propose an efficient die-stacking flow and the corresponding built-in self-repair architectures for yield enhancement of 3D memories. The matching problem for die stacking can be converted into a bipartite graph maximal matching problem and the traditional algorithm can be used to solve this problem. Experimental results show that the proposed stacking flow, algorithm, and the corresponding BISR (built-in self-repair) architecture can improve fabrication yield significantly. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction Semiconductor memories play a pivot role for most electronic products. According to the Semiconductor Industry Association (SIA) and ITRS 2007, the relative silicon area occupied by embedded memories will approach 94% by 2014 [1]. Since embedded memories have higher complexity and higher density than other logic blocks, they have higher failure possibility. Therefore, an appropriate fault-tolerant and reliable design technique should be incorporated into the chip at the design stage. For the conventional 2D memories, the reliability and fabrication yield of embedded memories can be improved by the incorporation of some form of redundancy. Conventional ways to add redundancy into an embedded memory array include: Redundant rows or redundant columns [2,3]: By using this approach, redundant rows or columns are added into the memory array. One of the redundant rows/columns is used to replace the faulty row/column. Redundant rows and redundant columns [4–7]: By using this approach, both redundant rows and columns are incorporated into the memory array. When a faulty cell is detected, we can use a redundant row or a redundant column to replace it. It is more efficient than the first approach when multiple faulty cells exist in the memory array.
⇑ Corresponding author. E-mail address: [email protected] (S.-K. Lu). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.12.017
Three-dimensional integration with through silicon via (TSV) is an emerging technology and has attracted many attentions from both industry and academia recently [8]. It has many potential benefits like higher performance and data bandwidth, lower power consumption and form factor. For the conventional redundancy mechanisms described above, the assumption is that the added redundancy can only be exclusively used by the memory die containing it. We thereafter call this type of redundancy as intra-tier redundancy. However, this may not be suitable for 3D integration of memories. The reason is that for the memory dies unable to be repaired with their intra-tier redundancy, we may still devote our efforts to exploit the possibility to repair them by using redundancy in other tier after the stacking process. We call this concept the inter-tier redundancy. For example, by using the inter-tier redundancy concept, it is even possible that two irreparable memory dies can be bonded together and repaired successfully with the full storage capability. To make this possible, the required amount of redundancy for one memory die can be provided by the available redundancy in another die and vice versa. If the remained amount of redundancy for each memory die is available after the pre-bond test and repair procedures, then suitable die stacking techniques are required for effectively yield enhancement of 3D memories. To make the inter-tier redundancy concept useful, two basic issues should be addressed: 1. The local BISR controller should be modified globally. In other words, instead of considering the intra-tier redundancy during pre-bond test, it is also required for it to consider the inter-tier redundancy after bonding.
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2. For die stacking, it is required to maximize the effective yield after stacking. We cannot stack memory dies randomly. Alternately, we can stack memory dies which will exploit the maximum usage of inter-tier redundancy. This will eventually improve the fabrication yield significantly. As we know, there are three 3D integration methods— Die-toDie (DTD), Die-to-Wafer (DTW), and Wafer-to-Wafer (WTW). These methods have different considerations in terms of throughput, integration yield, and fabrication cost. Although WTW stacking has the optimal stacking throughput, it will always incur unnecessary yield loss when a bad die in one wafer is stacked with a good die in another wafer to produce a whole bad 3D IC. DTD and DTW stacking need more test and bonding cost [9]. However, these two methods can improve the yield of 3D ICs since all the dies can be tested and diced before bonding. For the conventional methods, only good dies will be bonded. Bad dies will be discarded completely. However, a yield enhancement technique by bad-die recycling and WTW integration can be found in [9,15]. In general, if redundancy is added for each die (especially for memories), a bad die (internal redundancies are exhaustively used) can still have the opportunity to be repaired by the redundancies from another die. Therefore, in this work, we propose an efficient die-stacking flow and the corresponding built-in self-repair architecture for yield enhancement of 3D memories. We use the DTD stacking method to illustrate the proposed inter-tier redundancy concept. The proposed methods and BISR flow can be easily applied to DTW integration. Based on the proposed concept, more researches can be performed for application to WTW integration. We assume that the intra-tier redundancy includes spare rows and spare columns. The die stacking problem then can be converted to a bipartite graph maximal matching problem and the conventional algorithm can be used to solve it. A simulator is also implemented to evaluate the effectiveness of the proposed techniques. Experimental results show that the proposed stacking flow and BISR architecture can improve fabrication yield significantly. The organization of this paper is as follows. In Section 2, the BISR flow for 3D memories (3D-BISR) and the shared redundancy architectures are proposed. Section 3 describes the die stacking flow. In Section 4, we convert the die stacking problem into the bipartite graph maximal matching problem and the complexity to solve this problem is shown. A simulator was implemented for analyzing the efficiency of the proposed techniques and experimental results for different fault distributions and memory sizes are shown in Section 5. Finally, some conclusions are given in Section 6.
2. BISR flow and architecture for 3D memory integration (3DBISR) In order to ease our discussion, some notations should be defined first. Let SR (SC) denote the number of spare rows (columns) in the memory die. NRC and NAC represent the number of required and available spare columns for the memory die, respectively. That is, NRC is the number of spare columns that should be exploited from inter-tier redundancy and NAC represents the number of available spare columns that can be used as inter-tier redundancy for repairing after die stacking. The number of spare (available) rows (NRR (NAR)) can be defined analogously. A typical BISR flow for 2D memories is shown in Fig. 1a. The BIST (built-in self-test) module performs a specified March algorithm to detect functional faults in the redundant memory module and the main memory module. When a fault is detected, the BISD (built-in self-diagnosis) mode is executed which will report the
(a)
(b) Fig. 1. (a) Conventional memory BISR flow and (b) the 3D-BISR flow.
fault syndrome of the fault (including the fault location and the erroneous signature) to the BIRA (built-in redundancy analysis) circuit. According to the received information, the BIRA module starts to perform redundancy allocation. If there are still available redundancies that can be used to repair this fault, the BIST, BISD and BIRA operations will be iterated until all the test processes are finished. The BIST module will stop the test operation when either the memory is reported irreparable or the entire memory is tested and repaired successfully. The modified BISR flow suitable for 3D memory integration is shown in Fig. 1b. All memory tiers have their internal BIST, BISD, and BIRA modules and they are tested and repaired by their own BISR circuitry. If the BIRA module reports that there are no available redundancies, it means that the memory tier cannot be repaired successfully by merely using intra-tier redundancy. However, the BIRA module should also report the values of NRC and NRR. If NRC > SC or NRR > SR, it is impossible to repair this memory tier successfully by reusing inter-tier redundancies provided by other entirely fault-free memory tier. Therefore, this memory tier is identified as a failed die and cannot be used for memory stacking. Otherwise, if the test process is finished, the BIRA module will report the values of NRC and NRR which indicate the number of spares that should be exploited from other memory tiers. As shown in Fig. 1b, if the memory tier can be repaired successfully, the BIRA module will report the values of NAC and NAR which indicate the number of memory spares that can be reused by other memory tiers. It should be noted that even an irreparable memory tier has available spares. Two irreparable memory tiers can also have the opportunity to be repaired successfully after stacking if
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the value of NAC (NAR) of one die is greater than the value of NRC (NRR) of another die. The hardware architecture of the inter-tier BISR architecture is shown in Fig. 2. To facilitate BISR techniques for 3D stacked memories, we should first determine the 3D memory architectures which have the low-power and high-performance benefits. This is helpful for partitioning a memory design across several layers. There are three typical types of 3D memory architectures—stacked banks, cell arrays stacked on logic, and intra-cell partitioning [17,18]. In order to support pre-bond wafer tests (KGD) and KGS tests, the peripheral logic (sense amplifiers, row/column decoders, etc.) should be incorporated with the memory dies in each layer. Therefore, we assume that the stacked banks 3D memory architecture is adopted. As can be seen from Fig. 2, spare elements are added for each memory tier. We can see that the dedicated BISR circuitry (BIST, BISD, and BIRA modules) are added for each memory tier. The wrappers are used to switch between normal mode and BISR mode. As in the 2D memory, the reconfiguration mechanism is used to swap faulty elements [10,11] and the multiplexers are used to select outputs from either the main memory or the spare memory. The dedicated BISR module is used for each memory tier during pre-bond testing and determines the values of NAC, NRC, NAR, and NRR. After receiving the signal to activate the BIST module, it will then generate the adopted March patterns to test the memory dies. Once faulty cells are detected, the BIRA module is then activated for redundancy analysis. The redundancy analysis algorithm used is the ESP algorithm [16]. It will generate a nearly optimal spare allocation solution. After finishing the BIST and BIRA procedures, the values of NAR, NAC, NRC, and NRR can then be determined. Moreover, the hardware overhead defined as the ratio between the required extra transistor count for BISR and the transistor count of the whole memory array is about 0.58% [20] for a 2 Mbit SRAM with 2 spare rows and two spare columns. The added hardware overhead is almost negligible. Therefore, the incurred extra power consumption of the redundancy mechanism is also very small. After the bonding, the spares used in each tier of the 3D memory, the dedicated BISR modules, memory arrays, I/O signals, and reconfiguration mechanisms can be connected by TSVs as shown in this figure. One of the BISR modules (the master BISR) then performs the BIST/BISR procedure. The slave BISR module then can be used as a redundant BISR module. If one of the BISR modules is faulty, then the roles of the BISR modules can be interchanged. This will further increase the yield of the memory tiers after stacking.
3. Die stacking flow In general, after the pre-bond test procedure, only good dies (KGD’s) can be used for stacking for 3D integration and all the bad dies should be discarded directly. It is evident that the resulting yield will be very low. Therefore, to efficiently use the inter-tier redundancy architecture and optimize the yield of 3D RAMs, the die stacking algorithm play an important role. As shown in Fig. 3, the proposed stacking technique consists of 4 steps—pre-bond test and BISR, classification, matching, and post-bond test and BISR. The pre-bond test can be performed by the BIST circuitry and the faulty elements can be analyzed by the BISR module to seek for possible spare allocation. After finishing the BIST and BISR procedures for each memory die, all the memory dies can be categorized into four sets (we assume redundant columns are added)— GDAC (good dies with available spare columns), GDNC (good dies with no available spare columns), BDRC (bad dies which require spare columns), and BDERC (bad dies which require excessive spare rows/columns), according to the redundancy analysis results reported by the BISR module. The set GDAC denotes the set of good dies (either fault free or repairable) with available spare columns which can be reused for repairing faulty memory elements in other memory dies. GDNC denotes the set of memory dies that can be repaired successfully by exhaustively using all the intra-tier spare columns. Therefore, each die belongs to the set GDNC cannot provide any redundancy for inter-tier usage. The set of memory dies which cannot be repaired with the intra-die spare columns and require less than SC (SR) spare columns (rows) to repair them successfully is denoted as BDRC (bad dies which requires inter-tier spare columns (rows)). The set of memory dies which cannot be repaired with the intradie spare columns and require more than SC (SR) spare columns (rows) to repair them successfully is denoted as BDERC (bad dies which requires excessive inter-tier spare columns/rows). The memory dies in BDERC can be viewed as failed dies (Fig. 1) and can be discarded directly. Moreover, the memory dies in GDNC cannot be stacked with any faulty dies in BDRC since they cannot provide any spare elements for inter-tier usage. The only possible opportunity for increasing fabrication yield is by stacking memory dies belonging to GDAC and BDRC, respectively. The die stacking flow then can be modeled as a bipartite maximal matching problem. After the matching procedures, the remained memory dies in GDAC and GDNC then can be randomly stacked without sacrificing the yield. Two dies in GDAC and BDRC, respectively, are said to be compatible if one die’s NRC/NAC are less/more than the other die’s NAC/ NRC. If two dies are compatible, they can be stacked successfully
Reconfiguration . . . Mechanism
Spare Elements
BIRA
M
Master BISR
U
BISD
X
Main Memory
BIST
Wrapper Data Address Control
Data out
TSVs Reconfiguration . . . Mechanism
TSVs
TSVs
Spare Elements
BIRA
M
Slave BISR
X
Main Memory
U
BISD
BIST
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Wrapper
Fig. 2. The inter-tier redundancy architecture.
Data out
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Fault Injection for Memory Dies
BIST & BISR Procedures
Defect & fault information March Algorithm Memory Specifications RA Algorithm (ESP) Spare Element Organization
Die Classification
Fig. 3. 3D-IC stacking flow.
without yield loss. This will be very helpful for 3D integration of memories.
Maximal Matching for Stacking
Yield Evaluation
Fig. 5. Flow chart of the simulator.
4. Problem modeling for the die stacking flow As described in the previous section, when the pre-bond test and BISR flow are finished, each die is categorized into the four die sets and the values of NRC and NAC for each die are also stored. The maximum matching algorithm is performed only for the memory dies in GDAC and BDRC. Definition. A graph G(V, E) (or G(V1, V2, E)) is called a bipartite graph if its vertex set V is the disjoint union of set V1 and V2 and every edge in E has the form (v1, v2), where v1 2 V1 and v2 2 V2 [12]. Let the die sets BDAC and GDAC be the vertex sets V1 and V2, respectively. Therefore, each node in the bipartite graph denotes a memory die. For each node in V1 (V2), a positive number is associated with it which denotes the value of NRC (NAC). Two nodes v1 2 V1 and v2 2 V2 are connected with an edge if the value associated with v1 is less than or equal to that in v2. These two nodes are said to be compatible. An example is shown in Fig. 4. The vertex sets V1 and V2 contain 5 vertices, respectively. The total number of edges is 18. Two dies in V1 and V2 can be stacked if an edge is connected between them. To increase the yield after stacking, we have to find the maximal matching pairs. Therefore, the DTD stacking problem is converted to a bipartite maximum matching problem. The complexity to solve this problem is proved to be O(V(V + E)) [13]. 5. Experimental results We have implemented a simulator to evaluate the effectiveness of the proposed BISR and die stacking flow. The flow chart of the simulator is shown in Fig. 5. As this figure shows, the simulation flow consists of the fault injection stage, the BIST and BISR stage, the Die classification stage, the maximal matching stage, and the yield evaluation stage. In the fault injection stage, we can specify
the memory specifications, the adopted March algorithms, and defect and fault information for the BIST module. We assume that the number of defects in the memory die is modeled by Poisson distribution. Although bulk defects are possible, we assume only spot defects here. Note that the manifestation of a defect may result in various fault patterns [14]. We collect eight fault patterns and classify them into three faulty types–faulty cell, faulty column, and faulty row (cluster faults are not considered for simplification) as shown in Fig. 6. For example, the type faulty_column consists of stuck-at-0, stuck-at-1 and random faults can be described as SA0, SA1, and random, respectively. With these fault patterns, defects are transformed to them according to the specified probability distributions. After that, our simulator can generate a faulty memory with the faults which can be detected by the different read operations of the adopted March algorithms. This is used to simulate the sequence of the faults detected by the BIST circuit which should be used for analysis of spare allocation in the following stage. During the BIST and BISR stage, the simulator performs the adopted March algorithms. After faulty cells are detected, the spare elements (defined by the user) can be used to repair them and the values of NAC and
Faulty_Cell
Faulty_Column
Faulty_Row
FP1
FP4
FP7
FP2
FP5
FP8 SAF 1 SAF 0
FP3 Fig. 4. An example bipartite graph.
FP6 Fig. 6. The mapped fault types.
Random Fault
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Fig. 7. Parameter setting for the simulator’s graphical user interface (GUI).
NRC for each die can be determined after finishing this step. We assume that the March C algorithm is used for the BIST circuit and the ESP (Essential Spare Pivoting) algorithm [16] is used for redundancy analysis. The next step is the die classification stage. According to the values of NAC and NRC, the memory dies are classified into four die sets–GDNC, GDAC, BDRC, and BDERC. The dies in BDERC are discarded directly and not used for stacking. The conventional maximum matching algorithm is performed for dies in GDAC and BDRC. The remained dies in GDAC are randomly stacked with dies in GDNC. After the matching stage, we can evaluate the yield after die stacking.
To simplify the yield analysis, two assumptions are made first. First, we assume all failures on the memory chip are the result of spot defects. Spot defects are in contrast to global defects, which affect complete sections of a chip or wafer. Second, any single spot defect will result in the chip being inoperative unless some types of redundancy are included. Let Y0 denote the yield the non-redundant memory array and PESP be the probability of successful allocation (repair rate) with the adopted ESP algorithm. Then, the yield YESP can be expressed as follows
Table 1 Effective yield after stacking (512 1024 32).
Table 3 Effective yield after stacking (1024 1024 32).
1R1C 1R2C 1R3C 2R1C 2R2C 2R3C 3R1C 3R2C 3R3C
60% SCFs, 20% FRs, and 20% FCs
100% SCFs Intra-tier redundancy
Inter-tier redundancy
Intra-tier redundancy
Inter-tier redundancy
3.0 26.2 77.0 25.6 76.6 97.9 97.6 100 100
3.0 27.9 100 28.3 99.7 100 97.6 100 100
2.0 17.4 44.2 17.4 42.7 58.5 39.5 57.4 65.5
2.0 19.3 58.9 19.0 60.5 66.7 55.1 72.2 77.1
Intra-tier redundancy
Inter-tier redundancy
Intra-tier redundancy
Inter-tier redundancy
3 28.2 78 24 76.2 98.5 76.1 98.1 100
3 31.2 100 26.4 100 100 100 100 100
2.8 19.1 55.8 16.4 42.6 55.7 40.9 55.0 67.2
3 21.9 68.1 18.0 57.3 69.0 55.0 75.8 77.7
1R1C 1R2C 1R3C 2R1C 2R2C 2R3C 3R1C 3R2C 3R3C
60% SCFs, 20% FRs, and 20% FCs
Table 4 Effective yield after stacking (1024 1024 32).
Table 2 Effective yield after stacking (512 1024 32).
Memory size 1024 1024 32, unit (%)
Memory size 512 1024 32, unit (%)
1R1C 1R2C 1R3C 2R1C 2R2C 2R3C 3R1C 3R2C 3R3C
Y0 is basically the proportion of dies in GDNC and GDAC. However, if inter-die redundancy is used, the dies in BDRC can be reused for
Memory size 1024 1024 32, unit (%)
Memory size 512 1024 32, unit (%) 100% SCFs
Y ESP ¼ Y 0 þ ð1 Y 0 ÞP ESP :
60% SCFs and 40% FRs
60% SCFs and 40% FCs
60% SCFs and 40% FRs
60% SCFs and 40% FCs
Intra-tier redundancy
Inter-tier redundancy
Intra-tier redundancy
Inter-tier redundancy
Intra-tier redundancy
Inter-tier redundancy
Intra-tier redundancy
Inter-tier redundancy
1.8 14.6 26.7 19.2 40.5 44.00 54.7 61.1 63.1
1.8 16.4 29.8 22.2 45.6 50.5 61.1 63.1 67.5
2.0 21.1 58.7 14.4 42.7 65.3 25.5 43.7 63.2
2.0 22.9 79.6 15.4 56.1 99.9 35.1 69.5 100
2.1 14.3 27.2 18.6 41.0 61.6 56.4 63.7 65.6
2.1 15.7 41.8 20.7 45.7 68.8 63.5 67.3 70.7
2.0 21.1 58.7 14.2 41.6 62.8 26.2 45.1 64.8
2.0 22.9 79.6 15.5 56.3 100 35.7 73.3 100
1R1C 1R2C 1R3C 2R1C 2R2C 2R3C 3R1C 3R2C 3R3C
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100% 90% 80% 70%
100% SCF Intra-Tier Redundnacy (512 × 1024 × 32) Inter-Tier Redundancy (512 × 1024 × 32) Intra-Tier Redundnacy (1024 × 1024 × 32) Inter-Tier Redundancy (1024 × 1024 × 32)
60% 50% 40% 30% 20% 10% 0% 1R/1C
1R/2C
1R/3C
2R/1C
2R/2C
2R/3C
3R/1C
3R/2C
3R/3C
Fig. 8. The comparison of two sizes in 100% SCFs.
stacking with dies in GDAC. Moreover, according to the proposed die stacking algorithm, the effective yield can be improved significantly. The graphic user interface (GUI) of the simulator is shown in Fig. 7. Two memory sizes are used in our simulation–512 1024 32 and 1024 1024 32. The average number of defects injected is 4. Four different fault distributions are applied for the simulator. The first fault distribution is 100% single cell faults (SCFs). The second fault distribution is 60% SCFs, 20% faulty rows (FRs), and 20% faulty columns (FCs). The third fault distribution is 60% SCFs and 40% FRs. The final fault distribution is 60% SCFs and 40% FCs. These fault profiles can be verified from the foundry data provided in [19]. Simulation results for the memory size 512 1024 32 are shown in Tables 1 and 2. The term xRyC denotes that x spare rows and y spare columns are added as redundancy. The column ‘‘Intra-Tier Redundancy’’ denotes that the redundancy in the memory die will not be reused by the memory die stacked with it. Therefore, the memory dies in BDRC and BDERC will all be discarded. The column ‘‘Inter-Tier Redundancy’’ denotes that each die’s redundancy can be reused by the memory die stacked with it. That is, the stacking flow shown in Fig. 3 is used. From these tables we can see that if more redundancies are added, the effective yield will increase for either the inter-tier or intra-tier redundancy mechanism. However, the yield for the inter-tier redundancy is always higher than that of the intra-tier redundancy. Moreover, if the yield of intra-tier redundancy is very low (e.g., 3%) or very high (e.g., 100%), the yield will not be further increased if inter-tier redundancy is used instead. However, these two situations occur not often in practical process technology and stacking flow. For the average yield level, (70–80%), the yield improvement by inter-tier redundancy is significant. This situation is practical since significant yield ramp-up can be achieved by this technique. We can also find that if the proportion of FRs (FCs) increases, the yield will be higher if more spare rows (columns) are added. The same observations can be found from Tables 3 and 4 for the memory size 1024 1024 32. The comparisons of the effective yield after stacking are shown in Fig. 8. As shown in this figure, if a large amount of redundancy is added (e.g., 3R3C), the yield improvement is almost negligible. The same situation also occur for very low yield dies (e.g., 1R1C). More yield improvement can be found for average yield levels such as 1R3C, 2R2C, and 3R1C. 6. Conclusions In this paper, a novel BISR and stacking flow based on inter-tier redundancy technique was proposed for yield improvement of 3D memories. The redundancy exclusively added in a memory tier can
also be reused to repair defects in the other memory tier after the bonding process. Therefore, we can further increase the yield of 3D memories after stacking. The stacking procedure by using inter-tier redundancy can be modeled as a bipartite maximal matching problem and conventional algorithms can be used to solve it. A simulator was also implemented to verify the effectiveness of the proposed techniques. Experimental results show that the proposed BISR and stacking flow can improve the yield significantly. References [1] The International Technology Roadmap for Semiconductors. SIA; 2007. [2] Bhavsar DK. An algorithm for row-column self-repair of RAMs and its implementation in the alpha 21264. In: Proc Int’l Test Conf; September 1999. p. 311–18. [3] Ilyoung I Kim, Zorian Y, Komoriya G, Pham H, Higgins FP, Lewandowski JL. Built In Self Repair for Embedded High Density SRAM. In: Proc Int’l Test Conf; October 1998. p. 1112–9. [4] Huang WK, Shen YH, Lombrardi F. New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement. IEEE Trans Comput Aided Des 1990;9(3):323–8. [5] Horiguchi M, Etoh J, Aoki M, Itoh K, Matsumoto T. A flexible redundancy technique for high-density DRAM’s. IEEE J Solid-State Circuits 1991;26(1). [6] Mazumder P, Jih YS. A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits. IEEE Trans Comput Aided Des 1993;12(1). [7] Kim HC, Yi DS, Park JY, Cho CH. A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies. In: Proc Int’l Conf on VLSI and CAD; October 1999. p. 602–5. [8] Lu JQ. 3-D Hyperintegration and packaging technologies for micro-nano systems. Proc IEEE 2009;97(1):18–30. [9] Reda S, Smith G, Smith L. Maximizing the functional yield of wafer-to-wafer 3D integration. IEEE Trans VLSI Syst 2009;17(9):1352–7. [10] Lu SK, Hsu CH, Tsai YC, Wang KH, Wu CW. Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. IEEE Trans VLSI Syst 2006;14(1):31–42. [11] Deng LM, Wang TC, Wu CW. An enhanced SRAM BISR design with reduced timing penalty. In: Proc 15th Asian Test Symp (ATS), Fukuoka, Japan; November 2006. p. 25–30. [12] Levitin A. Introduction to the design & analysis of algorithms. Addison Wesley; 2006. [13] Mchugh JA. Algorithm graph theory. Englewood Cliffs, NJ: Prentice-Hall; 1990. [14] Cheng KL, Wang CW, Lee JN, Chou YF, Huang CT. FAME: a fault-pattern based memory failure analysis framework. In: Proc Int’l Conf on Computer Aided Design; November 2003. p. 595–8. [15] Chou YF, Kwai DM, Wu CW. Yield enhancement by bad-die recycling and stacking with through-silicon vias. IEEE Trans VLSI Systems 2011;19(8): 1346–56. [16] Huang CT, Wu CF, Li JF, Wu CW. Built-in redundancy analysis for memory yield improvement. IEEE Trans Rel 2003;52:386–99. [17] Puttaswamy K et al. 3D-integrated SRAM components for high-performance microprocessors. IEEE Trans Comput 2009;58(10):1369–81. [18] Tauuli M, Hamdioui S. Layer redundancy based yield improvement for 3D wafer-to-wafer stacked memories. In: Proc European Test Symp; May 2011. p. 45–50. [19] Segal J, Jee A, Lepejian D, Chu B. Using electrical bitmap results from embedded memory to enhance yield. IEEE Des Test Comput 2001:28–39. [20] Lu SK, Yang CL, Hsiao YC, Wu CW. Efficient BISR techniques for embedded memories considering cluster faults. IEEE Trans VLSI Syst 2010;18(2):184–93.
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Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Yield enhancement techniques for 3-dimensional random access memories Shyue-Kung Lu ⇑, Tin-Wei Chang, Han-Yu Hsu Dept. of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan
a r t i c l e
i n f o
Article history: Received 18 August 2011 Received in revised form 15 December 2011 Accepted 15 December 2011 Available online 5 January 2012
a b s t r a c t As the advances of process technology keep growing, three-dimensional (3D) integration with through silicon vias is a new alternative solution to extend Moore’s law especially for random access memories (RAMs). In general, the reliability and fabrication yield of the traditional 2D memories can be improved by the incorporation of some form of redundancy. However, for 3D integration, the scenarios for the repair process are totally different. The redundancy exclusively added in a memory tier can also be reused to repair defects in the other memory tier after the bonding process. That is, the concept of inter-tier redundancy can be exploited to further increase the yield of 3D memories. Die-to-die and die-to-wafer bonding can be adopted. In this paper, we propose an efficient die-stacking flow and the corresponding built-in self-repair architectures for yield enhancement of 3D memories. The matching problem for die stacking can be converted into a bipartite graph maximal matching problem and the traditional algorithm can be used to solve this problem. Experimental results show that the proposed stacking flow, algorithm, and the corresponding BISR (built-in self-repair) architecture can improve fabrication yield significantly. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction Semiconductor memories play a pivot role for most electronic products. According to the Semiconductor Industry Association (SIA) and ITRS 2007, the relative silicon area occupied by embedded memories will approach 94% by 2014 [1]. Since embedded memories have higher complexity and higher density than other logic blocks, they have higher failure possibility. Therefore, an appropriate fault-tolerant and reliable design technique should be incorporated into the chip at the design stage. For the conventional 2D memories, the reliability and fabrication yield of embedded memories can be improved by the incorporation of some form of redundancy. Conventional ways to add redundancy into an embedded memory array include: Redundant rows or redundant columns [2,3]: By using this approach, redundant rows or columns are added into the memory array. One of the redundant rows/columns is used to replace the faulty row/column. Redundant rows and redundant columns [4–7]: By using this approach, both redundant rows and columns are incorporated into the memory array. When a faulty cell is detected, we can use a redundant row or a redundant column to replace it. It is more efficient than the first approach when multiple faulty cells exist in the memory array.
⇑ Corresponding author. E-mail address: [email protected] (S.-K. Lu). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.12.017
Three-dimensional integration with through silicon via (TSV) is an emerging technology and has attracted many attentions from both industry and academia recently [8]. It has many potential benefits like higher performance and data bandwidth, lower power consumption and form factor. For the conventional redundancy mechanisms described above, the assumption is that the added redundancy can only be exclusively used by the memory die containing it. We thereafter call this type of redundancy as intra-tier redundancy. However, this may not be suitable for 3D integration of memories. The reason is that for the memory dies unable to be repaired with their intra-tier redundancy, we may still devote our efforts to exploit the possibility to repair them by using redundancy in other tier after the stacking process. We call this concept the inter-tier redundancy. For example, by using the inter-tier redundancy concept, it is even possible that two irreparable memory dies can be bonded together and repaired successfully with the full storage capability. To make this possible, the required amount of redundancy for one memory die can be provided by the available redundancy in another die and vice versa. If the remained amount of redundancy for each memory die is available after the pre-bond test and repair procedures, then suitable die stacking techniques are required for effectively yield enhancement of 3D memories. To make the inter-tier redundancy concept useful, two basic issues should be addressed: 1. The local BISR controller should be modified globally. In other words, instead of considering the intra-tier redundancy during pre-bond test, it is also required for it to consider the inter-tier redundancy after bonding.
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2. For die stacking, it is required to maximize the effective yield after stacking. We cannot stack memory dies randomly. Alternately, we can stack memory dies which will exploit the maximum usage of inter-tier redundancy. This will eventually improve the fabrication yield significantly. As we know, there are three 3D integration methods— Die-toDie (DTD), Die-to-Wafer (DTW), and Wafer-to-Wafer (WTW). These methods have different considerations in terms of throughput, integration yield, and fabrication cost. Although WTW stacking has the optimal stacking throughput, it will always incur unnecessary yield loss when a bad die in one wafer is stacked with a good die in another wafer to produce a whole bad 3D IC. DTD and DTW stacking need more test and bonding cost [9]. However, these two methods can improve the yield of 3D ICs since all the dies can be tested and diced before bonding. For the conventional methods, only good dies will be bonded. Bad dies will be discarded completely. However, a yield enhancement technique by bad-die recycling and WTW integration can be found in [9,15]. In general, if redundancy is added for each die (especially for memories), a bad die (internal redundancies are exhaustively used) can still have the opportunity to be repaired by the redundancies from another die. Therefore, in this work, we propose an efficient die-stacking flow and the corresponding built-in self-repair architecture for yield enhancement of 3D memories. We use the DTD stacking method to illustrate the proposed inter-tier redundancy concept. The proposed methods and BISR flow can be easily applied to DTW integration. Based on the proposed concept, more researches can be performed for application to WTW integration. We assume that the intra-tier redundancy includes spare rows and spare columns. The die stacking problem then can be converted to a bipartite graph maximal matching problem and the conventional algorithm can be used to solve it. A simulator is also implemented to evaluate the effectiveness of the proposed techniques. Experimental results show that the proposed stacking flow and BISR architecture can improve fabrication yield significantly. The organization of this paper is as follows. In Section 2, the BISR flow for 3D memories (3D-BISR) and the shared redundancy architectures are proposed. Section 3 describes the die stacking flow. In Section 4, we convert the die stacking problem into the bipartite graph maximal matching problem and the complexity to solve this problem is shown. A simulator was implemented for analyzing the efficiency of the proposed techniques and experimental results for different fault distributions and memory sizes are shown in Section 5. Finally, some conclusions are given in Section 6.
2. BISR flow and architecture for 3D memory integration (3DBISR) In order to ease our discussion, some notations should be defined first. Let SR (SC) denote the number of spare rows (columns) in the memory die. NRC and NAC represent the number of required and available spare columns for the memory die, respectively. That is, NRC is the number of spare columns that should be exploited from inter-tier redundancy and NAC represents the number of available spare columns that can be used as inter-tier redundancy for repairing after die stacking. The number of spare (available) rows (NRR (NAR)) can be defined analogously. A typical BISR flow for 2D memories is shown in Fig. 1a. The BIST (built-in self-test) module performs a specified March algorithm to detect functional faults in the redundant memory module and the main memory module. When a fault is detected, the BISD (built-in self-diagnosis) mode is executed which will report the
(a)
(b) Fig. 1. (a) Conventional memory BISR flow and (b) the 3D-BISR flow.
fault syndrome of the fault (including the fault location and the erroneous signature) to the BIRA (built-in redundancy analysis) circuit. According to the received information, the BIRA module starts to perform redundancy allocation. If there are still available redundancies that can be used to repair this fault, the BIST, BISD and BIRA operations will be iterated until all the test processes are finished. The BIST module will stop the test operation when either the memory is reported irreparable or the entire memory is tested and repaired successfully. The modified BISR flow suitable for 3D memory integration is shown in Fig. 1b. All memory tiers have their internal BIST, BISD, and BIRA modules and they are tested and repaired by their own BISR circuitry. If the BIRA module reports that there are no available redundancies, it means that the memory tier cannot be repaired successfully by merely using intra-tier redundancy. However, the BIRA module should also report the values of NRC and NRR. If NRC > SC or NRR > SR, it is impossible to repair this memory tier successfully by reusing inter-tier redundancies provided by other entirely fault-free memory tier. Therefore, this memory tier is identified as a failed die and cannot be used for memory stacking. Otherwise, if the test process is finished, the BIRA module will report the values of NRC and NRR which indicate the number of spares that should be exploited from other memory tiers. As shown in Fig. 1b, if the memory tier can be repaired successfully, the BIRA module will report the values of NAC and NAR which indicate the number of memory spares that can be reused by other memory tiers. It should be noted that even an irreparable memory tier has available spares. Two irreparable memory tiers can also have the opportunity to be repaired successfully after stacking if
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the value of NAC (NAR) of one die is greater than the value of NRC (NRR) of another die. The hardware architecture of the inter-tier BISR architecture is shown in Fig. 2. To facilitate BISR techniques for 3D stacked memories, we should first determine the 3D memory architectures which have the low-power and high-performance benefits. This is helpful for partitioning a memory design across several layers. There are three typical types of 3D memory architectures—stacked banks, cell arrays stacked on logic, and intra-cell partitioning [17,18]. In order to support pre-bond wafer tests (KGD) and KGS tests, the peripheral logic (sense amplifiers, row/column decoders, etc.) should be incorporated with the memory dies in each layer. Therefore, we assume that the stacked banks 3D memory architecture is adopted. As can be seen from Fig. 2, spare elements are added for each memory tier. We can see that the dedicated BISR circuitry (BIST, BISD, and BIRA modules) are added for each memory tier. The wrappers are used to switch between normal mode and BISR mode. As in the 2D memory, the reconfiguration mechanism is used to swap faulty elements [10,11] and the multiplexers are used to select outputs from either the main memory or the spare memory. The dedicated BISR module is used for each memory tier during pre-bond testing and determines the values of NAC, NRC, NAR, and NRR. After receiving the signal to activate the BIST module, it will then generate the adopted March patterns to test the memory dies. Once faulty cells are detected, the BIRA module is then activated for redundancy analysis. The redundancy analysis algorithm used is the ESP algorithm [16]. It will generate a nearly optimal spare allocation solution. After finishing the BIST and BIRA procedures, the values of NAR, NAC, NRC, and NRR can then be determined. Moreover, the hardware overhead defined as the ratio between the required extra transistor count for BISR and the transistor count of the whole memory array is about 0.58% [20] for a 2 Mbit SRAM with 2 spare rows and two spare columns. The added hardware overhead is almost negligible. Therefore, the incurred extra power consumption of the redundancy mechanism is also very small. After the bonding, the spares used in each tier of the 3D memory, the dedicated BISR modules, memory arrays, I/O signals, and reconfiguration mechanisms can be connected by TSVs as shown in this figure. One of the BISR modules (the master BISR) then performs the BIST/BISR procedure. The slave BISR module then can be used as a redundant BISR module. If one of the BISR modules is faulty, then the roles of the BISR modules can be interchanged. This will further increase the yield of the memory tiers after stacking.
3. Die stacking flow In general, after the pre-bond test procedure, only good dies (KGD’s) can be used for stacking for 3D integration and all the bad dies should be discarded directly. It is evident that the resulting yield will be very low. Therefore, to efficiently use the inter-tier redundancy architecture and optimize the yield of 3D RAMs, the die stacking algorithm play an important role. As shown in Fig. 3, the proposed stacking technique consists of 4 steps—pre-bond test and BISR, classification, matching, and post-bond test and BISR. The pre-bond test can be performed by the BIST circuitry and the faulty elements can be analyzed by the BISR module to seek for possible spare allocation. After finishing the BIST and BISR procedures for each memory die, all the memory dies can be categorized into four sets (we assume redundant columns are added)— GDAC (good dies with available spare columns), GDNC (good dies with no available spare columns), BDRC (bad dies which require spare columns), and BDERC (bad dies which require excessive spare rows/columns), according to the redundancy analysis results reported by the BISR module. The set GDAC denotes the set of good dies (either fault free or repairable) with available spare columns which can be reused for repairing faulty memory elements in other memory dies. GDNC denotes the set of memory dies that can be repaired successfully by exhaustively using all the intra-tier spare columns. Therefore, each die belongs to the set GDNC cannot provide any redundancy for inter-tier usage. The set of memory dies which cannot be repaired with the intra-die spare columns and require less than SC (SR) spare columns (rows) to repair them successfully is denoted as BDRC (bad dies which requires inter-tier spare columns (rows)). The set of memory dies which cannot be repaired with the intradie spare columns and require more than SC (SR) spare columns (rows) to repair them successfully is denoted as BDERC (bad dies which requires excessive inter-tier spare columns/rows). The memory dies in BDERC can be viewed as failed dies (Fig. 1) and can be discarded directly. Moreover, the memory dies in GDNC cannot be stacked with any faulty dies in BDRC since they cannot provide any spare elements for inter-tier usage. The only possible opportunity for increasing fabrication yield is by stacking memory dies belonging to GDAC and BDRC, respectively. The die stacking flow then can be modeled as a bipartite maximal matching problem. After the matching procedures, the remained memory dies in GDAC and GDNC then can be randomly stacked without sacrificing the yield. Two dies in GDAC and BDRC, respectively, are said to be compatible if one die’s NRC/NAC are less/more than the other die’s NAC/ NRC. If two dies are compatible, they can be stacked successfully
Reconfiguration . . . Mechanism
Spare Elements
BIRA
M
Master BISR
U
BISD
X
Main Memory
BIST
Wrapper Data Address Control
Data out
TSVs Reconfiguration . . . Mechanism
TSVs
TSVs
Spare Elements
BIRA
M
Slave BISR
X
Main Memory
U
BISD
BIST
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Wrapper
Fig. 2. The inter-tier redundancy architecture.
Data out
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Fault Injection for Memory Dies
BIST & BISR Procedures
Defect & fault information March Algorithm Memory Specifications RA Algorithm (ESP) Spare Element Organization
Die Classification
Fig. 3. 3D-IC stacking flow.
without yield loss. This will be very helpful for 3D integration of memories.
Maximal Matching for Stacking
Yield Evaluation
Fig. 5. Flow chart of the simulator.
4. Problem modeling for the die stacking flow As described in the previous section, when the pre-bond test and BISR flow are finished, each die is categorized into the four die sets and the values of NRC and NAC for each die are also stored. The maximum matching algorithm is performed only for the memory dies in GDAC and BDRC. Definition. A graph G(V, E) (or G(V1, V2, E)) is called a bipartite graph if its vertex set V is the disjoint union of set V1 and V2 and every edge in E has the form (v1, v2), where v1 2 V1 and v2 2 V2 [12]. Let the die sets BDAC and GDAC be the vertex sets V1 and V2, respectively. Therefore, each node in the bipartite graph denotes a memory die. For each node in V1 (V2), a positive number is associated with it which denotes the value of NRC (NAC). Two nodes v1 2 V1 and v2 2 V2 are connected with an edge if the value associated with v1 is less than or equal to that in v2. These two nodes are said to be compatible. An example is shown in Fig. 4. The vertex sets V1 and V2 contain 5 vertices, respectively. The total number of edges is 18. Two dies in V1 and V2 can be stacked if an edge is connected between them. To increase the yield after stacking, we have to find the maximal matching pairs. Therefore, the DTD stacking problem is converted to a bipartite maximum matching problem. The complexity to solve this problem is proved to be O(V(V + E)) [13]. 5. Experimental results We have implemented a simulator to evaluate the effectiveness of the proposed BISR and die stacking flow. The flow chart of the simulator is shown in Fig. 5. As this figure shows, the simulation flow consists of the fault injection stage, the BIST and BISR stage, the Die classification stage, the maximal matching stage, and the yield evaluation stage. In the fault injection stage, we can specify
the memory specifications, the adopted March algorithms, and defect and fault information for the BIST module. We assume that the number of defects in the memory die is modeled by Poisson distribution. Although bulk defects are possible, we assume only spot defects here. Note that the manifestation of a defect may result in various fault patterns [14]. We collect eight fault patterns and classify them into three faulty types–faulty cell, faulty column, and faulty row (cluster faults are not considered for simplification) as shown in Fig. 6. For example, the type faulty_column consists of stuck-at-0, stuck-at-1 and random faults can be described as SA0, SA1, and random, respectively. With these fault patterns, defects are transformed to them according to the specified probability distributions. After that, our simulator can generate a faulty memory with the faults which can be detected by the different read operations of the adopted March algorithms. This is used to simulate the sequence of the faults detected by the BIST circuit which should be used for analysis of spare allocation in the following stage. During the BIST and BISR stage, the simulator performs the adopted March algorithms. After faulty cells are detected, the spare elements (defined by the user) can be used to repair them and the values of NAC and
Faulty_Cell
Faulty_Column
Faulty_Row
FP1
FP4
FP7
FP2
FP5
FP8 SAF 1 SAF 0
FP3 Fig. 4. An example bipartite graph.
FP6 Fig. 6. The mapped fault types.
Random Fault
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Fig. 7. Parameter setting for the simulator’s graphical user interface (GUI).
NRC for each die can be determined after finishing this step. We assume that the March C algorithm is used for the BIST circuit and the ESP (Essential Spare Pivoting) algorithm [16] is used for redundancy analysis. The next step is the die classification stage. According to the values of NAC and NRC, the memory dies are classified into four die sets–GDNC, GDAC, BDRC, and BDERC. The dies in BDERC are discarded directly and not used for stacking. The conventional maximum matching algorithm is performed for dies in GDAC and BDRC. The remained dies in GDAC are randomly stacked with dies in GDNC. After the matching stage, we can evaluate the yield after die stacking.
To simplify the yield analysis, two assumptions are made first. First, we assume all failures on the memory chip are the result of spot defects. Spot defects are in contrast to global defects, which affect complete sections of a chip or wafer. Second, any single spot defect will result in the chip being inoperative unless some types of redundancy are included. Let Y0 denote the yield the non-redundant memory array and PESP be the probability of successful allocation (repair rate) with the adopted ESP algorithm. Then, the yield YESP can be expressed as follows
Table 1 Effective yield after stacking (512 1024 32).
Table 3 Effective yield after stacking (1024 1024 32).
1R1C 1R2C 1R3C 2R1C 2R2C 2R3C 3R1C 3R2C 3R3C
60% SCFs, 20% FRs, and 20% FCs
100% SCFs Intra-tier redundancy
Inter-tier redundancy
Intra-tier redundancy
Inter-tier redundancy
3.0 26.2 77.0 25.6 76.6 97.9 97.6 100 100
3.0 27.9 100 28.3 99.7 100 97.6 100 100
2.0 17.4 44.2 17.4 42.7 58.5 39.5 57.4 65.5
2.0 19.3 58.9 19.0 60.5 66.7 55.1 72.2 77.1
Intra-tier redundancy
Inter-tier redundancy
Intra-tier redundancy
Inter-tier redundancy
3 28.2 78 24 76.2 98.5 76.1 98.1 100
3 31.2 100 26.4 100 100 100 100 100
2.8 19.1 55.8 16.4 42.6 55.7 40.9 55.0 67.2
3 21.9 68.1 18.0 57.3 69.0 55.0 75.8 77.7
1R1C 1R2C 1R3C 2R1C 2R2C 2R3C 3R1C 3R2C 3R3C
60% SCFs, 20% FRs, and 20% FCs
Table 4 Effective yield after stacking (1024 1024 32).
Table 2 Effective yield after stacking (512 1024 32).
Memory size 1024 1024 32, unit (%)
Memory size 512 1024 32, unit (%)
1R1C 1R2C 1R3C 2R1C 2R2C 2R3C 3R1C 3R2C 3R3C
Y0 is basically the proportion of dies in GDNC and GDAC. However, if inter-die redundancy is used, the dies in BDRC can be reused for
Memory size 1024 1024 32, unit (%)
Memory size 512 1024 32, unit (%) 100% SCFs
Y ESP ¼ Y 0 þ ð1 Y 0 ÞP ESP :
60% SCFs and 40% FRs
60% SCFs and 40% FCs
60% SCFs and 40% FRs
60% SCFs and 40% FCs
Intra-tier redundancy
Inter-tier redundancy
Intra-tier redundancy
Inter-tier redundancy
Intra-tier redundancy
Inter-tier redundancy
Intra-tier redundancy
Inter-tier redundancy
1.8 14.6 26.7 19.2 40.5 44.00 54.7 61.1 63.1
1.8 16.4 29.8 22.2 45.6 50.5 61.1 63.1 67.5
2.0 21.1 58.7 14.4 42.7 65.3 25.5 43.7 63.2
2.0 22.9 79.6 15.4 56.1 99.9 35.1 69.5 100
2.1 14.3 27.2 18.6 41.0 61.6 56.4 63.7 65.6
2.1 15.7 41.8 20.7 45.7 68.8 63.5 67.3 70.7
2.0 21.1 58.7 14.2 41.6 62.8 26.2 45.1 64.8
2.0 22.9 79.6 15.5 56.3 100 35.7 73.3 100
1R1C 1R2C 1R3C 2R1C 2R2C 2R3C 3R1C 3R2C 3R3C
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100% 90% 80% 70%
100% SCF Intra-Tier Redundnacy (512 × 1024 × 32) Inter-Tier Redundancy (512 × 1024 × 32) Intra-Tier Redundnacy (1024 × 1024 × 32) Inter-Tier Redundancy (1024 × 1024 × 32)
60% 50% 40% 30% 20% 10% 0% 1R/1C
1R/2C
1R/3C
2R/1C
2R/2C
2R/3C
3R/1C
3R/2C
3R/3C
Fig. 8. The comparison of two sizes in 100% SCFs.
stacking with dies in GDAC. Moreover, according to the proposed die stacking algorithm, the effective yield can be improved significantly. The graphic user interface (GUI) of the simulator is shown in Fig. 7. Two memory sizes are used in our simulation–512 1024 32 and 1024 1024 32. The average number of defects injected is 4. Four different fault distributions are applied for the simulator. The first fault distribution is 100% single cell faults (SCFs). The second fault distribution is 60% SCFs, 20% faulty rows (FRs), and 20% faulty columns (FCs). The third fault distribution is 60% SCFs and 40% FRs. The final fault distribution is 60% SCFs and 40% FCs. These fault profiles can be verified from the foundry data provided in [19]. Simulation results for the memory size 512 1024 32 are shown in Tables 1 and 2. The term xRyC denotes that x spare rows and y spare columns are added as redundancy. The column ‘‘Intra-Tier Redundancy’’ denotes that the redundancy in the memory die will not be reused by the memory die stacked with it. Therefore, the memory dies in BDRC and BDERC will all be discarded. The column ‘‘Inter-Tier Redundancy’’ denotes that each die’s redundancy can be reused by the memory die stacked with it. That is, the stacking flow shown in Fig. 3 is used. From these tables we can see that if more redundancies are added, the effective yield will increase for either the inter-tier or intra-tier redundancy mechanism. However, the yield for the inter-tier redundancy is always higher than that of the intra-tier redundancy. Moreover, if the yield of intra-tier redundancy is very low (e.g., 3%) or very high (e.g., 100%), the yield will not be further increased if inter-tier redundancy is used instead. However, these two situations occur not often in practical process technology and stacking flow. For the average yield level, (70–80%), the yield improvement by inter-tier redundancy is significant. This situation is practical since significant yield ramp-up can be achieved by this technique. We can also find that if the proportion of FRs (FCs) increases, the yield will be higher if more spare rows (columns) are added. The same observations can be found from Tables 3 and 4 for the memory size 1024 1024 32. The comparisons of the effective yield after stacking are shown in Fig. 8. As shown in this figure, if a large amount of redundancy is added (e.g., 3R3C), the yield improvement is almost negligible. The same situation also occur for very low yield dies (e.g., 1R1C). More yield improvement can be found for average yield levels such as 1R3C, 2R2C, and 3R1C. 6. Conclusions In this paper, a novel BISR and stacking flow based on inter-tier redundancy technique was proposed for yield improvement of 3D memories. The redundancy exclusively added in a memory tier can
also be reused to repair defects in the other memory tier after the bonding process. Therefore, we can further increase the yield of 3D memories after stacking. The stacking procedure by using inter-tier redundancy can be modeled as a bipartite maximal matching problem and conventional algorithms can be used to solve it. A simulator was also implemented to verify the effectiveness of the proposed techniques. Experimental results show that the proposed BISR and stacking flow can improve the yield significantly. References [1] The International Technology Roadmap for Semiconductors. SIA; 2007. [2] Bhavsar DK. An algorithm for row-column self-repair of RAMs and its implementation in the alpha 21264. In: Proc Int’l Test Conf; September 1999. p. 311–18. [3] Ilyoung I Kim, Zorian Y, Komoriya G, Pham H, Higgins FP, Lewandowski JL. Built In Self Repair for Embedded High Density SRAM. In: Proc Int’l Test Conf; October 1998. p. 1112–9. [4] Huang WK, Shen YH, Lombrardi F. New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement. IEEE Trans Comput Aided Des 1990;9(3):323–8. [5] Horiguchi M, Etoh J, Aoki M, Itoh K, Matsumoto T. A flexible redundancy technique for high-density DRAM’s. IEEE J Solid-State Circuits 1991;26(1). [6] Mazumder P, Jih YS. A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits. IEEE Trans Comput Aided Des 1993;12(1). [7] Kim HC, Yi DS, Park JY, Cho CH. A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies. In: Proc Int’l Conf on VLSI and CAD; October 1999. p. 602–5. [8] Lu JQ. 3-D Hyperintegration and packaging technologies for micro-nano systems. Proc IEEE 2009;97(1):18–30. [9] Reda S, Smith G, Smith L. Maximizing the functional yield of wafer-to-wafer 3D integration. IEEE Trans VLSI Syst 2009;17(9):1352–7. [10] Lu SK, Hsu CH, Tsai YC, Wang KH, Wu CW. Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. IEEE Trans VLSI Syst 2006;14(1):31–42. [11] Deng LM, Wang TC, Wu CW. An enhanced SRAM BISR design with reduced timing penalty. In: Proc 15th Asian Test Symp (ATS), Fukuoka, Japan; November 2006. p. 25–30. [12] Levitin A. Introduction to the design & analysis of algorithms. Addison Wesley; 2006. [13] Mchugh JA. Algorithm graph theory. Englewood Cliffs, NJ: Prentice-Hall; 1990. [14] Cheng KL, Wang CW, Lee JN, Chou YF, Huang CT. FAME: a fault-pattern based memory failure analysis framework. In: Proc Int’l Conf on Computer Aided Design; November 2003. p. 595–8. [15] Chou YF, Kwai DM, Wu CW. Yield enhancement by bad-die recycling and stacking with through-silicon vias. IEEE Trans VLSI Systems 2011;19(8): 1346–56. [16] Huang CT, Wu CF, Li JF, Wu CW. Built-in redundancy analysis for memory yield improvement. IEEE Trans Rel 2003;52:386–99. [17] Puttaswamy K et al. 3D-integrated SRAM components for high-performance microprocessors. IEEE Trans Comput 2009;58(10):1369–81. [18] Tauuli M, Hamdioui S. Layer redundancy based yield improvement for 3D wafer-to-wafer stacked memories. In: Proc European Test Symp; May 2011. p. 45–50. [19] Segal J, Jee A, Lepejian D, Chu B. Using electrical bitmap results from embedded memory to enhance yield. IEEE Des Test Comput 2001:28–39. [20] Lu SK, Yang CL, Hsiao YC, Wu CW. Efficient BISR techniques for embedded memories considering cluster faults. IEEE Trans VLSI Syst 2010;18(2):184–93.