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Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET
Superlattices and Microstructures 85 (2015) 149–155
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET K.P. Pradhan a,⇑, P.K. Sahu a, D. Singh a, L. Artola b, S.K. Mohapatra a a b
Nano Electronics Laboratory, Department of Electrical Engineering, National Institute of Technology (NIT), Rourkela 769008, Odisha, India ONERA, 31055 Toulouse, France
a r t i c l e
i n f o
Article history: Received 2 April 2015 Received in revised form 23 May 2015 Accepted 26 May 2015 Available online 27 May 2015 Keywords: Double material gate oxide (DMGO) Silicon–germanium on insulator (SGOI) Charge plasma Dual insulator (DI) ZTC point Double gate (DG)
a b s t r a c t A novel device named charge plasma based doping less double material gate oxide (DMGO) silicon–germanium on insulator (SGOI) double gate (DG) MOSFET is proposed for the first time. The fundamental objective in this work is to modify the channel potential, electric field and electron velocity for improving leakage current, transconductance (gm) and transconductance generation factor (TGF). Using 2-D simulation, we exhibit that the DMGO-SGOI MOSFET shows higher electron velocity at source side and lower electric field at drain side as compare to ultra-thin body (UTB) DG MOSFET. On the other hand DMGO-SGOI MOSFET demonstrates a significant improvement in gm and TGF in comparison to UTB-DG MOSFET. This work also evaluates the existence of a biasing point i.e. zero temperature coefficient (ZTC) bias point, where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performance metrics are also subjected to extensive analysis. This further validates the reliability of charge plasma DMGO SGOI MOSFET and its application opportunities involved in designing analog/RF circuits for a wide range of temperature applications. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction The ultra-thin body (UTB) [1] MOSFETs is one of the emerging devices for further scaling down. As the body thickness is less, the leakage current path is eradicated and the thin channel is perfectly controlled by gate, which continue to provide excellent scaling capacity [2,3]. Similarly, for getting higher drive current and higher mobility, silicon–germanium (SiGe) material in the channel has been suggested from past several years [4–6]. However, the SiGe material also suffers from undesirable characteristics with increased Ge content, which is the main contributor for short channel effects (SCEs) [7]. In the same way, with miniaturization of transistor towards nanometer regime, many unwanted effects have become more prominent and causes poor performances [8]. In earlier studies, many researchers [9–12] had demonstrated that the device performance can be enhanced in terms of higher breakdown voltage and higher electric field peak by changing the shape of buried oxide (BOX) region in partial SOI technology. Here, in this analysis we have evaluated the device performance by focusing on gate oxide materials in DG platform. So, to get rid of from the above said problems, we have proposed one novel device i.e., charge plasma based doping less DMGO-SGOI MOSFET. Two different gate oxide materials are considered to modify the potential and field profiles. Similarly, ⇑ Corresponding author. E-mail addresses: [email protected] (K.P. Pradhan), [email protected] (P.K. Sahu), [email protected] (D. Singh), [email protected] (L. Artola), [email protected] (S.K. Mohapatra). http://dx.doi.org/10.1016/j.spmi.2015.05.034 0749-6036/Ó 2015 Elsevier Ltd. All rights reserved.
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for higher mobility and drive current, the SiGe material is chosen as channel material. Using 2-D simulation [13], we have analyzed and presented that DMGO-SGOI MOSFET is superior in performance in comparison to its counterpart UTB DG MOSFET. It is also essential to analyze the device reliability and it’s sustainability towards temperature (T) variation. From previous investigations [14,15], it is desirable to bias the digital and analog circuits meant for low and high temperature applications at a point where the I–V characteristics show a little or no variation with respect to temperature. This point is typically known as zero temperature point (ZTC) point [16]. Mohapatra et al. [15] and Sahu et al. [14] have identified the ZTC bias point for single gate (SG), double gate (DG), and gate stack double gate (GS-DG) ultra-thin body (UTB) silicon on insulator (SOI) MOSFETs. This paper reveals a systematic analysis of ZTC point to examine the reliability issues over a wide temperature range (25–225 °C) of the doping less DMGO SGOI MOSFET. Section 2 describes the device, which includes all the dimensions, materials and doping concentrations with the models and methods activated for numerical simulation. Section 3 comprises of two subsections, from which the first one compares various performance metrics including the SCEs like Ion, Ioff, Ion/Ioff ratio, and also important analog/RF figures of merit (FOMs) such as gm, Cgg, fT of the doping less DMGO-SGOI MOSFET with the UTB DG-MOSFET. And the second subsection examines the reliability of the doping less DMGO-SGOI MOSFET subject to temperature variations. Finally, the concluding remarks are included in Section 4.
2. Doping less DMGO-SGOI structure and simulation The schematic simulated DMGO-SGOI and UTB-DG MOSFET structures are shown in Fig. 1(a) and (b) respectively. The silicon channel is surrounded above and below by two different material of oxide, SiO2 (source side) and HfO2 (drain side) [17], with 1:1 ratio and physical oxide thickness of 0.9 nm. The gate metal with work-function of 4.6 eV is assumed. The SiGe channel material with length 20 nm and a fixed width of 1 lm has been considered. Source and drain extensions are 40 nm with contacts placed vertically. The source, drain, and channel are formed with intrinsic silicon film with gi = 1015 cm3. The concept of doping less is adopted from Kumar and Nadda [18]. For fulfillment of the requirements for doping less concept, the work function of source/drain and silicon body thickness (tSi) is considered as 3.9 eV and 10 nm respectively [19,20]. According to ITRS the drain bias has been fixed at VDD = 0.7 V [21]. In the simulation, the inversion-layer Lombardi constant voltage and temperature (CVT) mobility model has been used. The Shockley–Read–Hall (SRH) generation and recombination parameters simulate the leakage currents. The model Fermi–Dirac uses a Rational Chebyshev approximation that gives results close to the exact values. The Auger recombination models for minority carrier recombination have been used [13]. The validity of the simulator has been verified by comparing its results with previous literature data. From Fig. 1(c), it can be noted that our simulation results are in great agreement with [4]. The major issue faced by conventional doped devices is random dopant fluctuations (RDF), which degrades the device performances in terms of on–off ratio and threshold voltage variation. Another concern of
Fig. 1. Cross sectional view of (a) Doping less DMGO-SGOI MOSFET. (b) UTB-DG MOSFET. (c) Comparison of ID with respect to VGS of [4] with simulation.
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doping devices is thermal budget because of the ion implantation and expensive annealing techniques. So, this proposed doping less device can successfully eliminate the above said problems [19,20]. 3. Results and discussion 3.1. Performance measure of doping less DMGO-SGOI The surface potential, electron velocity and electric field along the channel for doping less DMGO SGOI and UTB DG MOSFET with VDS = 0.7 V and VGS = 0–0.7 V are shown in Fig. 2. In all figures, the position along the channel (from the Source to the Drain) is plotted in the x-axis direction where ‘‘0.055 lm’’ indicates the center of the channel. The difference in the value of permittivity for the two gate oxide materials in the DMGO SGOI device results in an additional peak which influences the transport phenomena. Fig. 2(a) describes electric field of DMGO-SGOI MOSFET by virtue of different gate oxide ratios as 1:2, 1:1, and 2:1 i.e., 5 nm:15 nm, 10 nm:10 nm, and 15 nm:5 nm of SiO2:HfO2 respectively to analyze the ratio effect on device performance. As per the figure, the peak position of the electric field is shifted towards the source side or middle of the channel or drain side, according to the junction point of the two gate oxides. Hence, the rest of the investigations are carried out by contemplating the ratio of SiO2:HfO2 as 1:1 i.e., 10 nm:10 nm. Fig. 2(b) shows the surface potential of the device. This parameter can be controlled by adjusting the work function of the gate metal and the doping concentration, which consequently leads to control the threshold voltage. The increase in surface potential at the abrupt doping profile junction for the DMGO SGOI device, reduces the subthreshold leakage current. Fig. 2(c) demonstrates the electric field of doping less DMGO SGOI MOSFET and compares with the UTB DG MOSFET. The peak value of the electric field near the source side is more in case of DMGO SGOI MOSFET as compare to UTB DG counterpart, which impact the carrier transport efficiency and it is somewhat reduced at the drain side, resulting in smaller hot carrier effect (HCE). Fig. 2(d) presents the electron velocity for both device cases. Similarly, the additional peak can also be observed in case of DMGO SGOI MOSFET which enhances the electron mobility of the device. Fig. 3(a) and (b) represents the ID–VGS (log scale) and gm–VGS characteristics respectively. Ioff is maintained at nearly constant value of both device cases at VDS = 0.1 V, for a better comparison in analog/RF performances [22], which can be observed from the inset figure of Fig. 3(a) and it is in the range between 1010 A/lm and 1011 A/lm. Transconductance (gm = oID/oVGS) is one of the important parameter as far as analog performance of the device is concerned because it determines the transconductance generation factor (TGF = gm/ID) and cut-off frequency (fT = gm/2pCgg). From Fig. 3(b), a higher gm can also be achieved by DMGO-SGOI MOSFET which is desirable. This is due to the electron velocity and mobility which consequently increases the on current.
Fig. 2. Simulated parameters for UTB-DG and DMGO-SGOI MOSFET along the channel position (from the Source to the Drain, from the left to the right) at VDS = 0.7 V. (a) Electric field for different gate oxide ratios (SiO2:HfO2) of DMGO-SGOI MOSFET. (b) Surface potential. (c) Electric field. (d) Electron velocity.
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Fig. 3. Different characteristics comparison among UTB-DG and doping less DMGO-SGOI. (a) Drain current in log scale as a function of gate voltage. (b) Transconductance as a function of gate voltage.
Fig. 4(a), the variation of TGF can be observed for both device cases. The ideal value of TGF is limited to 40 V1 at minimum SS of 60 mV/decade of the device. An improvement in TGF can be achievable from our proposed device. This improvement is due to the higher value of gm. Never the less, availability of few challenges are trivial even if a long list of advantages exist. The major issue of concern for this proposed device is the total gate capacitance which should be carefully tackled. This degradation is due to the higher dielectric constant of partial gate oxide. 3.2. Reliability of doping less DMGO-SGOI Several physical parameters of the transistor are affected by variation of temperature. This effect changes the electrical behaviour of the device. The carrier mobility decreases with increase in temperature as (1).
n T To
lðTÞ ¼ lðT o Þ
ð1Þ
where n is an exponent which varies from 1.6 to 2.4 [23]. The dependency of threshold voltage (Vth) in the SOI MOSFETs is inversely proportional to the temperature range (25–225 °C) [24]. Fig. 5(a) shows the variations of ID with VGS as a parameter at different bias temperatures for doping less DMGO SGOI MOSFET. The drain current ID is influenced by two terms i.e. channel mobility l and threshold voltage Vth as (2) [14]
ID ðTÞ /
lðTÞ½V GS V th ðTÞ
ð2Þ
The mobility term of (2) forces ID to decrease, whereas the [VGS–Vth] term increases ID with increase in temperature. But the behaviour of ID with temperature shows opposite effect at a fixed gate bias voltage. The effect of two controlling terms of (2) are nullified at a fixed value of bias voltage, which is defined as ZTC bias point. The ZTC point of drain current ðZTC IDS ¼ 0:6475 VÞ, which can be clearly distinguishable from the inset figure of Fig. 5(a). Fig. 5(b) describes the gm variation with VGS for different temperature (T). In the gm–VGS plot, at VGS < Vth, the channel is weakly inverted and ID is mainly due to diffusion. Similarly at VGS > Vth the drain current ID is due to drift. Both the transport mechanisms have the same weight and ID becomes temperature independent at a particular VGS [25]. These two phenomena
Fig. 4. Different parameters comparison among UTB-DG and doping less DMGO-SGOI. (a) Transconductance generation factor (TGF) with different VGS. (b) Total gate capacitance (Cgg) as a function of VGS.
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Fig. 5. (a) Drain Current (ID) as a function of VGS with variation of Temperature (T) for doping less DMGO-SGOI MOSFET. (b) Transconductance (gm) as a function of VGS for different Temperature (T) values of doping less DMGO-SGOI MOSFET.
compensate each other to give rise to a ZTC bias point for gm. From the Fig. 5(a) and (b), we can conclude that the value of transconductance ZTC point (0.385 V) is lower than the drain current ZTC bias point (0.6475 V). The ZTC IDS and ZTC gm bias points are two important FOMs in analog circuit design for wide range of temperature applications. Moreover, the ZTC points are usually affected by process variations. Hence, depending upon the nature of applications, ZTC IDS and ZTC gm bias conditions are chosen accordingly [14]. Fig. 6 presents a combined plot for all the four important parameters which includes the variation of Ion, Ioff, Ion/Ioff, ratio, and Vth for different temperatures. With increase in temperature the carrier mobility decreases according to (1). As a matter of fact, the degradation of on state current (Ion) arises. This can be observed from Fig. 6(a), the Ion is very high for lower T and started decaying with an exponential manner as T increases. However, due to the degradation of threshold voltage with increase in T will enhances the off state leakage current, which can be examined from Fig. 6(b). The Ion/Ioff ratio is an important parameter for switching applications. It should be marginally high for a good switch. From Fig. 6(c), lower T provides supreme on–off ratio as compare to higher T values. This is evident from the nature of Ion and Ioff. Fig. 6(d) shows the behaviour of Vth for wide range of temperature variation (25–225 °C). The sensitivity of threshold voltage on temperature is quite obvious and follows as predicted.Fig. 7(a) and (b) describes the sensitivity of AC parameters like total gate capacitance (Cgg) and cut-off frequency (fT) towards temperature variation of doping less DMGO-SGOI MOSFET. The capacitances between each pair of electrode for all devices are calculated by a single AC frequency (1 MHz) when a DC ramp voltage swing from 0 V to 0.7 V is applied. From the Fig. 7(a), it is clear that there exists gate-to-gate capacitance ZTC point ðZTC C gg ¼ 0:245 VÞ. In sub-threshold region (below ZTC point), the value of Cgg is more for higher T and it gradually decreases as T decreases. However, the reverse situations have been observed in the super threshold region (above ZTC point). Cut-off frequency (fT) plays a vital role in evaluating the RF performance of the device which is plotted in Fig. 7(b). Generally, fT is the frequency at which the current gain is unity [26].
fT ¼
gm 2pC gg
ð3Þ
where gm, and Cgg are the transconductance, and the total gate capacitance. At low temperature, the improvement of cut-off frequency fT is due to steep increase in mobility in turn immense gm (refer Fig. 5(b)) and a crouched Cgg (refer Fig. 7(a)). In addition, it reveals the existence of ZTC bias point for cut-off frequency ðZTC f T ¼ 0:385 VÞ of the proposed doping less DMGO SGOI MOSFET.
Fig. 6. (a) On state current (Ion), (b) off state current (Ioff), (c) on–off current ratio (Ion/Ioff), (d) threshold voltage (Vth) as a function of temperature for doping less DMGO-SGOI MOSFET.
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Fig. 7. (a) Total gate capacitance (Cgg) as a function of VGS with different values of operating temperature (T) for doping less DMGO-SGOI MOSFET. (b) Cutoff frequency (fT) as a function of VGS with different values of operating temperature (T) for doping less DMGO-SGOI MOSFET.
4. Conclusion To improve the SCEs as well as the analog performance, we have proposed a novel structure i.e., charge plasma based doping less DMGO-SGOI MOSFET. According to our results, the proposed device shows significant improvements in electric field, electron velocity, leakage current, gm and TGF as compare to UTB DG MOSFET. The proposed one will also come up with a solution to successfully eliminate the doping related issues which are usually faced. To ensure the device reliability, we have performed and evaluated the temperature compensation point (TCP)/ZTC point over various parameters of the device by considering wide range of temperature (25–225 °C) variation. From the conferred results, the existence of TCP/ZTC point for ID, gm, Cgg, and fT can be identified, which will help to operate the device. Finally, the proposed one will show excellent performance in terms of Ion, Ioff, gm, fT while operate in low temperatures. This facilitates the circuit designers to choose our device in low temperature and low power environment.
References [1] Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, C. Hu, Ultra-thin body SOI MOSFET for deep-sub-tenth micron era, in: Electron Devices Meeting, 1999. IEDM’99. Technical Digest. International, 1999, pp. 919–921. [2] F.D.J., S.P. Wong, H.S. P., Devices design considerations for double-gate, ground-plane, and single-gate ultra thin SOI MOSFETs at the 25 nm channel length generation, IEDM Tech. 1998, pp. 407–410. [3] A.A. Orouji, S. Heydari, M. Fathipour, Double step buried oxide (DSBO) SOI-MOSFET: a proposed structure for improving self-heating effects, Phys. E Low-Dimens. Syst. Nanostruct. 41 (9) (2009) 1665–1668. [4] Z. Cheng, A.J. Pitera, M.L. Lee, J. Jung, J.L. Hoyt, D.A. Antoniadis, E.A. Fitzgerald, Fully depleted strained-SOI n-and p-MOSFETs on bonded SGOI substrates and study of the SiGe/BOX interface, Electron Device Lett. IEEE 25 (3) (2004) 147–149. [5] G.H. Wang, E.-H. Toh, A. Du, G.-Q. Lo, G. Samudra, Y.-C. Yeo, Strained silicon–germanium-on-insulator n-MOSFET with embedded silicon source-anddrain stressors, Electron Device Lett. IEEE 29 (1) (2008) 77–79. [6] T. Tezuka, N. Sugiyama, S. Takagi, Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction, Appl. Phys. Lett. 79 (12) (2001) 1798–1800. [7] C.K. Maiti, Applications of Silicon–Germanium Heterostructure Devices, CRC Press, 2001. [8] P.K. Sahu, S.K. Mohapatra, K.P. Pradhan, P.K. Sahu, S.K. Mohapatra, K.P. Pradhan, Impact of downscaling on analog/RF performance of sub-100 nm GSDG MOSFET, J. Microelectron. Electron. Compon. Mater. 44 (2) (2014) 119–125. [9] A.A. Orouji, S.E.J. Mahabadi, P. Keshavarzi, A novel partial SOI LDMOSFET with a trench and buried P layer for breakdown voltage improvement, Superlattices Microstruct. 50 (5) (2011) 449–460. [10] B. Duan, B. Zhang, Z. Li, New thin-film power MOSFETs with a buried oxide double step structure, Electron Device Lett. IEEE 27 (5) (2006) 377–379. [11] S.E.J. Mahabadi, A.A. Orouji, P. Keshavarzi, S. Rajabi, H.A. Moghadam, M.I.P. Haghighi, A novel step buried oxide partial SOI LDMOSFET with triple drift layer, in: Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), 2011 International Conference on, 2011, pp. 174–177. [12] S.E.J. Mahabadi, A.A. Orouji, P. Keshavarzi, H.A. Moghadam, A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage, Semicond. Sci. Technol. 26 (9) (2011) 95005. [13] http://www.synopsys.com/, Sentaurus TCAD User’s Manual, in: Synopsys Sentaurus Device, pp. 191–403. [14] P.K. Sahu, S.K. Mohapatra, K.P. Pradhan, Zero temperature-coefficient bias point over wide range of temperatures for single-and double-gate UTB-SOI n-MOSFETs with trapped charges, Mater. Sci. Semicond. Process. 31 (2015) 175–183. [15] S.K. Mohapatra, K.P. Pradhan, P.K. Sahu, Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: an influence to key performance metrics, Superlattices Microstruct. 78 (2015) 134–143. [16] Z. Prijic´, Z. Pavlovic´, S. Ristic´, N. Stojadinovic´, Zero-temperature-coefficient (ZTC) biasing of power VDMOS transistors, Electron. Lett. 29 (5) (1993) 435– 437. [17] S.K. Mohapatra, K.P. Pradhan, P.K. Sahu, Effect of channel and gate engineering on Double Gate (DG) MOSFET-A comparative study, in: Emerging Electronics (ICEE), 2012 International Conference on, 2012, pp. 1–3. [18] M.J. Kumar, K. Nadda, Bipolar charge-plasma transistor: a novel three terminal device, Electron Devices, IEEE Trans. 59 (4) (2012) 962–967. [19] M.J. Kumar, S. Janardhanan, Doping-less tunnel field effect transistor: Design and investigation, Electron Devices, IEEE Trans. 60 (10) (2013) 3285– 3290. [20] C. Sahu, J. Singh, Charge-plasma based process variation immune junctionless transistor, IEEE Electron Device Lett. 35 (3) (2014) 411–413. [21] The International Technology Roadmap for Semiconductors, 2013. [22] S.K. Mohapatra, K.P. Pradhan, L. Artola, P.K. Sahu, Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET, Mater. Sci. Semicond. Process. 31 (2015) 455–462. [23] S.M. Sze, Physics of Semiconductor Devices, third ed., John Wiley and Sons Inc., 2009.
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Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET K.P. Pradhan a,⇑, P.K. Sahu a, D. Singh a, L. Artola b, S.K. Mohapatra a a b
Nano Electronics Laboratory, Department of Electrical Engineering, National Institute of Technology (NIT), Rourkela 769008, Odisha, India ONERA, 31055 Toulouse, France
a r t i c l e
i n f o
Article history: Received 2 April 2015 Received in revised form 23 May 2015 Accepted 26 May 2015 Available online 27 May 2015 Keywords: Double material gate oxide (DMGO) Silicon–germanium on insulator (SGOI) Charge plasma Dual insulator (DI) ZTC point Double gate (DG)
a b s t r a c t A novel device named charge plasma based doping less double material gate oxide (DMGO) silicon–germanium on insulator (SGOI) double gate (DG) MOSFET is proposed for the first time. The fundamental objective in this work is to modify the channel potential, electric field and electron velocity for improving leakage current, transconductance (gm) and transconductance generation factor (TGF). Using 2-D simulation, we exhibit that the DMGO-SGOI MOSFET shows higher electron velocity at source side and lower electric field at drain side as compare to ultra-thin body (UTB) DG MOSFET. On the other hand DMGO-SGOI MOSFET demonstrates a significant improvement in gm and TGF in comparison to UTB-DG MOSFET. This work also evaluates the existence of a biasing point i.e. zero temperature coefficient (ZTC) bias point, where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performance metrics are also subjected to extensive analysis. This further validates the reliability of charge plasma DMGO SGOI MOSFET and its application opportunities involved in designing analog/RF circuits for a wide range of temperature applications. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction The ultra-thin body (UTB) [1] MOSFETs is one of the emerging devices for further scaling down. As the body thickness is less, the leakage current path is eradicated and the thin channel is perfectly controlled by gate, which continue to provide excellent scaling capacity [2,3]. Similarly, for getting higher drive current and higher mobility, silicon–germanium (SiGe) material in the channel has been suggested from past several years [4–6]. However, the SiGe material also suffers from undesirable characteristics with increased Ge content, which is the main contributor for short channel effects (SCEs) [7]. In the same way, with miniaturization of transistor towards nanometer regime, many unwanted effects have become more prominent and causes poor performances [8]. In earlier studies, many researchers [9–12] had demonstrated that the device performance can be enhanced in terms of higher breakdown voltage and higher electric field peak by changing the shape of buried oxide (BOX) region in partial SOI technology. Here, in this analysis we have evaluated the device performance by focusing on gate oxide materials in DG platform. So, to get rid of from the above said problems, we have proposed one novel device i.e., charge plasma based doping less DMGO-SGOI MOSFET. Two different gate oxide materials are considered to modify the potential and field profiles. Similarly, ⇑ Corresponding author. E-mail addresses: [email protected] (K.P. Pradhan), [email protected] (P.K. Sahu), [email protected] (D. Singh), [email protected] (L. Artola), [email protected] (S.K. Mohapatra). http://dx.doi.org/10.1016/j.spmi.2015.05.034 0749-6036/Ó 2015 Elsevier Ltd. All rights reserved.
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for higher mobility and drive current, the SiGe material is chosen as channel material. Using 2-D simulation [13], we have analyzed and presented that DMGO-SGOI MOSFET is superior in performance in comparison to its counterpart UTB DG MOSFET. It is also essential to analyze the device reliability and it’s sustainability towards temperature (T) variation. From previous investigations [14,15], it is desirable to bias the digital and analog circuits meant for low and high temperature applications at a point where the I–V characteristics show a little or no variation with respect to temperature. This point is typically known as zero temperature point (ZTC) point [16]. Mohapatra et al. [15] and Sahu et al. [14] have identified the ZTC bias point for single gate (SG), double gate (DG), and gate stack double gate (GS-DG) ultra-thin body (UTB) silicon on insulator (SOI) MOSFETs. This paper reveals a systematic analysis of ZTC point to examine the reliability issues over a wide temperature range (25–225 °C) of the doping less DMGO SGOI MOSFET. Section 2 describes the device, which includes all the dimensions, materials and doping concentrations with the models and methods activated for numerical simulation. Section 3 comprises of two subsections, from which the first one compares various performance metrics including the SCEs like Ion, Ioff, Ion/Ioff ratio, and also important analog/RF figures of merit (FOMs) such as gm, Cgg, fT of the doping less DMGO-SGOI MOSFET with the UTB DG-MOSFET. And the second subsection examines the reliability of the doping less DMGO-SGOI MOSFET subject to temperature variations. Finally, the concluding remarks are included in Section 4.
2. Doping less DMGO-SGOI structure and simulation The schematic simulated DMGO-SGOI and UTB-DG MOSFET structures are shown in Fig. 1(a) and (b) respectively. The silicon channel is surrounded above and below by two different material of oxide, SiO2 (source side) and HfO2 (drain side) [17], with 1:1 ratio and physical oxide thickness of 0.9 nm. The gate metal with work-function of 4.6 eV is assumed. The SiGe channel material with length 20 nm and a fixed width of 1 lm has been considered. Source and drain extensions are 40 nm with contacts placed vertically. The source, drain, and channel are formed with intrinsic silicon film with gi = 1015 cm3. The concept of doping less is adopted from Kumar and Nadda [18]. For fulfillment of the requirements for doping less concept, the work function of source/drain and silicon body thickness (tSi) is considered as 3.9 eV and 10 nm respectively [19,20]. According to ITRS the drain bias has been fixed at VDD = 0.7 V [21]. In the simulation, the inversion-layer Lombardi constant voltage and temperature (CVT) mobility model has been used. The Shockley–Read–Hall (SRH) generation and recombination parameters simulate the leakage currents. The model Fermi–Dirac uses a Rational Chebyshev approximation that gives results close to the exact values. The Auger recombination models for minority carrier recombination have been used [13]. The validity of the simulator has been verified by comparing its results with previous literature data. From Fig. 1(c), it can be noted that our simulation results are in great agreement with [4]. The major issue faced by conventional doped devices is random dopant fluctuations (RDF), which degrades the device performances in terms of on–off ratio and threshold voltage variation. Another concern of
Fig. 1. Cross sectional view of (a) Doping less DMGO-SGOI MOSFET. (b) UTB-DG MOSFET. (c) Comparison of ID with respect to VGS of [4] with simulation.
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doping devices is thermal budget because of the ion implantation and expensive annealing techniques. So, this proposed doping less device can successfully eliminate the above said problems [19,20]. 3. Results and discussion 3.1. Performance measure of doping less DMGO-SGOI The surface potential, electron velocity and electric field along the channel for doping less DMGO SGOI and UTB DG MOSFET with VDS = 0.7 V and VGS = 0–0.7 V are shown in Fig. 2. In all figures, the position along the channel (from the Source to the Drain) is plotted in the x-axis direction where ‘‘0.055 lm’’ indicates the center of the channel. The difference in the value of permittivity for the two gate oxide materials in the DMGO SGOI device results in an additional peak which influences the transport phenomena. Fig. 2(a) describes electric field of DMGO-SGOI MOSFET by virtue of different gate oxide ratios as 1:2, 1:1, and 2:1 i.e., 5 nm:15 nm, 10 nm:10 nm, and 15 nm:5 nm of SiO2:HfO2 respectively to analyze the ratio effect on device performance. As per the figure, the peak position of the electric field is shifted towards the source side or middle of the channel or drain side, according to the junction point of the two gate oxides. Hence, the rest of the investigations are carried out by contemplating the ratio of SiO2:HfO2 as 1:1 i.e., 10 nm:10 nm. Fig. 2(b) shows the surface potential of the device. This parameter can be controlled by adjusting the work function of the gate metal and the doping concentration, which consequently leads to control the threshold voltage. The increase in surface potential at the abrupt doping profile junction for the DMGO SGOI device, reduces the subthreshold leakage current. Fig. 2(c) demonstrates the electric field of doping less DMGO SGOI MOSFET and compares with the UTB DG MOSFET. The peak value of the electric field near the source side is more in case of DMGO SGOI MOSFET as compare to UTB DG counterpart, which impact the carrier transport efficiency and it is somewhat reduced at the drain side, resulting in smaller hot carrier effect (HCE). Fig. 2(d) presents the electron velocity for both device cases. Similarly, the additional peak can also be observed in case of DMGO SGOI MOSFET which enhances the electron mobility of the device. Fig. 3(a) and (b) represents the ID–VGS (log scale) and gm–VGS characteristics respectively. Ioff is maintained at nearly constant value of both device cases at VDS = 0.1 V, for a better comparison in analog/RF performances [22], which can be observed from the inset figure of Fig. 3(a) and it is in the range between 1010 A/lm and 1011 A/lm. Transconductance (gm = oID/oVGS) is one of the important parameter as far as analog performance of the device is concerned because it determines the transconductance generation factor (TGF = gm/ID) and cut-off frequency (fT = gm/2pCgg). From Fig. 3(b), a higher gm can also be achieved by DMGO-SGOI MOSFET which is desirable. This is due to the electron velocity and mobility which consequently increases the on current.
Fig. 2. Simulated parameters for UTB-DG and DMGO-SGOI MOSFET along the channel position (from the Source to the Drain, from the left to the right) at VDS = 0.7 V. (a) Electric field for different gate oxide ratios (SiO2:HfO2) of DMGO-SGOI MOSFET. (b) Surface potential. (c) Electric field. (d) Electron velocity.
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Fig. 3. Different characteristics comparison among UTB-DG and doping less DMGO-SGOI. (a) Drain current in log scale as a function of gate voltage. (b) Transconductance as a function of gate voltage.
Fig. 4(a), the variation of TGF can be observed for both device cases. The ideal value of TGF is limited to 40 V1 at minimum SS of 60 mV/decade of the device. An improvement in TGF can be achievable from our proposed device. This improvement is due to the higher value of gm. Never the less, availability of few challenges are trivial even if a long list of advantages exist. The major issue of concern for this proposed device is the total gate capacitance which should be carefully tackled. This degradation is due to the higher dielectric constant of partial gate oxide. 3.2. Reliability of doping less DMGO-SGOI Several physical parameters of the transistor are affected by variation of temperature. This effect changes the electrical behaviour of the device. The carrier mobility decreases with increase in temperature as (1).
n T To
lðTÞ ¼ lðT o Þ
ð1Þ
where n is an exponent which varies from 1.6 to 2.4 [23]. The dependency of threshold voltage (Vth) in the SOI MOSFETs is inversely proportional to the temperature range (25–225 °C) [24]. Fig. 5(a) shows the variations of ID with VGS as a parameter at different bias temperatures for doping less DMGO SGOI MOSFET. The drain current ID is influenced by two terms i.e. channel mobility l and threshold voltage Vth as (2) [14]
ID ðTÞ /
lðTÞ½V GS V th ðTÞ
ð2Þ
The mobility term of (2) forces ID to decrease, whereas the [VGS–Vth] term increases ID with increase in temperature. But the behaviour of ID with temperature shows opposite effect at a fixed gate bias voltage. The effect of two controlling terms of (2) are nullified at a fixed value of bias voltage, which is defined as ZTC bias point. The ZTC point of drain current ðZTC IDS ¼ 0:6475 VÞ, which can be clearly distinguishable from the inset figure of Fig. 5(a). Fig. 5(b) describes the gm variation with VGS for different temperature (T). In the gm–VGS plot, at VGS < Vth, the channel is weakly inverted and ID is mainly due to diffusion. Similarly at VGS > Vth the drain current ID is due to drift. Both the transport mechanisms have the same weight and ID becomes temperature independent at a particular VGS [25]. These two phenomena
Fig. 4. Different parameters comparison among UTB-DG and doping less DMGO-SGOI. (a) Transconductance generation factor (TGF) with different VGS. (b) Total gate capacitance (Cgg) as a function of VGS.
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Fig. 5. (a) Drain Current (ID) as a function of VGS with variation of Temperature (T) for doping less DMGO-SGOI MOSFET. (b) Transconductance (gm) as a function of VGS for different Temperature (T) values of doping less DMGO-SGOI MOSFET.
compensate each other to give rise to a ZTC bias point for gm. From the Fig. 5(a) and (b), we can conclude that the value of transconductance ZTC point (0.385 V) is lower than the drain current ZTC bias point (0.6475 V). The ZTC IDS and ZTC gm bias points are two important FOMs in analog circuit design for wide range of temperature applications. Moreover, the ZTC points are usually affected by process variations. Hence, depending upon the nature of applications, ZTC IDS and ZTC gm bias conditions are chosen accordingly [14]. Fig. 6 presents a combined plot for all the four important parameters which includes the variation of Ion, Ioff, Ion/Ioff, ratio, and Vth for different temperatures. With increase in temperature the carrier mobility decreases according to (1). As a matter of fact, the degradation of on state current (Ion) arises. This can be observed from Fig. 6(a), the Ion is very high for lower T and started decaying with an exponential manner as T increases. However, due to the degradation of threshold voltage with increase in T will enhances the off state leakage current, which can be examined from Fig. 6(b). The Ion/Ioff ratio is an important parameter for switching applications. It should be marginally high for a good switch. From Fig. 6(c), lower T provides supreme on–off ratio as compare to higher T values. This is evident from the nature of Ion and Ioff. Fig. 6(d) shows the behaviour of Vth for wide range of temperature variation (25–225 °C). The sensitivity of threshold voltage on temperature is quite obvious and follows as predicted.Fig. 7(a) and (b) describes the sensitivity of AC parameters like total gate capacitance (Cgg) and cut-off frequency (fT) towards temperature variation of doping less DMGO-SGOI MOSFET. The capacitances between each pair of electrode for all devices are calculated by a single AC frequency (1 MHz) when a DC ramp voltage swing from 0 V to 0.7 V is applied. From the Fig. 7(a), it is clear that there exists gate-to-gate capacitance ZTC point ðZTC C gg ¼ 0:245 VÞ. In sub-threshold region (below ZTC point), the value of Cgg is more for higher T and it gradually decreases as T decreases. However, the reverse situations have been observed in the super threshold region (above ZTC point). Cut-off frequency (fT) plays a vital role in evaluating the RF performance of the device which is plotted in Fig. 7(b). Generally, fT is the frequency at which the current gain is unity [26].
fT ¼
gm 2pC gg
ð3Þ
where gm, and Cgg are the transconductance, and the total gate capacitance. At low temperature, the improvement of cut-off frequency fT is due to steep increase in mobility in turn immense gm (refer Fig. 5(b)) and a crouched Cgg (refer Fig. 7(a)). In addition, it reveals the existence of ZTC bias point for cut-off frequency ðZTC f T ¼ 0:385 VÞ of the proposed doping less DMGO SGOI MOSFET.
Fig. 6. (a) On state current (Ion), (b) off state current (Ioff), (c) on–off current ratio (Ion/Ioff), (d) threshold voltage (Vth) as a function of temperature for doping less DMGO-SGOI MOSFET.
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Fig. 7. (a) Total gate capacitance (Cgg) as a function of VGS with different values of operating temperature (T) for doping less DMGO-SGOI MOSFET. (b) Cutoff frequency (fT) as a function of VGS with different values of operating temperature (T) for doping less DMGO-SGOI MOSFET.
4. Conclusion To improve the SCEs as well as the analog performance, we have proposed a novel structure i.e., charge plasma based doping less DMGO-SGOI MOSFET. According to our results, the proposed device shows significant improvements in electric field, electron velocity, leakage current, gm and TGF as compare to UTB DG MOSFET. The proposed one will also come up with a solution to successfully eliminate the doping related issues which are usually faced. To ensure the device reliability, we have performed and evaluated the temperature compensation point (TCP)/ZTC point over various parameters of the device by considering wide range of temperature (25–225 °C) variation. From the conferred results, the existence of TCP/ZTC point for ID, gm, Cgg, and fT can be identified, which will help to operate the device. Finally, the proposed one will show excellent performance in terms of Ion, Ioff, gm, fT while operate in low temperatures. This facilitates the circuit designers to choose our device in low temperature and low power environment.
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