Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

Accepted Manuscript Temperature dependency of Double Material Gate Oxide (DMGO) Symmetric Dual-k Spacer (SDS) Wavy FinFET K.P. Pradhan, Priyanka, P.K. Sahu PII:

S0749-6036(15)30290-1

DOI:

10.1016/j.spmi.2015.11.025

Reference:

YSPMI 4078

To appear in:

Superlattices and Microstructures

Received Date: 8 October 2015 Revised Date:

20 November 2015

Accepted Date: 22 November 2015

Please cite this article as: K. Pradhan, Priyanka P. Sahu Temperature dependency of Double Material Gate Oxide (DMGO) Symmetric Dual-k Spacer (SDS) Wavy FinFET, Superlattices and Microstructures (2015), doi: 10.1016/j.spmi.2015.11.025. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

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K P Pradhan, Priyanka, P K Sahu

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Temperature dependency of Double Material Gate Oxide (DMGO) Symmetric Dual-k Spacer (SDS) Wavy FinFET

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Nanoelectronics Lab, Electrical Department, National Institute of Technology (NIT), Rourkela 769008, Odisha, India. [email protected], [email protected], [email protected]

Abstract

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Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultrathin-body (UTB), wavy channel FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2 , and Hf O2 ) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion ), transconductance (gm ), transconductance generation factor (TGF), total gate capacitance (Cgg ), and cutoff frequency (fT ) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance. Keywords: Trigate FinFET, wavy FinFET, Dual-k spacer, Dual Material gate oxide (DMGO), ZTC point

Preprint submitted to Superlattices and Microstructures

November 20, 2015

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1. Introduction

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One of the greatest pertinent invention in the semiconductor era is 3-D FinFET technology, which has been greatly enabled the development of electronics industry. Major manufacturing companies like Intel and TSMC have adopted FinFET in their 22-nm technology node while others are expecting to use it in the near future [1] [2]. This advancement in technology facilitates highly energy efficient electronics and a long battery lifetime in both low power (LP) and high performance (HP) operating regions. According to the International Technology Roadmap for Semiconductors (ITRS) prediction, the 3-D topologies are here to drive the commercial industries up to 5-nm technology node [3] [4]. The only innovations in lower technology nodes will be incorporation of new channel materials as SiGe, Ge, GaAs, etc., which are CMOS compatible or in physical architecture like nanowires and nanotubes [5] [6]. Nowadays the market is more thoughtful regarding HP consumer applications and will continue for next subsequent 10 years. HP applications mainly target to achieve high current drivability as well as density instead of thinking about the off state leakage current. Hence, to achieve the HP computing operation, a novel transistor i.e., ITFET [7] [8] was first proposed by M athew et al. and Zhang et al. The device is further explored by F ahad et al. [4] [9] in order to optimize the UTB layer and they have renamed as Wavy FinFET. Wavy FinFET merges two different and emerging technologies in the same SOI platform, i.e., 2-D UTB MOSFET and 3-D FinFET. This gives many advantages like high integration density, maximum area efficiency, and also high performance with back biasing capability [4] [7] [8]. As wavy FinFETs are capable of providing more drive current without compromising the chip area due to its unique device architecture (addition of UTB layer renders to an increased path for current flow). Hence, it is roughly material independent and can be applicable for both organic transistors and thin film applications [9]. In this work, we have incorporated the symmetric dual-k spacer (SDS) in the underlap regions near S/D side of trigate wavy FinFET. Previously, the underlap FinFETs have already earned very good control over SCEs [10] [11]. Similarly, P al et al. [1] [2] have proposed that excellent control over channel and significant improvement in Ion and Iof f are achievable with contemplate dual-k spacers in the underlap region. This work quantitatively describes the effect of considering two different dielectric materials as gate oxide in the SDS wavy FinFET on various performance metrics. Perfor2

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mances like drive current (Ion ), transconductance (gm ), transconductance generation factor (T GF ), total gate capacitance (Cgg ), and cutoff frequency (fT ) for DMGO-SDS wavy FinFET are systematically listed and compared with SDS architecture. It is also essential to analyze the device reliability, and its feasibility towards temperature (T) variation. From previous investigations [12] [13], it is desirable to bias the digital, and analog circuits meant for low and hightemperature applications at a point where the I-V characteristics show a slight or no variation with temperature. This position is typically known as zero temperature point (ZTC) point [12]. Mohapatra et al. [14] [13] [15] and Sahu et al. [12] have identified the ZTC bias point for single gate (SG), double gate (DG), as well as FinFETs. This paper reveals a systematic analysis of ZTC point to examine the reliability issues over a wide temperature range (200 K-500 K) of the DMGO SDS FinFET. Section 2 describes the device, which includes all the dimensions, materials, and doping concentrations. Section 3 deals with the methods and models activated for numerical simulation. Section 4 comprises of two subsections, out of which, the first one compares various performance metrics including the static parameters like mobility, Ion , and also important analog/RF figures of merit (FOMs) such as gm , Cgg , fT of the DMGO-SDS wavy FinFET with the SDS wavy FinFET. And the second subsection examines the temperature dependency of the DMGO-SDS wavy FinFET subject to a broad range of temperature variation. Finally, Section 5 comprised the concluding remarks of this work.

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2. DMGO-SDS Wavy FinFET Architecture

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The 3-D bird view of SDS wavy FinFET and DMGO-SDS wavy FinFET architectures considered for this work are shown in Fig. 1(a) and (b) respectively. Fig. 1(c) illustrates the primary difference in the gate oxide materials among both SDS and DMGO-SDS device cases. The state-of-the-art wavy topology combines the 2-D UTB technology with advanced 3-D FinFET. It gives many advantages like high drive current, maximum area efficiency, and high packing density as reported in [8]. The concept of dual-k spacer in underlap regions of wavy topology is adopted from P al et. al. [2]. The key idea of this work is to insert two different dielectric materials like SiO2 (source side) and Hf O2 (drain side) as gate oxide [16] instead of considering a single oxide layer in the SDS wavy architecture. The ratio of two different gate oxides is considered as 1:1 with physical thickness of 0.9 nm. The electrical 3

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Figure 1: 3-D bird view of (a) symmetric dual-k spacer (SDS) wavy FinFET (D1) (b) DMGO-SDS wavy FinFET (D2) (c) 2-D view of difference between gate oxides among both devices.

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and physical parameters are calibrated to meet the ITRS specifications for 14-nm physical gate length [3] [17]. To avoid random dopant fluctuation (RDF) effect, the channel is lightly doped with 1 x 1016 cm−3 . All the design specifications used for simulation of SDS FinFET and DMGO-SDS wavy FinFETs are tabulated in Table 1. This work merges several technologies into a single SOI platform i.e., 2-D UTB + 3-D FinFET + spacer engineering + gate oxide technique. This will be powerful and pretty much advantageous topology for future HP consumer electronics.

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3. Simulation Methodology Extensive 3-D simulations are carried out by Sentaurus TCAD [18] to estimate the perspective benefits of the SHS Wavy FinFET over conventional FinFET. Along with the default carrier transport model, i.e., drift-diffusion model, the mobility model that takes account of doping, transverse field, and velocity saturation dependency are activated in the simulation. The density gradient based quantization model that determines the quantum confinement effect in UTBs and narrow fins are also considered in the simulation, and the high-k related mobility degradation effects are deal with Lombardi high-k 4

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Table 1: Parameters considered for simulation

Nomenclature

DMGO-SDS wavy FinFET

WF in

Fin Width

7 nm

HF in

Fin Height

HF in -UTB= 25 nm

Lg

Gate length

20 nm

UTB

Ultra thin body thickness

5 nm

Llk

Low-k spacer length (Si3 N4 )

1 nm

Lhk

High-k spacer length (Hf O2 )

4 nm

tox

Physical oxide thickness

0.9 nm

LT

Total device length

110 nm

WT

Total device width

32.2 nm

BOX

Buried oxide thickness

40 nm

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Parameters

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model. The current, voltage and charge for each electrode are calculated after every step of bias ramp through quasi-stationary manner. The validity of the simulator has been verified by comparing its results with previous literature data. From Fig. 2, it can be noted that our simulation results are in good agreement with [8].

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4. Results and Discussion

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4.1. performance measure of DMGO SDS wavy FinFET The electron mobility in the channel for both SDS and DMGO-SDS wavy FinFETs at VDS =50 mV, and 0.7 V is shown in Fig. 3(a). In this, the position along the channel is plotted in the x-axis (from the source to drain) where 0.055 µm shows the center of the channel. The difference in the material properties like lattice structure and permittivity for the two gate oxide materials will change the interfacial properties in case of DMGO-SDS wavy device results in an additional peak in the mobility, which further influences the transport phenomena. Hence, higher electron mobility can be achievable by considering DMGO architecture as compared to its SDS wavy counterpart. Similarly, the transfer characteristic (ID -VGS ), and transconductance 5

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Figure 2: Comparison of IDS with respect to VGS of reported results [8] with simulation

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(gm -VGS ) at VDS =50 mV, and 0.7 V for both device cases can be noticed from Fig. 3(b) and (c) respectively. It is observed from the ID -VGS characteristics that there is significant enhancement in ID for DMGO architecture. The DMGO-SDS wavy FinFET exhibits an approximately 1.36x times of improvement in ID from the SDS wavy FinFET. In a similar manner, the gm of the DMGO-SDS wavy FinFET is higher (around 1.73x) than the SDS wavy one. This increment in both ID , and gm is due to the higher mobility, and inversion charge modulation induced by gate fringing field as described by Koley et al. [19]. The transconductance generation factor (TGF=gm /ID ), and the output characteristics (ID − VDS ) for both configuration at low and high biasing conditions are examined in Fig. 4(a), and (b) respectively. From Fig. 4(a), there is a little improvement occurs in TGF for the DMGO-SDS one over SDS wavy FinFET. This improvement is because of the higher amount of enhancement in gm as compared to ID , which is already discussed in Fig. 3(b) and (c). The output characteristics (ID − VDS ) of the proposed DMGOSDS wavy FinFET are compared with SDS wavy FinFET at VGS = VDD /2 and VGS = VDD and presented in Fig. 4(b). The Ion (VGS = VDD ) is much higher in case of DMGO-SDS wavy FinFET than the SDS wavy FinFET, which is required for high switching speed of the device. In Fig. 5(a) and (b), the variation of total gate capacitance (Cgg ), and cutoff frequency (fT = gm /(2πCgg )) with respect to VGS for conventional FinFET and SHS Wavy FinFET are presented. Never the less, availability of 6

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Figure 3: Comparison of performances among SDS wavy FinFET and DMGO-SDS wavy FinFET (a) electron mobility (b) ID -VGS (c) gm -VGS .

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few challenges is trivial even if a long list of advantages exist. The major issue of concern for this proposed device is the total gate capacitance that should be carefully tackled. This degradation is due to the higher dielectric constant of partial gate oxide. Thus, the increase in Cgg dominates the cutoff frequency of the device and resulting a reduction in fT for the DMGO-SDS wavy FinFET as demonstrated in Fig. 5(b). However, there is some amount of improvement is also noticed in fT for DMGO architecture in the subthreshold region of operation (low VDS =50 mV). This is due to the difference in increment of gm and Cgg values in subthreshold region. 4.2. Temperature dependency of DMGO SDS wavy FinFET Several physical parameters are very much sensitive to temperature. Hence, due to this effect, the electrical behavior of the device changes with respect to the temperature. The non-monotonic behavior of carrier mobility as a function of temperature is due to the combination of several scattering mechanisms [12]. By referring Eq. 1, the drain current ID is mainly influenced by 7

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Figure 4: Parameter analysis between SDS and DMGO-SDS wavy FinFETs (a) T GF -VGS (b) ID -VDS .

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Figure 5: Parameter analysis between SDS and DMGO-SDS wavy FinFETs (a) Cgg -VGS (b) fT -VGS .

two terms i.e., channel mobility (µ) and threshold voltage (Vth ) [16].

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ID (T )αµ (T ) [VGS − Vth (T )]

(1)

And the mobility term is related to temperature in an inverse phenomenon like [16]:  −n T µ (T ) = µ (To ) (2) To

where n is an exponent which varies from 1.6 to 2.4 [20]. And according to the previous reported results, the dependency of threshold voltage (Vth ) in the SOI MOSFETs is inversely proportional to the temperature range (250 C 2250 C) [21]. Hence, the mobility term of Eq. 1 forces ID to decrease, whereas 8

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Figure 6: Drain Current (ID ) as a function of VGS with variation of Temperature (T) (a) SDS wavy FinFET (D1) (b) DMGO-SDS wavy FinFETs (D2).

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the [VGS − Vth ] term increases ID with increase in temperature. However, the behavior of ID with temperature shows opposite effect at a fixed gate bias as reported in Fig. 6(a) and (b). So, the effect of two controlling terms of 1 are nullified at a fixed value of gate bias, which is defined as ZTC bias point. The ZTC point of drain current for SDS wavy FinFET (D1), and DMGO-SDS wavy FinFET (D2) is evaluated and shown in the inset of Fig. 6(a), and (b) respectively. The ZTC point of drain current, ZT CIDS =0.4 V for D1 and 0.421 V for D2 that can be clearly identified from the inset of the Fig. 6.

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Figure 7: Transconductance (gm ) as a function of VGS with variation of Temperature (T) (a) SDS wavy FinFET (D1) (b) DMGO-SDS wavy FinFETs (D2).

Fig. 7 describes the gm variation with VGS at different temperatures (T) for both SDS, and DMGO-SDS wavy FinFETs. In the gm − VGS plot, at VGS < Vth , the channel is weakly inverted and ID is mainly due to diffusion. 9

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Similarly at VGS > Vth the drain current ID is due to drift. Both the transport mechanisms have the same gravity and ID becomes temperature independent at a particular VGS [22]. These two phenomena compensate each other to bring about a ZTC bias point for gm . From the inset values of Fig. 7(a) and (b), we can identify the ZTC point of transconductance, ZT Cgm =0.221 V for D1 and 0.273 V for D2. By observing Fig. 6 and Fig. 7, we can conclude that the ZT Cgm is lower than the ZT CIDS for both the device cases. The ZT CIDS , and ZT Cgm points are two important figures of merit (FOMs) in analog circuit design for wide range of temperature applications. Moreover, the ZTC points are affected by process variations. So, depending upon the nature of applications, the ZTC bias conditions are chosen accordingly [12].

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Figure 8: Comparison of performances among SDS wavy FinFET and DMGO-SDS wavy FinFET with temperature variation (a) on-current (Ion ) (b) off-current (Iof f ) (c) on-off ratio (Ion /Iof f ).

Fig. 8 presents a comparative analysis of digital metrics among conventional FinFET, SDS wavy FinFET, and DMGO-SDS wavy FinFET. All three important digital figures of merit (FOMs), which include Ion , Iof f , and Ion /Iof f ratio are analyzed for three device cases at different temperatures. 10

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5. Conclusion

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With the increase in temperature, the carrier mobility decreases according to Eq. 2. As a matter of fact, the deterioration of on-state current (Ion ) arises. This can be observed from Fig. 8(a), the Ion is high for lower T values and started decaying in an exponential manner as T increases. However, due to the degradation of threshold voltage with the increase in T will also degrade the off-state leakage current, which can be examined from Fig. 8(b). The Ion /Iof f ratio is an important parameter for switching applications. It should be marginally high for a good switch. From Fig. 8(c), lower T provides supreme on-off ratio as compared to higher T values. This is evident from the nature of Ion , and Iof f . These above analogies of Ion , Iof f , and Ion /Iof f ratio are with respect to T variation. If we examine the variation of same parameters by considering the different device cases, then the proposed DMGO-SDS architecture performs superior as compared to its counterparts. By observing Fig. 8, SDS wavy FinFET shows better Ion , Iof f , and Ion /Iof f ratio as compared to conventional FinFET due to its UTB layer (increased the path for current flow), and high-k spacer material (enhances the fringing field lines). And because of the unique architecture of DMGO-SDS wavy FinFET (partial SiO2 and Hf O2 as gate oxide), it predicts optimum performance concerning digital metrics than others.

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This article reveals the concept of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) trigate wavy FinFET (UTB+FinFET+highk spacer material+gate oxide technology) and its unique advantages over SDS wavy FinFET for future technology nodes. This paper illustrates the impact of considering two different dielectric material as gate oxide in SDS wavy platform. Nonetheless, the proposed device architecture shows a 1.36x improvement in Ion , and around 1.73x in gm as compared to SDS wavy FinFET, which is required for higher chip speed. To ensure the device stability, we have performed and evaluated the temperature compensation point (TCP)/ZTC point over various parameters of the device by considering a wide range of temperature (200 K to 500 K) variation. From the conferred results, the existence of TCP/ZTC points for ID , and gm can be identified, which will help to operate the device. Finally, the proposed one will show excellent performance in terms of Ion , Iof f , and gm while operate in low temperatures. This facilitates the circuit designers to choose the device in the low-temperature environment. 11

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The impact of dual material gate oxide (DMGO) in SDS wavy FinFET.

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Evaluation of temperature compensation point (TCP)/ZTC point.

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Approximately 1.36x improvement in Ion and 1.73x in gm for DMGO case.

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