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Reliability challenges of high performance PD SOI CMOS with ultra-thin gate dielectrics
Solid-State Electronics 48 (2004) 1703–1708 www.elsevier.com/locate/sse
Reliability challenges of high performance PD SOI CMOS with ultra-thin gate dielectrics Eugene Zhao *, John Zhang, Akram Salman, Niraj Subba, Jay Chan, Amit Marathe, Stephen Beebe, Kurt Taylor AMD, One AMD place, P.O. Box 3453, M/S 143, Sunnyvale, CA 94088, USA Received 10 December 2003; accepted 15 March 2004
Abstract gate dielectrics, which have significantly higher nitrogen concentration, With the introduction of ultra-thin (<15A) and thus a higher dielectric constant, many new reliability challenges need to be addressed. At the same time, highperformance transistors are now migrating from bulk to silicon-on-insulator (SOI) to boost the performance. This paper will discuss major reliability issues such as negative bias temperature instability (NBTI), hot carrier injection (HCI), time dependent dielectric breakdown (TDDB) and electro-static discharge stress (ESD), etc., facing the state of art technology for SOI. 2004 Elsevier Ltd. All rights reserved. Keywords: SOI; Reliability; Ultra-thin gate dielectrics; Hot carrier; HCI; TDDB; NBTI; ESD
1. Introduction With the demand for better performance (larger drive current) and reliability (longer lifetime) in advanced CMOS technologies, the gate dielectric has been the subject of constant improvement, especially as we enter the 90 and 65 nm technology era [1]. As SOI goes mainstream, it is important to investigate various reliability issues of SOI with ultra-thin gate dielectrics, such as HCI, TDDB, NBTI and ESD. Because of the poor thermal conductivity of the buried oxide (BOX), selfheating, which can cause accelerated degradation, is much more critical in SOI than in bulk. Also, while the floating body effects (FBE) help to deliver higher drive currents, they can nevertheless present a challenge in SOI reliability. Both floating body (FB) and body tied to the source (BT) structures on partially depleted (PD) SOI will be investigated in this paper. The important
*
Corresponding author. Tel.: +1-408-749-3116. E-mail address: [email protected] (E. Zhao).
parameters of the devices studied are as follows: channel length L ¼ 60 nm (nominal), gate oxide thickness tox ¼ 13–18 A (physical), silicon film thickness tSi 90 nm, and buried oxide thickness tBOX 110 nm.
2. Reliability challenges in SOI Structurally the difference between SOI and bulk transistors is the existence of BOX. Typically T-gate structures are used for body tied transistors to provide a current path from body to ground. 2.1. Hot carrier reliability The most common way of characterizing transistor reliability here is through DC-HCI. As the electric field increases, carriers can gain much higher kinetic energy than the ambient temperature; such a carrier is termed a ‘‘hot carrier’’. These hot carriers can be injected into the oxide and degrade the device. As drive current increases, HCI usually gets worse. In Fig. 1, shift in Idsat of a
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.05.003
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E. Zhao et al. / Solid-State Electronics 48 (2004) 1703–1708 100
1.E+2
NMOS PMOS
NMOS Lifetime (A.U.)
1
~6 x VDD =1.7V
1.E+0 VDD =1.8V
Not sensitive to Tox
1.E-1
VDD =1.9V VDD =2.0V
0.1 1.0E+0
1.0E+2
1.E-2 0.48
1.0E+4
Stress Time (s)
typical FB NMOS and a typical FB PMOS are shown following HCI at VG ¼ VD ¼ 1:7 V (NMOS) and VG ¼ VD ¼ 1:8 V (PMOS). It is seen that the shift follows power-time laws with different exponents, suggesting a single carrier injection in PMOS and hole + electron injection in NMOS [2]. Worst-case degradation needs to be identified during the technology qualification. In Fig. 2, device lifetime vs. stress 1=VD is plotted for devices with decoupled plasma nitridation (DPN) gate dielectrics. Unlike the traditional worst-case stress condition at Isubmax , here stressing at VG ¼ VD is found to have shorter lifetime and larger activation
0.52
0.54
0.56
0.58
0.60
Fig. 3. Comparison of thickness and temperature effects: 25 C difference in Tox-inv has 6· lifetime as that of 120 C; but 0.5 A only results in minimal difference in DC-HCI lifetime. All are FB devices, L ¼ 0:06 lm, and measured at VG ¼ VD ¼ 1:5 V.
energy. Temperature and gate dielectric thickness effects on the degradation are shown in Fig. 3, where we compare the lifetimes between 25 and 120 C and see a difference in Tox-inv 6· difference between them. A 0.5 A only results in less than 2· difference in DC-HCI lifetime. Besides DC-HCI, AC-HCI is an alternative way of characterizing hot carrier reliability. It is done with ring oscillators (RO) [3], which correlates directly with the actual product. A comparison of bulk vs. SOI AC-HCI lifetime is shown in Fig. 4, where no significant difference is observed. Our simulation has confirmed that during AC-HCI stress, SOI transistors have limited selfheating, and as a result, their behavior is similar to that
L=0.07µm Floating Body
1.E+2 VG 1@ Isubmax
1.E+20
F-NO-1, SOI
1.E+19
F-NO-2, Bulk F-NO-3, Bulk
1.E+1
1.E+0
VG1 = VD
1.E-1
Isubmax,RT VG=VD, RT Isubmax,100C VG =VD ,10°C
1.E-2 0.35
0.45
0.55
0.65
1/VD (1/V)
Fig. 2. Lifetime vs. 1/VD for DPN gate dielectrics. VG ¼ VD is found to have shorter lifetime and larger activation energy than Isubmax condition. All are FB devices, L ¼ 0:07 lm, and measured at VG ¼ VD ¼ 1:6 V.
Lifetime (A.U.)
Lifetime (A. U.), 10% Idsat)
0.50
1/VDD (1/V)
Fig. 1. NMOS and PMOS follow different power time law, suggesting a single carrier injection in PMOS whereas hole + electron injection in NMOS. All are FB devices, L ¼ 0:06 lm, and measured at VG ¼ VD ¼ 1:5 V. NMOS stressed at VG ¼ VD ¼ 1:7 V, PMOS stressed at VG ¼ VD ¼ 1:8 V.
1.E+3
23.4A-120°C
1.E+1
10
∆Idsat (%)
22.9A-120°C 23.4A-room
F-NO-4, Bulk
1.E+18 1.E+17 1.E+16 1.E+15 lifetime at 10% ∆f
1.E+14 1.E+13 1.5
2
2.5
3
Vstr(V) Fig. 4. Comparison of bulk and SOI AC-HCI lifetime. No significant difference was observed between bulk and SOI.
E. Zhao et al. / Solid-State Electronics 48 (2004) 1703–1708 10
Lifetime (A.U.)
10.0
1 AC-HCI, FO=1 Tox,inv~22.8A
1.0
0.1
Lifetime (A.U.)
100.0
DC-HCI, VG=VD Tox,inv~22.6A 0.1 0.40
0.45
0.50
0.55
0.01 0.60
1/VDD (1/V) Fig. 5. DC and AC HCI at similar conditions have been conducted in parallel. DC-HCI has higher voltage scaling factor, which is only observed in SOI. L ¼ 0:06 (physical).
of bulk. To understand the correlation between DC and AC degradation, we have compared these two HCI degradations in Fig. 5. DC-HCI was found to have a larger voltage scaling factor, a result that can also be explained by self-heating. 2.2. NBTI A PMOS with a surface channel and a Pþ poly gate is subject to NBTI degradation. NBTI is manifested as an increase in threshold voltage (Vt ) and a decrease in drive current (Idsat ) during the operation in the inversion mode at a bias that limits the gate tunneling below the Fowler– Nordheim (F–N) regime at elevated temperature [4,5]. This effect becomes increasingly prominent as CMOS technology scales down, given that a thinner gate dielectric is more prone to the influence of interface states. The mechanism of NBTI degradation, though not completely understood yet, is widely believed to relate to hole-assisted SiAH bond dissociation in Si3 BSiAH through an electrochemical reaction that produces interface states (Si3 BSi ) and positive fixed charges (O3 BSiþ ) [4–6]. NBTI degradation is very sensitive to the gate dielectric fabrication process and may be employed as a process monitor by a fab. This failure mechanism may seriously affect the semiconductor reliability, competing with HCI. For 130 nm technology, product-level reliability measurements show that Fmax degradation can no longer be accounted for by HCI alone. It appears that NBTI plays a significant role in the overall reliability of a microprocessor. Although SOI technology possesses some unique reliability features, FB SOI technology exhibits NBTI degradation very similar to that of bulk technology.
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Here, both technologies are Furnace-NO (F-NO) process based. Stress conditions are )2.6 V and 100 C. Given that little current flows in the channel during the NBTI stress, the self-heating effect inherent to SOI technology due to buried oxide (BOX) is not important in the SOI experiment. Yet the temperature rise caused by the self-heating that occurs in the other portions of a circuit has to be considered for the overall reliability evaluation. Fortunately, self-heating is minimized during AC operation. The dynamic behavior of a FB SOI transistor is one of the factors that boosts transistor performance. However, this dynamic feature must be avoided in some paths, such as a phase-locked loop (PLL) or I/O, for the high stability requirement of the circuit. A BT or body contact (BC) is designed toward this end. Though bodytied transistors are limited in use due to the fact that the extrinsic gate results in extra loading capacitance and lowers performance, their reliability must be carefully investigated––the unique body tie structure may pose unique reliability challenges. Now we compare the Vt shift of BT devices subjected to the NBTI stress at )2.6 V and 100 C to that of FB devices. About 14% more degradation is observed in the BT devices. To verify that the extra degradation is indeed associated with the body tie, we have the body-tie terminal floated (BTf) in some BT devices and stress them at the same condition. We obtain similar results to those of the FB devices. This unique body-tie effect on NBTI reveals that both hole population and oxide field control NBTI degradation [7].
2.3. TDDB The reliability of a gate dielectric is evaluated by TDDB, when a gate dielectric is stressed with high electric field [8]. To obtain a clear breakdown behavior, test structures need to be designed with small gate area [9], so the total gate leakage is relatively small. Besides soft breakdown that challenges ultra-thin dielectric testing, signal RTS noise is more common in SOI, especially with small-area FB test structures. Since the T-gate is a special structure in SOI, we need to assess its reliability. BT vs. FB lifetimes have been compared in Fig. 6 to check the impact of T-gate. The results imply that the addition of a T-gate shortens gate dielectric lifetime. This is because part of the gate dielectric is biased in accumulation and thus has shorter lifetime. Fig. 7 shows the maximum voltage that can be applied on gate dielectric (Max-Vcc) vs. gate dielectric thickness in the current technology era. Furnace-NO no longer meets the Vcc requirements, so DPN, with 100 mV improvement at Tox-inv A, need to be used. As stated earlier, DPN has significantly higher nitrogen than Furnace-NO.
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1400
HBM level (KV)
10
Lifetime (A.U.)
Floating Body
10
SOI(HBM)
1000
BULK(HBM 800 600
Tied Body
1
1200
400 0 2.5
2.6
2.7
2.8
VG(V)
2.00
(Vcc normalized to the same lifetime and failure rate)
MaxVcc (A.U.)
1.60
1.40
F-NO
DPN
1.20
1.00 20
21
22
1
1.5
2
L(µm) Fig. 8. Comparison of HBM protection level of bulk vs. SOI for three different channel lengths (grounded gate NMOS).
Fig. 6. Body tied devices show shorter TDDB lifetime than floating body at inversion. Both are PMOS and have the same W and L.
1.80
0.5
23
24
25
Tox_inv (A) Fig. 7. Max-Vcc vs. gate dielectric thickness in current technology era. Furnace-NO no longer meets the Vcc requirements. DPN, which can provide 100 mV improvement at 21A Toxinv, needs to be used.
2.4. ESD ESD susceptibility of SOI technology is a major reliability issue. In bulk technologies good protection levels have been demonstrated by using NMOS/CMOS output buffers. However, most protection schemes developed for bulk may not be compatible with SOI structures. For example the use of thick-field oxide devices becomes impractical on SOI wafers. Large area low-series-resistance (vertical) PN junctions are not available either, as the silicon film is usually thinner than
150 nm. Fig. 8 shows that the SOI human body model (HBM) protection levels drop to almost 50% of the bulk technology protection levels for MOSFET protection scheme. Most of the ESD failures are attributed to thermal runaway, which can explain the reduction in the protection levels due to the self-heating problem associated with the SOI. Based on what we have explained, the protection elements that can be used for the ESD protection of SOI circuits are mainly diodes and transistors. Diodes are always considered the easiest and the simplest way to protect against an ESD event due to their low turn-on voltage and low capacitance. MOSFET transistors can also be used for ESD protection in the grounded gate configuration. However, during snapback operation uniform triggering is not usually guaranteed and current can crowd in a portion of the width causing partial damage to the transistor. There are some solutions that have been introduced to solve the problem either by blocking the salicide on the junction, thus increasing the resistance and, therefore, pushing the current away from the surface to achieve uniform triggering [10–12], or by external triggering of the gate or the substrate, or both [13,14]. These solutions, though successful, might increase the input capacitance and leakage or complicate the protection circuit design and consume more area [15]. So a diode protection seems more attractive for ESD protection of SOI circuits. The lateral diode is the best way to create a uniform diode in the SOI technology and it has been used for ESD because of its high current capability, low capacitive loading, and its simplicity to design. There are several ways to build the lateral diode [16], but the most compatible one with the CMOS process is the poly bounded lateral diode. As shown in Fig. 9 the diode is built in an N-well and looks identical to a PMOS transistor, except the source side implant is changed from Pþ
E. Zhao et al. / Solid-State Electronics 48 (2004) 1703–1708 Cathode
N+
Anode
N-well
P+
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gate oxide breakdown voltage. This voltage is due to the body resistance IR drop that becomes high near the anode junction. To solve such a problem a floating-poly diode can be used for the ESD protection circuits. 3. Conclusions
BOX
Fig. 9. Typical ESD protection structure used in SOI: polybounded SOI lateral diode with poly tied to cathode.
to Nþ , creating a body diode. This diode can also be fabricated like an NMOS, but the P-body may have a higher sheet resistance than the N-body. The diode has the halo and extension implants blocked for two reasons: (1) to prevent any stress on the gate where the gate is connected to the ground side of the transistor and (2) to have a uniform conducting diode in which the current is conducted through the whole junction wall, yielding higher current carrying capability. Junction breakdown and filamentation due to thermal runaway are the usual ESD failure mechanisms of the diodes, but for the thin oxide technology stressed under charged device model (CDM) [17], the SOI ESD diode experiences gate dielectric breakdown. This is shown in Fig. 10. This can be explained using Medici device simulation where a pulsed stress current of 30 mA/lm for 10 ns was applied. It was observed that a voltage drop across the gate oxide in the range of 4.5 V can develop, which is close to the
Fig. 10. Gate oxide failure of SOI ESD lateral diode under CDM stress.
We have discussed some major reliability issues in developing cutting-edge SOI technologies with ultra-thin gate dielectrics. These include HCI, NBTI, TDDB and ESD. It is found that with careful device and process design, good reliability levels can be achieved. Moreover, it emerged from this study that PMOS can be a growing concern with the continuous increase of nitrogen concentration in the gate dielectrics.
References [1] Celik M et al. VLSI Technol 2002:166–7. [2] Sinha SP, Duan FL, Ioannou DE, Jenkins WC, Hughes HL. Time dependence power laws of hot carrier degradation in SOI MOSFETS. In: 1996 IEEE International SOI Conference Proceedings, 30 September–3 October 1996. p. 18–9. [3] Zhang J et al. IEEE EDL 2002;(9):1672–4. [4] Jeppson KO, Svensson CM. J Appl Phys 1977;48:2004. [5] Blat CE, Nicollian EH, Poidexter EH. J Appl Phys 1991; 69:1712. [6] Ogawa S, Shimoya M, Shiono N. J Appl Phys 1995; 77(3):1137. [7] Zhang J, Marathe A, Taylor K, Zhao E, En B. IRPS. #TR05. 2004. [8] Hunter WR, The analysis of oxide reliability data. In: 1998 IEEE International Integrated Reliability Workshop Final Report, 12–15 October 1998. p. 114–34. [9] Wu EY, Aitken J, Nowak E, Vayshenker A, Varekamp P, Hueckel G, et al. Voltage-dependent voltage-acceleration of oxide breakdown for ultra-thin oxides. In: 2000 International Electron Devices Meeting Technical Digest, 10–13 December 2000. p. 541–4. [10] Ajith Amerasekera, Charvaka Duvvury. ESD in silicon integrated circuits. second ed. Wiley; 2002. [11] Amerasekera A, Ramaswamy S, Chang M, Duvvury C. Modeling MOS snapback and the parasitic bipolar action for circuit level and high current simulations. In: Proceedings of the IRPS. 1996. [12] Voldman S, Assaderaghi F, Hsu L, Shahidi G. Dynamic threshold body-and gate-coupled SOI ESD protection networks. In: EOS/ESD Symposium Proceedings. 1997. [13] Salman A, Mitra S, Ioannou D, Fechner P, Liu M. An ESD protection circuit for SOI technology using gate- and body-biased MOSFET’s. In: Proceedings of the International SOI Conference. 2002. p. 45–6. [14] Duvvury M, Amerasekera A. Advanced CMOS protection device trigger mechanism during CDM. In: EOS/ESD Symposium Proceedings. 1995. [15] Gauthier R, Stadler W, Esmark K, Riess P, Salman A, Muhammad M, et al. Evaluation of diode-based and
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NMOS/Lnpn-based ESD protection strategies in a triple gate oxide thickness 0.13m CMOS logic technology. In: EOS/ESD Symposium Proceedings. 2001. p. 205–15. [16] Ker M-D, Hung K-K, Tang H, Huang S-C, Chen S-S, Wang M-C. Novel diode structures and ESD protection
circuits in a 1.8-V 0.15-m partially-depleted SOI salicided CMOS process. IPFA 2001:91–6. [17] Beebe S. Simulation of complete CMOS I/O circuit response to CDM stress. In: EOS/ESD Symposium Proceedings. 1998. p. 259–70.
Reliability challenges of high performance PD SOI CMOS with ultra-thin gate dielectrics Eugene Zhao *, John Zhang, Akram Salman, Niraj Subba, Jay Chan, Amit Marathe, Stephen Beebe, Kurt Taylor AMD, One AMD place, P.O. Box 3453, M/S 143, Sunnyvale, CA 94088, USA Received 10 December 2003; accepted 15 March 2004
Abstract gate dielectrics, which have significantly higher nitrogen concentration, With the introduction of ultra-thin (<15A) and thus a higher dielectric constant, many new reliability challenges need to be addressed. At the same time, highperformance transistors are now migrating from bulk to silicon-on-insulator (SOI) to boost the performance. This paper will discuss major reliability issues such as negative bias temperature instability (NBTI), hot carrier injection (HCI), time dependent dielectric breakdown (TDDB) and electro-static discharge stress (ESD), etc., facing the state of art technology for SOI. 2004 Elsevier Ltd. All rights reserved. Keywords: SOI; Reliability; Ultra-thin gate dielectrics; Hot carrier; HCI; TDDB; NBTI; ESD
1. Introduction With the demand for better performance (larger drive current) and reliability (longer lifetime) in advanced CMOS technologies, the gate dielectric has been the subject of constant improvement, especially as we enter the 90 and 65 nm technology era [1]. As SOI goes mainstream, it is important to investigate various reliability issues of SOI with ultra-thin gate dielectrics, such as HCI, TDDB, NBTI and ESD. Because of the poor thermal conductivity of the buried oxide (BOX), selfheating, which can cause accelerated degradation, is much more critical in SOI than in bulk. Also, while the floating body effects (FBE) help to deliver higher drive currents, they can nevertheless present a challenge in SOI reliability. Both floating body (FB) and body tied to the source (BT) structures on partially depleted (PD) SOI will be investigated in this paper. The important
*
Corresponding author. Tel.: +1-408-749-3116. E-mail address: [email protected] (E. Zhao).
parameters of the devices studied are as follows: channel length L ¼ 60 nm (nominal), gate oxide thickness tox ¼ 13–18 A (physical), silicon film thickness tSi 90 nm, and buried oxide thickness tBOX 110 nm.
2. Reliability challenges in SOI Structurally the difference between SOI and bulk transistors is the existence of BOX. Typically T-gate structures are used for body tied transistors to provide a current path from body to ground. 2.1. Hot carrier reliability The most common way of characterizing transistor reliability here is through DC-HCI. As the electric field increases, carriers can gain much higher kinetic energy than the ambient temperature; such a carrier is termed a ‘‘hot carrier’’. These hot carriers can be injected into the oxide and degrade the device. As drive current increases, HCI usually gets worse. In Fig. 1, shift in Idsat of a
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.05.003
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E. Zhao et al. / Solid-State Electronics 48 (2004) 1703–1708 100
1.E+2
NMOS PMOS
NMOS Lifetime (A.U.)
1
~6 x VDD =1.7V
1.E+0 VDD =1.8V
Not sensitive to Tox
1.E-1
VDD =1.9V VDD =2.0V
0.1 1.0E+0
1.0E+2
1.E-2 0.48
1.0E+4
Stress Time (s)
typical FB NMOS and a typical FB PMOS are shown following HCI at VG ¼ VD ¼ 1:7 V (NMOS) and VG ¼ VD ¼ 1:8 V (PMOS). It is seen that the shift follows power-time laws with different exponents, suggesting a single carrier injection in PMOS and hole + electron injection in NMOS [2]. Worst-case degradation needs to be identified during the technology qualification. In Fig. 2, device lifetime vs. stress 1=VD is plotted for devices with decoupled plasma nitridation (DPN) gate dielectrics. Unlike the traditional worst-case stress condition at Isubmax , here stressing at VG ¼ VD is found to have shorter lifetime and larger activation
0.52
0.54
0.56
0.58
0.60
Fig. 3. Comparison of thickness and temperature effects: 25 C difference in Tox-inv has 6· lifetime as that of 120 C; but 0.5 A only results in minimal difference in DC-HCI lifetime. All are FB devices, L ¼ 0:06 lm, and measured at VG ¼ VD ¼ 1:5 V.
energy. Temperature and gate dielectric thickness effects on the degradation are shown in Fig. 3, where we compare the lifetimes between 25 and 120 C and see a difference in Tox-inv 6· difference between them. A 0.5 A only results in less than 2· difference in DC-HCI lifetime. Besides DC-HCI, AC-HCI is an alternative way of characterizing hot carrier reliability. It is done with ring oscillators (RO) [3], which correlates directly with the actual product. A comparison of bulk vs. SOI AC-HCI lifetime is shown in Fig. 4, where no significant difference is observed. Our simulation has confirmed that during AC-HCI stress, SOI transistors have limited selfheating, and as a result, their behavior is similar to that
L=0.07µm Floating Body
1.E+2 VG 1@ Isubmax
1.E+20
F-NO-1, SOI
1.E+19
F-NO-2, Bulk F-NO-3, Bulk
1.E+1
1.E+0
VG1 = VD
1.E-1
Isubmax,RT VG=VD, RT Isubmax,100C VG =VD ,10°C
1.E-2 0.35
0.45
0.55
0.65
1/VD (1/V)
Fig. 2. Lifetime vs. 1/VD for DPN gate dielectrics. VG ¼ VD is found to have shorter lifetime and larger activation energy than Isubmax condition. All are FB devices, L ¼ 0:07 lm, and measured at VG ¼ VD ¼ 1:6 V.
Lifetime (A.U.)
Lifetime (A. U.), 10% Idsat)
0.50
1/VDD (1/V)
Fig. 1. NMOS and PMOS follow different power time law, suggesting a single carrier injection in PMOS whereas hole + electron injection in NMOS. All are FB devices, L ¼ 0:06 lm, and measured at VG ¼ VD ¼ 1:5 V. NMOS stressed at VG ¼ VD ¼ 1:7 V, PMOS stressed at VG ¼ VD ¼ 1:8 V.
1.E+3
23.4A-120°C
1.E+1
10
∆Idsat (%)
22.9A-120°C 23.4A-room
F-NO-4, Bulk
1.E+18 1.E+17 1.E+16 1.E+15 lifetime at 10% ∆f
1.E+14 1.E+13 1.5
2
2.5
3
Vstr(V) Fig. 4. Comparison of bulk and SOI AC-HCI lifetime. No significant difference was observed between bulk and SOI.
E. Zhao et al. / Solid-State Electronics 48 (2004) 1703–1708 10
Lifetime (A.U.)
10.0
1 AC-HCI, FO=1 Tox,inv~22.8A
1.0
0.1
Lifetime (A.U.)
100.0
DC-HCI, VG=VD Tox,inv~22.6A 0.1 0.40
0.45
0.50
0.55
0.01 0.60
1/VDD (1/V) Fig. 5. DC and AC HCI at similar conditions have been conducted in parallel. DC-HCI has higher voltage scaling factor, which is only observed in SOI. L ¼ 0:06 (physical).
of bulk. To understand the correlation between DC and AC degradation, we have compared these two HCI degradations in Fig. 5. DC-HCI was found to have a larger voltage scaling factor, a result that can also be explained by self-heating. 2.2. NBTI A PMOS with a surface channel and a Pþ poly gate is subject to NBTI degradation. NBTI is manifested as an increase in threshold voltage (Vt ) and a decrease in drive current (Idsat ) during the operation in the inversion mode at a bias that limits the gate tunneling below the Fowler– Nordheim (F–N) regime at elevated temperature [4,5]. This effect becomes increasingly prominent as CMOS technology scales down, given that a thinner gate dielectric is more prone to the influence of interface states. The mechanism of NBTI degradation, though not completely understood yet, is widely believed to relate to hole-assisted SiAH bond dissociation in Si3 BSiAH through an electrochemical reaction that produces interface states (Si3 BSi ) and positive fixed charges (O3 BSiþ ) [4–6]. NBTI degradation is very sensitive to the gate dielectric fabrication process and may be employed as a process monitor by a fab. This failure mechanism may seriously affect the semiconductor reliability, competing with HCI. For 130 nm technology, product-level reliability measurements show that Fmax degradation can no longer be accounted for by HCI alone. It appears that NBTI plays a significant role in the overall reliability of a microprocessor. Although SOI technology possesses some unique reliability features, FB SOI technology exhibits NBTI degradation very similar to that of bulk technology.
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Here, both technologies are Furnace-NO (F-NO) process based. Stress conditions are )2.6 V and 100 C. Given that little current flows in the channel during the NBTI stress, the self-heating effect inherent to SOI technology due to buried oxide (BOX) is not important in the SOI experiment. Yet the temperature rise caused by the self-heating that occurs in the other portions of a circuit has to be considered for the overall reliability evaluation. Fortunately, self-heating is minimized during AC operation. The dynamic behavior of a FB SOI transistor is one of the factors that boosts transistor performance. However, this dynamic feature must be avoided in some paths, such as a phase-locked loop (PLL) or I/O, for the high stability requirement of the circuit. A BT or body contact (BC) is designed toward this end. Though bodytied transistors are limited in use due to the fact that the extrinsic gate results in extra loading capacitance and lowers performance, their reliability must be carefully investigated––the unique body tie structure may pose unique reliability challenges. Now we compare the Vt shift of BT devices subjected to the NBTI stress at )2.6 V and 100 C to that of FB devices. About 14% more degradation is observed in the BT devices. To verify that the extra degradation is indeed associated with the body tie, we have the body-tie terminal floated (BTf) in some BT devices and stress them at the same condition. We obtain similar results to those of the FB devices. This unique body-tie effect on NBTI reveals that both hole population and oxide field control NBTI degradation [7].
2.3. TDDB The reliability of a gate dielectric is evaluated by TDDB, when a gate dielectric is stressed with high electric field [8]. To obtain a clear breakdown behavior, test structures need to be designed with small gate area [9], so the total gate leakage is relatively small. Besides soft breakdown that challenges ultra-thin dielectric testing, signal RTS noise is more common in SOI, especially with small-area FB test structures. Since the T-gate is a special structure in SOI, we need to assess its reliability. BT vs. FB lifetimes have been compared in Fig. 6 to check the impact of T-gate. The results imply that the addition of a T-gate shortens gate dielectric lifetime. This is because part of the gate dielectric is biased in accumulation and thus has shorter lifetime. Fig. 7 shows the maximum voltage that can be applied on gate dielectric (Max-Vcc) vs. gate dielectric thickness in the current technology era. Furnace-NO no longer meets the Vcc requirements, so DPN, with 100 mV improvement at Tox-inv A, need to be used. As stated earlier, DPN has significantly higher nitrogen than Furnace-NO.
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1400
HBM level (KV)
10
Lifetime (A.U.)
Floating Body
10
SOI(HBM)
1000
BULK(HBM 800 600
Tied Body
1
1200
400 0 2.5
2.6
2.7
2.8
VG(V)
2.00
(Vcc normalized to the same lifetime and failure rate)
MaxVcc (A.U.)
1.60
1.40
F-NO
DPN
1.20
1.00 20
21
22
1
1.5
2
L(µm) Fig. 8. Comparison of HBM protection level of bulk vs. SOI for three different channel lengths (grounded gate NMOS).
Fig. 6. Body tied devices show shorter TDDB lifetime than floating body at inversion. Both are PMOS and have the same W and L.
1.80
0.5
23
24
25
Tox_inv (A) Fig. 7. Max-Vcc vs. gate dielectric thickness in current technology era. Furnace-NO no longer meets the Vcc requirements. DPN, which can provide 100 mV improvement at 21A Toxinv, needs to be used.
2.4. ESD ESD susceptibility of SOI technology is a major reliability issue. In bulk technologies good protection levels have been demonstrated by using NMOS/CMOS output buffers. However, most protection schemes developed for bulk may not be compatible with SOI structures. For example the use of thick-field oxide devices becomes impractical on SOI wafers. Large area low-series-resistance (vertical) PN junctions are not available either, as the silicon film is usually thinner than
150 nm. Fig. 8 shows that the SOI human body model (HBM) protection levels drop to almost 50% of the bulk technology protection levels for MOSFET protection scheme. Most of the ESD failures are attributed to thermal runaway, which can explain the reduction in the protection levels due to the self-heating problem associated with the SOI. Based on what we have explained, the protection elements that can be used for the ESD protection of SOI circuits are mainly diodes and transistors. Diodes are always considered the easiest and the simplest way to protect against an ESD event due to their low turn-on voltage and low capacitance. MOSFET transistors can also be used for ESD protection in the grounded gate configuration. However, during snapback operation uniform triggering is not usually guaranteed and current can crowd in a portion of the width causing partial damage to the transistor. There are some solutions that have been introduced to solve the problem either by blocking the salicide on the junction, thus increasing the resistance and, therefore, pushing the current away from the surface to achieve uniform triggering [10–12], or by external triggering of the gate or the substrate, or both [13,14]. These solutions, though successful, might increase the input capacitance and leakage or complicate the protection circuit design and consume more area [15]. So a diode protection seems more attractive for ESD protection of SOI circuits. The lateral diode is the best way to create a uniform diode in the SOI technology and it has been used for ESD because of its high current capability, low capacitive loading, and its simplicity to design. There are several ways to build the lateral diode [16], but the most compatible one with the CMOS process is the poly bounded lateral diode. As shown in Fig. 9 the diode is built in an N-well and looks identical to a PMOS transistor, except the source side implant is changed from Pþ
E. Zhao et al. / Solid-State Electronics 48 (2004) 1703–1708 Cathode
N+
Anode
N-well
P+
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gate oxide breakdown voltage. This voltage is due to the body resistance IR drop that becomes high near the anode junction. To solve such a problem a floating-poly diode can be used for the ESD protection circuits. 3. Conclusions
BOX
Fig. 9. Typical ESD protection structure used in SOI: polybounded SOI lateral diode with poly tied to cathode.
to Nþ , creating a body diode. This diode can also be fabricated like an NMOS, but the P-body may have a higher sheet resistance than the N-body. The diode has the halo and extension implants blocked for two reasons: (1) to prevent any stress on the gate where the gate is connected to the ground side of the transistor and (2) to have a uniform conducting diode in which the current is conducted through the whole junction wall, yielding higher current carrying capability. Junction breakdown and filamentation due to thermal runaway are the usual ESD failure mechanisms of the diodes, but for the thin oxide technology stressed under charged device model (CDM) [17], the SOI ESD diode experiences gate dielectric breakdown. This is shown in Fig. 10. This can be explained using Medici device simulation where a pulsed stress current of 30 mA/lm for 10 ns was applied. It was observed that a voltage drop across the gate oxide in the range of 4.5 V can develop, which is close to the
Fig. 10. Gate oxide failure of SOI ESD lateral diode under CDM stress.
We have discussed some major reliability issues in developing cutting-edge SOI technologies with ultra-thin gate dielectrics. These include HCI, NBTI, TDDB and ESD. It is found that with careful device and process design, good reliability levels can be achieved. Moreover, it emerged from this study that PMOS can be a growing concern with the continuous increase of nitrogen concentration in the gate dielectrics.
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NMOS/Lnpn-based ESD protection strategies in a triple gate oxide thickness 0.13m CMOS logic technology. In: EOS/ESD Symposium Proceedings. 2001. p. 205–15. [16] Ker M-D, Hung K-K, Tang H, Huang S-C, Chen S-S, Wang M-C. Novel diode structures and ESD protection
circuits in a 1.8-V 0.15-m partially-depleted SOI salicided CMOS process. IPFA 2001:91–6. [17] Beebe S. Simulation of complete CMOS I/O circuit response to CDM stress. In: EOS/ESD Symposium Proceedings. 1998. p. 259–70.