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Reliability studies of MOS Si-gate arrays
304
WORLD
ABSTRACTS
ON
MICROELECTRONICS
R e l i a b i l i t y s t u d i e s o f M O S Si-gate arrays. D. J. FITZGERALD,G. H. PARKER a n d P. SPIEGEL,Proc. I E E E Reliab. Phys. Symp., L a s Vegas, U.S.A. 31 M a r c h 2 April (1971). M O S failure m e c h a n i s m s involving charge built u p w i t h i n a n d on dielectrics, destructive b r e a k d o w n of dielectrics a n d o p e n i n g of a l u m i n u m interc o n n e c t i o n s are reviewed. D a t a are p r e s e n t e d on static a n d d y n a m i c L S I arrays stressed u n d e r a variety of conditions: h i g h t e m p e r a t u r e storage, h i g h t e m p e r a t u r e reverse bias/power life-testing, p o w e r cycling, e x t e n d e d t e m p e r a t u r e cycling. I n c l u d e d a m o n g t h e arrays is a novel electronically p r o g r a m m a b l e read only m e m o r y . T h e s e data s h o w that t h e Si-gate technology provides excellent reliability in every case.
C o m p u t e r a i d e d reliability a s s u r a n c e s y s t e m for ICs. M. NAKAMURA, H. KUMAGAI a n d N. MANABE, Proc. Ann. Syrup. Reliab., W a s h i n g t o n D C , U . S . A . I E E E Cat. No. 71C 2 - R 12-14 J a n u a r y (1971) p. 42. I n order to assure the reliability we have applied the lot verification test w h i c h comprises the life test a n d t h e e n v i r o n m e n t a l test for every s h i p p i n g lot of ICs. T h i s test requires a long period a n d m a n y laborious p r o c e d u r e s ; n e v e r t h e less the reliability of the lot assured by this test is s o m e t i m e s poor against t h e test data, a n d c o n s e q u e n t l y w h e n a m a n u f a c t u r i n g lot passes this test, it c a n n o t always be expected n o t to cause serious troubles at t h e customers. Accordinqly, after a precise analysis of t h e relation especially b e t w e e n the field failure data a n d the corres p o n d i n g s c r e e n i n g data, characteristics test data a n d m a n u f a c t u r i n g test data, we f o u n d the close correlation b e t w e e n t h e m . T h e n we tried to utilize this fact a n d finally succeeded to build up quite a n e w s y s t e m of reliability a s s u r a n c e for t h e p r o d u c t i o n of integrated circuits. T h i s s y s t e m is characterized in detailed observations to the process data, e.g. yield, and it is worked o u t by t h e c o m p u t e r . In this paper, we first introduce t h e conventional reliability a s s u r a n c e s y s t e m of o u r prod u c t s a n d discuss its shortcomings, citing s o m e examples. Next, t h e idea a n d t h e outline of the n e w reliability a s s u r a n c e s y s t e m " C A R A S " are described, and t h e effectiveness of the n e w s y s t e m is p r e s e n t e d with an example.
Variables affecting thermally induced surface r e c o n s t r u c t i o n in A l - m e t a l . E. PHILOFSKY, E. RAVI, E. HALL a n d J. BLACK. Proc. I E E E Re[lab. Phys. Symp.,
AND
RELIABILITY
stress w a v e s . J. R. ADAMS a n d H. L. FLOYD, Proc. I E E E Reliab. Phys. Syrup., L a s Vegas, U . S . A . 31 M a r c h - 2 April (1971). A novel t e c h n i q u e for either destructive or n o n - d e s t r u c t i v e evaluation of t h e m e c h a nical integrity of b e a m lead transistors a n d integrated circuits has been d e m o n s t r a t e d . A F e b e t r o n 705 flash election b e a m m a c h i n e was used to generate t h e r m o mechanical stress waves w h i c h were acoustically c o u p l e d to b o n d e d b e a m lead devices. C o m p u t e r - a i d e d stress wave analysis of t h e s y s t e m was used to calculate t h e stresses generated in t h e individual beams. T h i s allows prediction of failure m o d e s a n d levels. E x p e r i m e n t a l results have d e m o n s t r a t e d that m o s t failure m o d e s can be related to device or b o n d i n g deficiencies, a n d reveal failures w h i c h cannot be easily obtained by other m e t h o d s of testing.
Thermal
excursion
can
cause
bond p r o b l e m s .
M. F. NOWAKOWSKI and F. VILLELLA,Proc. IEEEReliab. Phys. Syrup., L a s Vegas, U.S.A. 31 M a r c h - 2 April (1971). T h e p u r p o s e of this p a p e r is to illustrate t h e failure m o d e caused by t h e r m a l d e f o r m a t i o n a n d h o w t h e r m a l d e f o r m a t i o n affects b o n d integrity. W e d g e b o n d i n g in small-signal transistors, microcircuits a n d L S I circuits is t h e subject of this work. Repeated s w i t c h ing of the devices b e t w e e n h i g h a n d low p o w e r at a rate that allows t h e r m a l expansion a n d contraction in t h e i n t e r c o n n e c t i n g wire causes t h e wire to flex at the p o i n t of reduced cross-sectional area until finally the wire breaks d u e to metal fatigue. It was observed that t h e t h e r m a l d e f o r m a t i o n was related to m a n y factors s u c h as device p o w e r dissipation, c u r r e n t density in t h e wire, wire dress a n d length, t h e r m a l t i m e c o n s t a n t a n d f r e q u e n c y of operation.
D e g r a d a t i o n a n d p a s s i v a t i o n of light e m i t t i n g d i o d e s . R. L. HARTMAN,M. KUHN a n d B. SCHWARTZ, Proc. I E E E Reliab. Phys. Syrup., L a s Vegas, U . S . A . 31 M a r c h - 2 April (1971). D e g r a d a t i o n of electrol u m i n e s c e n c e of G a P light e m i t t i n g diodes has been significantly reduced by chemical passivation of t h e surfaces. Passivation was achieved by p r o d u c i n g an a m o r p h o u s native oxide over t h e exposed surfaces of completed diode structures. D e g r a d a t i o n characteristics of passivated a n d u n p a s s i v a t e d devices will be d i s c u s s e d a n d qualitatively explained in t e r m s of a simple model.
L a s Vegas, U.S.A. 31 M a r c h - 2 April (1971). T h e surface of a l u m i n u m metallization on silicon devices can reconstruct with elevated t e m p e r a t u r e t r e a t m e n t s d u e to t h e relief of c o m p r e s s i v e stresses i n d u c e d by t h e r m a l e x p a n sion differences b e t w e e n a l u m i n u m and silicon. T h i s reconstruction can cause reliability p r o b l e m s because of t h e d e v e l o p m e n t of t h i n regions in t h e metal. Also, in multilayer cirouits, hillocks can p u n c h t h r o u g h the oxide layer a n d cause electrical shorts. T h e effects of grain size a n d alloying additions on this surface reconstruction are p r e s e n t e d a n d discussed in this study.
Aluminum-aluminum o x i d e m e t a l l u r g y for e n h a n c e d e l e c t r o m i g r a t i o n r e s i s t a n c e in m o n o l i t h i c circuits. S. M. DESHPANDE,Proc. I E E E Reliab. Phys. Symp., L a s Vegas, U . S . A . 31 M a r c h - 2 April (1971).
E v a l u a t i o n of the m e c h a n i c a l integrity o f b e a m lead devices and bonds using thermomechanical
* M e c h a n i s m s a n d m o d e s o f failure in s i l i c o n planar s e m i c o n d u c t o r d e v i c e s . F. N. SINNADURAI,
Because of its relatively h i g h creep resistance, A1 + A1 sO 3 alloy has been s h o w n to exhibit superior electromigration resistance. T h i s p a p e r reviews the r.f. s p u t t e r i n g d e p o sition t e c h n i q u e of t h e alloy films, feasibility of a l u m i n u m - a l u m i n u m oxide alloy m e t a l l u r g y for monolithic circuits a n d increased electromigration resistance data obtained on t h e alloy films.
WORLD
ABSTRACTS
ON
MICROELECTRONICS
R e l i a b i l i t y s t u d i e s o f M O S Si-gate arrays. D. J. FITZGERALD,G. H. PARKER a n d P. SPIEGEL,Proc. I E E E Reliab. Phys. Symp., L a s Vegas, U.S.A. 31 M a r c h 2 April (1971). M O S failure m e c h a n i s m s involving charge built u p w i t h i n a n d on dielectrics, destructive b r e a k d o w n of dielectrics a n d o p e n i n g of a l u m i n u m interc o n n e c t i o n s are reviewed. D a t a are p r e s e n t e d on static a n d d y n a m i c L S I arrays stressed u n d e r a variety of conditions: h i g h t e m p e r a t u r e storage, h i g h t e m p e r a t u r e reverse bias/power life-testing, p o w e r cycling, e x t e n d e d t e m p e r a t u r e cycling. I n c l u d e d a m o n g t h e arrays is a novel electronically p r o g r a m m a b l e read only m e m o r y . T h e s e data s h o w that t h e Si-gate technology provides excellent reliability in every case.
C o m p u t e r a i d e d reliability a s s u r a n c e s y s t e m for ICs. M. NAKAMURA, H. KUMAGAI a n d N. MANABE, Proc. Ann. Syrup. Reliab., W a s h i n g t o n D C , U . S . A . I E E E Cat. No. 71C 2 - R 12-14 J a n u a r y (1971) p. 42. I n order to assure the reliability we have applied the lot verification test w h i c h comprises the life test a n d t h e e n v i r o n m e n t a l test for every s h i p p i n g lot of ICs. T h i s test requires a long period a n d m a n y laborious p r o c e d u r e s ; n e v e r t h e less the reliability of the lot assured by this test is s o m e t i m e s poor against t h e test data, a n d c o n s e q u e n t l y w h e n a m a n u f a c t u r i n g lot passes this test, it c a n n o t always be expected n o t to cause serious troubles at t h e customers. Accordinqly, after a precise analysis of t h e relation especially b e t w e e n the field failure data a n d the corres p o n d i n g s c r e e n i n g data, characteristics test data a n d m a n u f a c t u r i n g test data, we f o u n d the close correlation b e t w e e n t h e m . T h e n we tried to utilize this fact a n d finally succeeded to build up quite a n e w s y s t e m of reliability a s s u r a n c e for t h e p r o d u c t i o n of integrated circuits. T h i s s y s t e m is characterized in detailed observations to the process data, e.g. yield, and it is worked o u t by t h e c o m p u t e r . In this paper, we first introduce t h e conventional reliability a s s u r a n c e s y s t e m of o u r prod u c t s a n d discuss its shortcomings, citing s o m e examples. Next, t h e idea a n d t h e outline of the n e w reliability a s s u r a n c e s y s t e m " C A R A S " are described, and t h e effectiveness of the n e w s y s t e m is p r e s e n t e d with an example.
Variables affecting thermally induced surface r e c o n s t r u c t i o n in A l - m e t a l . E. PHILOFSKY, E. RAVI, E. HALL a n d J. BLACK. Proc. I E E E Re[lab. Phys. Symp.,
AND
RELIABILITY
stress w a v e s . J. R. ADAMS a n d H. L. FLOYD, Proc. I E E E Reliab. Phys. Syrup., L a s Vegas, U . S . A . 31 M a r c h - 2 April (1971). A novel t e c h n i q u e for either destructive or n o n - d e s t r u c t i v e evaluation of t h e m e c h a nical integrity of b e a m lead transistors a n d integrated circuits has been d e m o n s t r a t e d . A F e b e t r o n 705 flash election b e a m m a c h i n e was used to generate t h e r m o mechanical stress waves w h i c h were acoustically c o u p l e d to b o n d e d b e a m lead devices. C o m p u t e r - a i d e d stress wave analysis of t h e s y s t e m was used to calculate t h e stresses generated in t h e individual beams. T h i s allows prediction of failure m o d e s a n d levels. E x p e r i m e n t a l results have d e m o n s t r a t e d that m o s t failure m o d e s can be related to device or b o n d i n g deficiencies, a n d reveal failures w h i c h cannot be easily obtained by other m e t h o d s of testing.
Thermal
excursion
can
cause
bond p r o b l e m s .
M. F. NOWAKOWSKI and F. VILLELLA,Proc. IEEEReliab. Phys. Syrup., L a s Vegas, U.S.A. 31 M a r c h - 2 April (1971). T h e p u r p o s e of this p a p e r is to illustrate t h e failure m o d e caused by t h e r m a l d e f o r m a t i o n a n d h o w t h e r m a l d e f o r m a t i o n affects b o n d integrity. W e d g e b o n d i n g in small-signal transistors, microcircuits a n d L S I circuits is t h e subject of this work. Repeated s w i t c h ing of the devices b e t w e e n h i g h a n d low p o w e r at a rate that allows t h e r m a l expansion a n d contraction in t h e i n t e r c o n n e c t i n g wire causes t h e wire to flex at the p o i n t of reduced cross-sectional area until finally the wire breaks d u e to metal fatigue. It was observed that t h e t h e r m a l d e f o r m a t i o n was related to m a n y factors s u c h as device p o w e r dissipation, c u r r e n t density in t h e wire, wire dress a n d length, t h e r m a l t i m e c o n s t a n t a n d f r e q u e n c y of operation.
D e g r a d a t i o n a n d p a s s i v a t i o n of light e m i t t i n g d i o d e s . R. L. HARTMAN,M. KUHN a n d B. SCHWARTZ, Proc. I E E E Reliab. Phys. Syrup., L a s Vegas, U . S . A . 31 M a r c h - 2 April (1971). D e g r a d a t i o n of electrol u m i n e s c e n c e of G a P light e m i t t i n g diodes has been significantly reduced by chemical passivation of t h e surfaces. Passivation was achieved by p r o d u c i n g an a m o r p h o u s native oxide over t h e exposed surfaces of completed diode structures. D e g r a d a t i o n characteristics of passivated a n d u n p a s s i v a t e d devices will be d i s c u s s e d a n d qualitatively explained in t e r m s of a simple model.
L a s Vegas, U.S.A. 31 M a r c h - 2 April (1971). T h e surface of a l u m i n u m metallization on silicon devices can reconstruct with elevated t e m p e r a t u r e t r e a t m e n t s d u e to t h e relief of c o m p r e s s i v e stresses i n d u c e d by t h e r m a l e x p a n sion differences b e t w e e n a l u m i n u m and silicon. T h i s reconstruction can cause reliability p r o b l e m s because of t h e d e v e l o p m e n t of t h i n regions in t h e metal. Also, in multilayer cirouits, hillocks can p u n c h t h r o u g h the oxide layer a n d cause electrical shorts. T h e effects of grain size a n d alloying additions on this surface reconstruction are p r e s e n t e d a n d discussed in this study.
Aluminum-aluminum o x i d e m e t a l l u r g y for e n h a n c e d e l e c t r o m i g r a t i o n r e s i s t a n c e in m o n o l i t h i c circuits. S. M. DESHPANDE,Proc. I E E E Reliab. Phys. Symp., L a s Vegas, U . S . A . 31 M a r c h - 2 April (1971).
E v a l u a t i o n of the m e c h a n i c a l integrity o f b e a m lead devices and bonds using thermomechanical
* M e c h a n i s m s a n d m o d e s o f failure in s i l i c o n planar s e m i c o n d u c t o r d e v i c e s . F. N. SINNADURAI,
Because of its relatively h i g h creep resistance, A1 + A1 sO 3 alloy has been s h o w n to exhibit superior electromigration resistance. T h i s p a p e r reviews the r.f. s p u t t e r i n g d e p o sition t e c h n i q u e of t h e alloy films, feasibility of a l u m i n u m - a l u m i n u m oxide alloy m e t a l l u r g y for monolithic circuits a n d increased electromigration resistance data obtained on t h e alloy films.