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High-value MOS capacitor arrays in ultradeep trenches in silicon
/¢IICX~II.I~I'ilON~ ELSEVIER
MicroelectronicEngineering 53 (2000) 581-584 www.elsevier.nl/locate/mee
High-value MOS capacitor arrays in ultradeep trenches in silicon F. Roozeboom, R. Elfrink, J. Verhoeven,J. van den Meerakker and F. Holthuysen Philips Research, Prof. Holstlaan 4, 5656 AA Eindhoven,The Netherlands A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of ~tm deep with a width and pitch of a few ~tm. The hundredfold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 ~tF. The specific capacitance was as high as 100 nF/mm2. 1. INTRODUCTION One of the problems anticipated in future microelectronic RF devices - in particular in wireless telecommunication and electronic data processing - is that further down-scaling in combination with clocktime reduction below 1 ns will seriously affect the reliability and signal integrity of these devices due to cross-talk and parasitic RC delay [1]. This may lead to a large supply and substrate bounce ('switching noise'). The S1A National Technology Roadmap for Semiconductors mentions this fundamental problem and indicates 'integration of active devices ... with high quality passive devices' as the superior future solution [2]. Today, high-performance processors have already decoupling capacitance on-board, often as discrete ceramic capacitors of 100-1000 nF, placed very close to the chip. However, as ICs have become more complex, many of the board and package level problems have been transferred to the chip level. For that reason modern, advanced microprocessor contain onchip decoupling capacitances of 100 nF or more [1,3]. Within the next decade a relatively large part (5 % or more) of the expensive chip area must be 'sacrificed' to maintain reliability and signal integrity at a sufficiently high level [1]. The idea of using high-value MOS capacitors made in silicon with enlarged surface was first proposed by Bean [4], who etched ridges in Si,
and recently by Lehmann et al. who used arrays of ultradeep trenches [5]. This paper reports on the fabrication and characterization of high-value MOS capacitor arrays in ultradeep trenches in 6-inch Si. An essential process step here is the photoelectrochemical etching of arrays of ultradeep trenches with aspect ratio of the order of 100 in 6-inch lightly n-doped Si wafers in aqueous HF solution. Figure l shows schematically a chip with a hexagonally packed array of cylindrical trenches containing the stack of layers that compose the MOS capacitor. lower electrode
m~
ne Io~
ek Si Figure 1. MOS capacitor scheme (not to scale).
2. TRENCH ETCHING THEORY Trench formation during anodic dissolution of n-type silicon in aqueous HF has been studied long ago in our labs by Theunissen [6] and explained by a depletion of the porous region due to space charge effects. The self-adjusting
0167-9317/00/$ - see front matter © 2000 Elsevier Science B.V. All rights reserved. PII: S0167-9317(00)00383-X
582
F. Roozeboom et al. / Microelectronic Engineering 53 (2000) 581-584
trench etching mechanism has been further studied by Lehmann [7], who defined a regular pattern of trench initiation indentations along the slow-etching (l 1 l) crystallographic planes in small (- 1 cm2) Si samples by pre-etching with hot KOH. The anisotropic etching is based on the preferential anodic dissolution of Si in the etch pit regions where the holes are collected more efficiently due to the enhanced electrical field in the space charge layer. When the ratedetermining step for dissolution is controlled by the number of holes, generated by white light illumination of the wafer backside, the pore walls become depleted of the minority carriers (holes) that drive the dissolution, and thus passivated. 3. EXPERIMENTAL 3.1 Trench etching Standard photolithography was used to apply a Si3N4mask with a hexagonally packed array of circular openings with 1.5 ~tm diameter and 3.5 ~tln spacing onto lightly n-doped (10 D.cm) 6inch (100) silicon wafers. This pattern was used for alkaline pre-etching the (lll)-oriented trench initiation indentations. The experimental set-up is shown in Fig. 2. The wafer is placed in a polypropylene holder containing a K2SO4 electrolyte, used for a uniform anodic contact at the wafer backside. The contact is made through a platinum grid anode placed in the electrolyte. The holder is
Figure 2. Photoelectrochemical etching cell.
placed in an aqueous HF solution with the wafer frontside facing the Pt cathode. Tungsten lamps illuminate the wafer backside through transparent polycarbonate windows in the wafer holder and the etch cell. Controlling the lamp power controls the anodic current, which is proportional to the light intensity, in an automated cycle. Typical etch conditions were 7 V bias and 0.75 A, using a 2.5 % (v/v) HF solution, which is circulated through a thermostat by a pneumatic Teflon pump. The etch rate at 20 °C was typically 0.6 ~tm/min. More details can be published elsewhere [8]. 3.2 Device processing and characterization The MOS capacitors were obtained as follows. First, the trench walls were made highly conductive by P indiffusion from a predeposited phosphorus silicate glass layer. Next, the trenches were filled with a nominally 30 nm 'ONO' dielectric layer stack consisting of a thermal oxide, LPCVD nitride and an oxide layer deposited by LPCVD-TEOS. Next, a 0.5 ~tm conductive layer of n-type in situ doped poly-Si was deposited by LPCVD from Sill4 and diluted PH3. Dopant activation is typically done in a 30-minutes furnace anneal step in atmospheric nitrogen at 1000 °C. The contacts for the top and bottom electrodes were made by e-gun evaporative deposition of a 1 lam aluminium layer and wet-etching after photolithographical steps. We designed arrays of capacitors in the range from 1 nF to 1 ~tF by designing dies with the top electrode area ranging from 0.12 x 0.12 to 4.37 x 4.37 mm2 and applying bottom electrodes surrounding the square top electrode surfaces. The bottom electrode contacts around were 100 ~tm wide and 50 ~m apart from the inner top electrode surface (cf. Fig. 1). Structural characterization was done on a Philips XL40-FEG scanning electron microscope. Preliminary electrical testing of the capacitors on wafer level was performed, using a Hewlett-Packard 4194A impedance analyzer with a probe station. A demonstrator capacitor array on chip was packaged in a conventional 18-pins housing.
583
F. Roozeboom et al. I Microelectronic Engineering 53 (2000) 581-584
4. RESULTS Figures 3 and 4 show SEM cross-sections of a typical trench structure and capacitor structures with the ONO dielectric, n-doped poly-Si and A1 contact layers. Figure 3 shows that trenches with 2 p,m diameter, pitch 3.5 ~tm, and depth of 150 gm or more can be etched with uniform trench shape and depth. Note, that a 6-inch wafer contains over a billion of such trenches. Figure 4 shows a uniform layer thickness of the dielectric layer and the n-doped poly-Si layer over the entire trench. The figure shows also that the AI layer is deposited onto the surface and not into the pores. The electrical results in Fig. 5 show a comparison between identical capacitors on a macroporous and on a planar substrate. Obviously the substrate surface enlargement factor of 100 gives rise to an equal increase in capacitance. This enables the design of arrays of trench capacitors ranging from 1 nF to 1 gF, with a specific capacitance of 100 nF/mm 2. For the combination of planar and trench capacitors this range is even from 10 pF to 1 ~tF. The MOS capacitors are fully bipolar: over a range fi'om - 5 to +5 V the impedance vs. voltage remained constant, as shown in Fig. 6.
c)NO d:~!,
l'1
t 5 ~tm ~
I
,
I
(c)
Figure 3. SEM-image of an as-etched trench structure with 150 gm depth.
Figure 4. SEM-images of (a) a complete MOS capacitor structure with 120 x 120 gm 2 top electrode surface, (b) its trench top (b) and (c) trench bottom at 105 pm depth. The irregularities in (a) are due to sample cleavage.
584
F. Roozeboom et al. / Microelectronic Engineering 53 (2000) 581-584 1 .E+03 1 .E+02
k •
.=.
1.E+01
I.E+00
Wk
&
1.E-01
1.E-o2
;;;~
•
1.E-02
"
&trench c a p a c i i o r s -
[ ¶P!~narc'~'~it°r'-
1.E-01 I.E+00 1.E+01 1.E+02 Top electrode surface [mm =]
Figure 5. Capacitance vs. top electrode area for trench and planar capacitors. 1ooo
I0~ Hz loo lO
N
......................................
.10..I,.H~
......................................
.1.HH~
t o.1 o#t
-4
-2
0
2
4
v Iv)
Figure 6. Impedance vs. operation voltage for 10 nF trench capacitors
Figure 7. Trench capacitor array (4 x 27 nF and 3 x 65 nF ) on one chip in an 18-pins package. The capacitor devices are fully MOScompatible; thus they can withstand temperatures up to 200 °C, both during packaging and operation. The capacitor arrays
can be easily packaged (see Fig. 7 for an example) or on-chip integrated (by flip-chip mounting), or mounted in a multi-chip package onto low- and medium voltage signal processors for decoupling and filtering purposes to improve signal reliability. The advantages here are less external connections, lower parasitic losses and component count. 5. CONCLUSIONS MOS capacitors in ultradeep trenches provide a fully CMOS compatible solution into the third dimension for the integration -on-chip or multiple chip module- of decoupling capacitor arrays using a minimum of lateral chip area. Its potential for miniaturization means smaller component size, reduced manufacturing costs per product, low power consumption and integration of more basic functions into one product. ACKNOWLEDGEMENT The experimental contributions of A. Dourson, J. Melai and R. Vrijens are gratefully acknowledged. REFERENCES 1. H.Veendrick, Deep Submicron CMOS ICs, From Basics to ASICS, Kluwer, Deventer, The Netherlands, 1998. 2. The National Technology Roadmap for Semiconductors, 1997, p. 43 and on. 3. C.F. Webb et al., Digest: Int. Solid-State Circuits Conf., 1995, 168. 4 K.E. Bean, IEEE Trans. Electron. Dev. ED-25 (1978) 1185. 5. V. Lehmann, W. H6nlein, H. Reisinger, A. Spitzer, H. Wendt and J. Willer, Thin Solid Films, 276 (1996) 138. 6. M. Theunissen, J. Electrochem. Soc., 119 (1972) 351. 7. V. Lehmann, J. Electrochem. Soc., 140 (1993) 2836. 8. J. van den Meerakker, R. Elfrink, F. Roozeboom and J. Verhoeven, J. Electrochem. Soc., to be published.
MicroelectronicEngineering 53 (2000) 581-584 www.elsevier.nl/locate/mee
High-value MOS capacitor arrays in ultradeep trenches in silicon F. Roozeboom, R. Elfrink, J. Verhoeven,J. van den Meerakker and F. Holthuysen Philips Research, Prof. Holstlaan 4, 5656 AA Eindhoven,The Netherlands A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of ~tm deep with a width and pitch of a few ~tm. The hundredfold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 ~tF. The specific capacitance was as high as 100 nF/mm2. 1. INTRODUCTION One of the problems anticipated in future microelectronic RF devices - in particular in wireless telecommunication and electronic data processing - is that further down-scaling in combination with clocktime reduction below 1 ns will seriously affect the reliability and signal integrity of these devices due to cross-talk and parasitic RC delay [1]. This may lead to a large supply and substrate bounce ('switching noise'). The S1A National Technology Roadmap for Semiconductors mentions this fundamental problem and indicates 'integration of active devices ... with high quality passive devices' as the superior future solution [2]. Today, high-performance processors have already decoupling capacitance on-board, often as discrete ceramic capacitors of 100-1000 nF, placed very close to the chip. However, as ICs have become more complex, many of the board and package level problems have been transferred to the chip level. For that reason modern, advanced microprocessor contain onchip decoupling capacitances of 100 nF or more [1,3]. Within the next decade a relatively large part (5 % or more) of the expensive chip area must be 'sacrificed' to maintain reliability and signal integrity at a sufficiently high level [1]. The idea of using high-value MOS capacitors made in silicon with enlarged surface was first proposed by Bean [4], who etched ridges in Si,
and recently by Lehmann et al. who used arrays of ultradeep trenches [5]. This paper reports on the fabrication and characterization of high-value MOS capacitor arrays in ultradeep trenches in 6-inch Si. An essential process step here is the photoelectrochemical etching of arrays of ultradeep trenches with aspect ratio of the order of 100 in 6-inch lightly n-doped Si wafers in aqueous HF solution. Figure l shows schematically a chip with a hexagonally packed array of cylindrical trenches containing the stack of layers that compose the MOS capacitor. lower electrode
m~
ne Io~
ek Si Figure 1. MOS capacitor scheme (not to scale).
2. TRENCH ETCHING THEORY Trench formation during anodic dissolution of n-type silicon in aqueous HF has been studied long ago in our labs by Theunissen [6] and explained by a depletion of the porous region due to space charge effects. The self-adjusting
0167-9317/00/$ - see front matter © 2000 Elsevier Science B.V. All rights reserved. PII: S0167-9317(00)00383-X
582
F. Roozeboom et al. / Microelectronic Engineering 53 (2000) 581-584
trench etching mechanism has been further studied by Lehmann [7], who defined a regular pattern of trench initiation indentations along the slow-etching (l 1 l) crystallographic planes in small (- 1 cm2) Si samples by pre-etching with hot KOH. The anisotropic etching is based on the preferential anodic dissolution of Si in the etch pit regions where the holes are collected more efficiently due to the enhanced electrical field in the space charge layer. When the ratedetermining step for dissolution is controlled by the number of holes, generated by white light illumination of the wafer backside, the pore walls become depleted of the minority carriers (holes) that drive the dissolution, and thus passivated. 3. EXPERIMENTAL 3.1 Trench etching Standard photolithography was used to apply a Si3N4mask with a hexagonally packed array of circular openings with 1.5 ~tm diameter and 3.5 ~tln spacing onto lightly n-doped (10 D.cm) 6inch (100) silicon wafers. This pattern was used for alkaline pre-etching the (lll)-oriented trench initiation indentations. The experimental set-up is shown in Fig. 2. The wafer is placed in a polypropylene holder containing a K2SO4 electrolyte, used for a uniform anodic contact at the wafer backside. The contact is made through a platinum grid anode placed in the electrolyte. The holder is
Figure 2. Photoelectrochemical etching cell.
placed in an aqueous HF solution with the wafer frontside facing the Pt cathode. Tungsten lamps illuminate the wafer backside through transparent polycarbonate windows in the wafer holder and the etch cell. Controlling the lamp power controls the anodic current, which is proportional to the light intensity, in an automated cycle. Typical etch conditions were 7 V bias and 0.75 A, using a 2.5 % (v/v) HF solution, which is circulated through a thermostat by a pneumatic Teflon pump. The etch rate at 20 °C was typically 0.6 ~tm/min. More details can be published elsewhere [8]. 3.2 Device processing and characterization The MOS capacitors were obtained as follows. First, the trench walls were made highly conductive by P indiffusion from a predeposited phosphorus silicate glass layer. Next, the trenches were filled with a nominally 30 nm 'ONO' dielectric layer stack consisting of a thermal oxide, LPCVD nitride and an oxide layer deposited by LPCVD-TEOS. Next, a 0.5 ~tm conductive layer of n-type in situ doped poly-Si was deposited by LPCVD from Sill4 and diluted PH3. Dopant activation is typically done in a 30-minutes furnace anneal step in atmospheric nitrogen at 1000 °C. The contacts for the top and bottom electrodes were made by e-gun evaporative deposition of a 1 lam aluminium layer and wet-etching after photolithographical steps. We designed arrays of capacitors in the range from 1 nF to 1 ~tF by designing dies with the top electrode area ranging from 0.12 x 0.12 to 4.37 x 4.37 mm2 and applying bottom electrodes surrounding the square top electrode surfaces. The bottom electrode contacts around were 100 ~tm wide and 50 ~m apart from the inner top electrode surface (cf. Fig. 1). Structural characterization was done on a Philips XL40-FEG scanning electron microscope. Preliminary electrical testing of the capacitors on wafer level was performed, using a Hewlett-Packard 4194A impedance analyzer with a probe station. A demonstrator capacitor array on chip was packaged in a conventional 18-pins housing.
583
F. Roozeboom et al. I Microelectronic Engineering 53 (2000) 581-584
4. RESULTS Figures 3 and 4 show SEM cross-sections of a typical trench structure and capacitor structures with the ONO dielectric, n-doped poly-Si and A1 contact layers. Figure 3 shows that trenches with 2 p,m diameter, pitch 3.5 ~tm, and depth of 150 gm or more can be etched with uniform trench shape and depth. Note, that a 6-inch wafer contains over a billion of such trenches. Figure 4 shows a uniform layer thickness of the dielectric layer and the n-doped poly-Si layer over the entire trench. The figure shows also that the AI layer is deposited onto the surface and not into the pores. The electrical results in Fig. 5 show a comparison between identical capacitors on a macroporous and on a planar substrate. Obviously the substrate surface enlargement factor of 100 gives rise to an equal increase in capacitance. This enables the design of arrays of trench capacitors ranging from 1 nF to 1 gF, with a specific capacitance of 100 nF/mm 2. For the combination of planar and trench capacitors this range is even from 10 pF to 1 ~tF. The MOS capacitors are fully bipolar: over a range fi'om - 5 to +5 V the impedance vs. voltage remained constant, as shown in Fig. 6.
c)NO d:~!,
l'1
t 5 ~tm ~
I
,
I
(c)
Figure 3. SEM-image of an as-etched trench structure with 150 gm depth.
Figure 4. SEM-images of (a) a complete MOS capacitor structure with 120 x 120 gm 2 top electrode surface, (b) its trench top (b) and (c) trench bottom at 105 pm depth. The irregularities in (a) are due to sample cleavage.
584
F. Roozeboom et al. / Microelectronic Engineering 53 (2000) 581-584 1 .E+03 1 .E+02
k •
.=.
1.E+01
I.E+00
Wk
&
1.E-01
1.E-o2
;;;~
•
1.E-02
"
&trench c a p a c i i o r s -
[ ¶P!~narc'~'~it°r'-
1.E-01 I.E+00 1.E+01 1.E+02 Top electrode surface [mm =]
Figure 5. Capacitance vs. top electrode area for trench and planar capacitors. 1ooo
I0~ Hz loo lO
N
......................................
.10..I,.H~
......................................
.1.HH~
t o.1 o#t
-4
-2
0
2
4
v Iv)
Figure 6. Impedance vs. operation voltage for 10 nF trench capacitors
Figure 7. Trench capacitor array (4 x 27 nF and 3 x 65 nF ) on one chip in an 18-pins package. The capacitor devices are fully MOScompatible; thus they can withstand temperatures up to 200 °C, both during packaging and operation. The capacitor arrays
can be easily packaged (see Fig. 7 for an example) or on-chip integrated (by flip-chip mounting), or mounted in a multi-chip package onto low- and medium voltage signal processors for decoupling and filtering purposes to improve signal reliability. The advantages here are less external connections, lower parasitic losses and component count. 5. CONCLUSIONS MOS capacitors in ultradeep trenches provide a fully CMOS compatible solution into the third dimension for the integration -on-chip or multiple chip module- of decoupling capacitor arrays using a minimum of lateral chip area. Its potential for miniaturization means smaller component size, reduced manufacturing costs per product, low power consumption and integration of more basic functions into one product. ACKNOWLEDGEMENT The experimental contributions of A. Dourson, J. Melai and R. Vrijens are gratefully acknowledged. REFERENCES 1. H.Veendrick, Deep Submicron CMOS ICs, From Basics to ASICS, Kluwer, Deventer, The Netherlands, 1998. 2. The National Technology Roadmap for Semiconductors, 1997, p. 43 and on. 3. C.F. Webb et al., Digest: Int. Solid-State Circuits Conf., 1995, 168. 4 K.E. Bean, IEEE Trans. Electron. Dev. ED-25 (1978) 1185. 5. V. Lehmann, W. H6nlein, H. Reisinger, A. Spitzer, H. Wendt and J. Willer, Thin Solid Films, 276 (1996) 138. 6. M. Theunissen, J. Electrochem. Soc., 119 (1972) 351. 7. V. Lehmann, J. Electrochem. Soc., 140 (1993) 2836. 8. J. van den Meerakker, R. Elfrink, F. Roozeboom and J. Verhoeven, J. Electrochem. Soc., to be published.