Research on optimizing the noise figure of low noise amplifier method via bias and frequency

The Journal of China Universities of Posts and Telecommunications August 2011, 18(4): 118–122 www.sciencedirect.com/science/journal/10058885

http://jcupt.xsw.bupt.cn

Research on optimizing the noise figure of low noise amplifier method via bias and frequency ZHANG Li-jun1, LI Li-nan2 ( ) 1. The School of Urban Rail Transportation, Soochow University, Suzhou 215021, China 2. School of Electronic and Information Engineering, Beijing Jiaotong University, Beijing 100044, China

Abstract

In this paper, we present the design of an integrated low noise amplifier (LNA) for wireless local area network (WLAN) applications in the 5.15–5.825 GHz range using a SiGe BiCMOS technology. A novel method that can determine both the optimum bias point and the frequency point for achieving the minimum noise figure is put forward. The method can be used to determine the optimum impedance over a relevant wider operating frequency range. The results show that this kind of optimizing method is more suitable for the WLAN circuits design. The LNA gain is optimized and the noise figure (NF) is reduced. This method can also achieve the noise match and power match simultaneously. This proposal is applied on designing a LNA for IEEE 802.11a WLAN. The LNA exhibits a power gain large than 16 dB from 5.15 to 5.825 GHz range. The noise figure is lower than 2 dB. The OIP3 is  8 dBm. Also the LNA is matched to 50 ȍ input impedance with 6 mA DC current for differential design. Keywords LNA, SiGe BiCMOS, noise figure, WLAN

1

Introduction 

The growth of wireless telecommunication industry has translated into very strict requirements concerning the performance of the microwave modules. The circuit must meet the requirement such as low noise figure and also high linearity due to the overcrowding spectrum. In additionally, for wireless use, the power consumption also must be kept at a low level. SiGe BiCMOS technology has been proved to be a very promising process to construct wireless communication systems [1]. Moreover, SiGe BiCMOS technology is silicon based technology that takes advantage of the maturity of silicon processing techniques and results into very low cost components [2–3]. The technology of 47-GHz SiGe BiCMOS is used to build a LNA in RF front end in this paper. It can reach the performance in certain frequency range which the technology of GaAs achieves. The LNA is designed to be used in wireless Received date: 29-12-2010 Corresponding author: LI Li-nan, E-mail: [email protected] DOI: 10.1016/S1005-8885(10)60093-3

communication systems such as IEEE 802.11a WLAN. In the design, a novel method is proposed to determine the optimum bias current and also to do the noise match. For the LNA will be a building block of the integrated direct conversion transceiver, a differential structure is introduced [4].

2 Method for determining the optimum bias current and doing the noise match The LNA is the most critical building block in modern integrated RF transceivers for wireless communication [5–8]. It is directly connected to the antenna or RF bandpass filter. It must enhance input signal levels at gigahertz frequencies while preserving the signal to noise ratio (SNR) and avoiding intermodulation distortion. That is to say the noise figure and the linearity are very important for LNAs. Another important consideration is LNA’s gain and input impedance matching. The LNA is designed to be used in an integrated transceiver. So it can directly be connected to the mixer and no output matching is required. However the matching network at the LNA input greatly determines the noise figure. The noise figure can be minimized by choosing the optimum source

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impedance [9]. This can be achieved by optimum noise matching network. In this paper, the technology can provide the on chip integrated inductor. And this approach allows low noise figure and high return loss to be achieved at the same time. This paper will focus on the cascade LNA, which give the best basic structure for good trade-off between low noise, high gain, and stability [10]. We start by reviewing the basic amplification stages, common-gate (CG) and common-source (CS). For each circuit, we derive equations, with different levels of approximation, for the gain, input matching and noise figure. By comparing the results obtained with the different equations with those obtained by simulation, we select the level of approximation required for the frequency range in which we are interested. Fig. 1 shows a simplified schematic of a cascade amplifier. Its use as a LNA and it has the advantage of high operating frequency and excellent frequency stability at high gain. This is because of the common base transistor Q2, which provides high isolation between input and output terminals and avoids Miller amplification of the base-collector capacitor of Q1 [11]. Drawbacks with respect to the simple common emitter amplifier are a slightly higher noise figure [12] and a lower output swing, which are both due to the transistor Q2. The circuit needs a proper input matching network while the output matching can be achieved by adjusting the impedance of Zc. In this paper a resonant load is used and it can improve the output swing, noise figure, and frequency capability. It is evident that to minimize the noise in high frequency range, it is proper to use transistors featuring low base and emitter resistance, high cut-off frequency and high current gain. The SiGe HBT fulfills all these requirements. The noise figure of LNA depends on the input load termination of the transistor through the following equation:

Fig. 1

FN

FNmin 

Simplified cascade low noise amplifier

Rn Ys  Ysopt Gs

2

(1)

where Ys=Gs+jBs is the input load termination, NFmin is the

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factor of minimum noise, Rn is the equivalent resistance of noise and Ysopt is the source admittance at the input giving the minimum noise figure possible (it is called the noise matching impedance). FNmin can be derived as the following expression [12]:

FNmin

1

n

E0



f fT

§ 2IC f 2 · n 2 f T2 ( rE  rB ) ¨1  T 2 ¸  2 VT © E0 f ¹ E0 f

(2)

where the E 0 , n, fT, rE, rB, VT are DC current gain, collector current ideality factor, unity current gain frequency, series emitter resistance, total base resistance and thermal voltage respectively. The value of n approximately equals to one. And the Ysopt and Rsopt can be expressed by these equations: § f § IC f 2 · n 2 f T2 n· ¨ (rE  rB ) ¨1  T 2 ¸  j ¸ (3) Ysopt 2 2¸ f T Rn ¨ 2VT © E 0 f ¹ 4E 0 f © ¹

Rsopt

§ IC f 2 · n 2 f T2 ( rE  rB ) ¨1  T 2 ¸  2 2VT © E 0 f ¹ 4E 0 f

Rn f T § f IC f 2 · n2 § f2 · (rE  rB ) ¨1  T 2 ¸  ¨1  T 2 ¸ 2VT © E0 f ¹ 4 © E0 f ¹

(4)

All noise parameters are nonlinear functions of emitter width wE via the term Ic(rE+rB). There are two parameters must be determined to achieve the minimum noise figure. The two parameters are the DC current and the input transistor size. So there is some difficulty to determine the two parameters simultaneously. But at the integrated circuit process, the minimum of the device is fixed. And that can solve this problem in practical. So the only thing left to do is to determine the optimum DC collector current density [13]. By taking the first derivative of FNmin with respect to collector current density Jc yields: wFNmin 0 (5) wJ C

The corresponding NFopt is obtained by substituting the value of Jcopt into Eq. (2). The followed step is to adjust the size of the input transistor. This is to select the device properly, it is possible to set Rsopt=50 ȍ. This choice allows simultaneous maximum power and minimum noise figure match. Note that in order not to disturb the value of the NFopt while varying the device size, the optimum device collector current density Jcopt, should be maintained. The last step is to add the degeneration inductor and base series inductor to complete the input matching [13]. This approach is adopted by many designs to achieve the best noise performance on RF LNA design. But it is based on the design for a frequency point a narrow frequency range. It is assumed the Rsopt is not varied with frequency or the variation is very small. So that

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the last term of Eq. (1) can always be maintained to zero. But in order to design some cases such as IEEE 802.11a WLAN, the operating frequency range is from 5.15 to 5.825 GHz, the sampling bandwidth or 610 MHz, this approach can not lead to an optimum design. For these design steps can just make the FN=FNmin at one frequency point. Even if it achieves the minimum noise figure at one matched frequency point, the overall noise performance of the low noise amplifier is not at the optimum biasing and matching case. In this paper, we proposed a method that can consider the optimum impedance over wider operating frequency range. It considers the current density and also the operating frequency of the LNA. For the NF is the function of both Jc and f. And it is known that to get the minimum value of a f(x,y), it must be satisfied that f ’x and f ’y equal to zero. So it can be derived that of the equations are that frequency: 2· wFN w § Rn (6) Ys  Ysopt ¸ 0 ¨ FNmin  wf wf © Gs ¹ And bias current: 2· wFN w § Rn (7) Ys  Ysopt ¸ 0 ¨ FNmin  wJ c wJ c © Gs ¹ On the matching case, the input impedance of the LNA is: § 1 · Z in Rin  jX in 2ʌf T Le  j¨ 2ʌfLe  (8) ¸ 2ʌfCʌ ¹ © By adding the inductor Lb connected to base of the input device, the optimum noise reactance of the amplifier is transformed to 0 [12]. So the last term of both Eqs. (6) and (7) will turn to: Ys  Ysopt Gs  Gsopt (9) In practical design, with the device is defined the emitter width by process, the rE+rB will be replaced by (rE+rB)u which represent the resistance of the input device. The relation between the rE+rB and the (rE+rB)u is expressed by this equation: 1 rE  rB (10) (rE  rB )u MN The parameter N represents the emitter stripe ratio of the device geometry relative to the unit device. The parameter M represents the number of devices of the same geometry used in parallel to increase the overall device size. And the Rn is: · 1 § n 2VT  (rE  rB )u ¸ Rn (11) ¨ MN © 2 J c ¹ Resolve the Eqs. (6) and (7). We get the relations between the Jc and the f: Jc

2ʌ(c je  c jc )VT

E0 f 2 2 4ʌ E 0W F2 f 2  1

(12)

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The c je is the capacitance of the emitter junction, and the

c jc is the capacitance of the collector junction. By using Eq. (12) we obtain the optimum frequency match at 5.56 GHz, associate optimum current density is 0.27 mA/um². The total current is 5.88 mA for whole differential circuit LNA.

3 Design of the IC Although the single-ended LNA architecture consumes less power dissipation and needs the less number of passive and active devices [14]. But this type of circuit has one important shortcoming which is its sensitivity to parasitic ground inductance. A differential LNA can solve this problem, however, for equal total power consumption; the noise figure of the differential LNA is higher than a single-ended one. A differential input leads to reduced harmonic distortion and to better power supply and substrate noise rejection. And the differential LNA has a good OIP2 performance than a single-ended one [15–17]. The differential LNA must be connected to the antenna by an off-chip balun which is shown in Fig. 2 [18].

Fig. 2

A differential LNA structure and off-chip balun

With the matching current density, device size, and frequency point is determined, the overall input matching network can be completed. The topology of the circuit is shown in Fig. 3.

Fig. 3

Simplified diagram of the low noise amplifier

The value of the Le is to match the real part of the impedance. And it can be calculated by the equation. Z0 Le (13) 2ʌf T It can be demonstrated using the theory of correlated noise sources in series-series feedback circuits that, if Le is a lossless inductor it will not change the value of Rsopt but it will

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affect the optimum reactance Xsopt. When the emitter inductor is added to the circuit, the Xsopt will turn to: c X sopt X sopt  2ʌfLe (14) The Xsopt can be determined by Eq. (3). Simultaneous noise and input impedance match is finally obtained by connecting an inductor Lb in the base. It cancels out the reactance due to the input capacitance of the device, and, at the same time, it transforms the optimum noise reactance of the amplifier to 0. It must to be noticed that Lb is constructed by bond wire inductors. For the input of the LNA will connect to antenna or off chip filter. The package that would affect the circuit performances must be taken into account. The design methodology we used can guarantees optimal noise and input impedance match with the simplest matching network in all operating frequency range. An LNA design can be completed by adding a suitable matching network in the collector in order to maximize the power gain or voltage gain. The simulation results are obtained by CADENCE Spectre RF. The impact of the finite Q of inductor can be reasonably well accounted for in simulations if an appropriate inductor model is employed. Also, in the previous analytical expressions, the series resistance of the base and the emitter inductors can be respectively incorporated into the base and the emitter resistance of the transistor. In order to minimize the parasitic elements introduced by connecting traces, the components are placed as close as possible to one another and also the connecting traces are kept short. However, the inductors must be kept apart from each other for some distance. This will guarantee the mutual inductance is small. Differential paths are made symmetrical and differential pair components are placed closed together.

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And the circuit has been measured at the wafer level by open cap package and differential microwave probes. The measurement has been performed by HP 8510C network analyzer and HP 8517B S parameter test set. The noise figure is measured by Agilent N8975A NFA series noise figure analyzer. The results of gain and noise figure are shown in Figs. 5 and 6 respectively. The line is the simulation results and the points are the measurements results. The measurements indicate a maximum gain value of about more than 16 dB. This value is slightly smaller than the simulation result. The explanation is related to the inductor model, which maybe larger than expected so the degeneration inductor will introduce more feed back and lower the power gain. The noise figure of the low noise amplifier is lower than 2 dB. And the simulation result is lower than 1.7 dB. Generally there is excellent agreement between simulation and measurement results. The linearity of the circuit is defined by its OIP3, which is shown in Fig. 7.

Fig. 5 Gain of the low noise amplifier

Results and discussion Fig. 6 Noise figure of the low noise amplifier

The circuit is fabricated on 0.35 um SiGe BiCMOS technology. The photo of the circuit is shown in Fig. 4.

Fig. 7 OIP3 of the low noise amplifier

The measured OIP3 is closed to  8 dBm. And also there is a good agreement between the measurement results and the simulation results. By adding the emitter degeneration Fig. 4

Chip photo of the low noise amplifier

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inductor, the LNA achieve the enough linearity for the wireless LAN use.

5

Conclusions

A novel design method is presented on designing the low noise amplifier for IEEE 802.11a WLAN use. The optimum bias current density is derived. And the frequency point at which the matching network will be designed is determined. With the device size and the added inductor, a network which simultaneously matched the minimum noise figure and the input impedance is completed. The matched network allows dominant noise contributions to be reduced and a very low noise figure to be achieved. In the SiGe BiCMOS technology, the gain of the LNA is more than 16dB, and the noise figure is lower than 2 dB. The OIP3 of the LNA is  8 dBm. The measurement of the circuit has very little difference with the simulation results. Generally there is a good agreement between the measurement and the simulation. And Comparing with the LNAs in prior works [19–20], as shown in Table 1, we can obtain the same gain and better noise figure of LNA. Table 1 Performance comparing of LNAs with SiGe BiCMOS and GaAs technology LNA SiGe BiCMOS (Our work) SiGe BiCMOS (Prior work 1 [19]) GaAs (Prior work 2 [20])

Gain/dB 16.00 16.07 15.10

FN/dB 2.00 2.82 3.80

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(Editor: ZHANG Ying)