- Email: [email protected]
Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach
Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach Fazel Sharifi a, Mohammad Hossein Moaiyeri a, Keivan Navi a,n, Nader Bagherzadeh b a b
Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran Department of Electrical Engineering and Computer Science, University of California, Irvine, United States
art ic l e i nf o
a b s t r a c t
Article history: Received 24 November 2014 Received in revised form 31 July 2015 Accepted 29 September 2015
In this paper energy-efficient multiple valued logic (MVL) circuits based on carbon nanotube field effect transistor (CNTFET) are proposed. These circuits are designed based on the unique properties of CNTFETs, such as having same mobility for electrons and holes and also capability of adopting desirable threshold voltage by adjusting the CNTs diameters. The proposed designs have high driving capability, larger noise margins and higher robustness as compared to the previous CNTFET-based designs. The proposed quaternary circuits are examined using HSPICE simulator with the standard CNTFET technology. Simulation results demonstrate more energy-efficient and robust operation of the proposed designs, as compared to the other state-of-the-art CNTFET-based MVL circuits, recently presented in the literature. According to the simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45% lower power-delay product (PDP), respectively as compared to their state-of-the-art counterparts. In addition, the proposed QNOT, QNAND and QNOR circuits have the average PDP improvements of 79%, 42% and 61%, respectively, as compared the other recently presented CNTFET-based quaternary designs. & 2015 Elsevier Ltd. All rights reserved.
Keywords: Nanoelectronics Multiple valued logic (MVL) CNTFET Low-power design
1. Introduction Digital computation is generally performed on two-valued (binary) logic. Powerful computational elements and tools have already supported binary logic to reach its present status. Multiple-valued logic (MVL) is an alternative logic which uses more than two logical values. MVL circuits have attracted the attention of researchers, due to some of their important features related to reduction of the number of interconnections and increased information content per unit area. In other word, MVL allows more information to be transmitted over a given set of lines or to be stored on a given register length, thus reducing the complexity of interconnects and chip area and achieving simplicity and energy efficiency in digital design [1–4]. Among MVL systems, using e base (eE 2.718) leads to the most efficient implementation of the switching systems [1]. However, due to the restrictions on hardware implementation, designers are limited to use natural numbers as the radices for computations. On the other hand, power-of-two radices take advantage of simple conversion between MVL signals and binary signals, generated by the existing binary circuits. Therefore researchers focus on radices 3 and 4 for hardware implementation. n
Corresponding author. E-mail address: [email protected] (K. Navi).
Carbon nanotube field effect transistor (CNTFET) is a promising alternative to silicon transistor for achieving low power and high performance. CNTFET avoids most problems of nanoscale MOSFET technology, such as very high leakage power dissipation, reduced gate control and velocity saturation [5,6]. The other advantage of CNTFET is that the threshold voltage of a CNTFET is determined dominantly based on the diameter of its CNT channels. Hence, multiple-threshold circuits can be achieved by utilizing CNTFETs with different diameters. This property is very useful in designing voltage-mode MVL circuits [7,8]. Some MOSFET and CNTFET-based MVL circuits, specifically for ternary and quaternary logics, have been presented so far in the literature [9–19]. However, they have some critical drawbacks such as using very large ohmic resistors [9,10], requiring obsolete depletion-mode MOSFET [11–16], high static power consumption [17–19] non-full swing nodes [9,10] and limited fan-out [19]. In this study, energy-efficient quaternary gates tolerant to process, voltage and temperature variations are proposed for nanoelectronics, which are designed based on the complementary CNTFET style. The rest of the paper is organized as follows: Section 2 briefly reviews the CNTFET device. The proposed designs are described in Section 3. In Section 4, the simulation results, analyses and comparisons are presented and finally Section 5 concludes this paper.
http://dx.doi.org/10.1016/j.mejo.2015.09.018 0026-2692/& 2015 Elsevier Ltd. All rights reserved.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
2
Table 1 The truth table of standard ternary NOT, NAND and NOR. a
b
STNOT (a)
STNAND (a,b)
STNOR (a,b)
0 0 0 1 1 1 2 2 2
0 1 2 0 1 2 0 1 2
2 2 2 1 1 1 0 0 0
2 2 2 2 1 1 2 1 0
2 1 0 1 1 0 0 0 0
and p þ for pCNTFET. MOSFET-like CNTFET has very high ION/IOFF ratio which makes it suitable for high-performance and energyefficient applications [21]. In this paper MOSFET-like CNTFETs are used for designing and simulating the circuits.
Fig. 1. Schematic of CNTFET.
2. Carbon nanotube field effect transistor (CNTFET) Carbon nanotube (CNT) is a sheet of graphene rolled up along a wrapping vector, which can be single-wall (SWCNT) or multi-wall (MWCNT). Single-wall CNT is a single nanotube and multi-wall CNT is made of two or more coaxial nanotubes. Rolling up the graphene sheet into a tube is assumed based on a vector called the chiral vector (n1, n2). Based on (n1, n2), if n1 n2 ¼3k (kA Z), then SWCNT becomes conductor and otherwise it becomes semiconductor. Conductive CNTs are used as on-chip interconnects and semiconducting CNTs are used as the channel of transistors [7]. The schematic of a typical CNTFET device is illustrated in Fig. 1. The gate width of a CNTFET (Wgate) is approximately calculated based on the following equation: W gate MaxðW min ; N PitchÞ
ð1Þ
where Pitch is the distance between the centers of two neighboring SWCNTs under the same gate, Wmin is the minimum gate width, determined by lithography and N is the number of nanotubes under the gate. The threshold voltage of a CNTFET is an inverse function of the diameter of its CNTs. This capability is utilized to adopt the desired threshold voltage (Vth) by choosing the correct DCNT. The CNTFET threshold voltage is calculated based on Eq. (3). pffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3a0 n1 2 þn1 n2 þ n2 2 DCNT ¼ 0:0783 n1 2 þ n1 n2 þ n2 2 ð2Þ
π
V th
Ebg a0 V π 0:43 ¼ 2e eDCNT DCNT ðnmÞ
ð3Þ
where e is the unit electron charge, Ebg is the CNT bandgap, a0 ( 0.142 nm) is the carbon to carbon bond length in a CNT and Vπ ( 3.033 eV) is the carbon π–π bond energy in the tight bonding model [20]. Based on the type of connections between source/drain regions and CNT channels and the type of source/drain regions there are three main categories of CNTFETs. The first type is Schottky Barrier CNTFET (SB-CNTFET) which has metallic source/drain regions. In this type of CNTFET, the Schottky barrier junctions limit the transconductance in the ON state and increase the reverse currents in the OFF state; thus ION/IOFF ratio becomes rather low. SBCNTFET is appropriate for medium to high-performance applications. The second type of CNTFET is the band-to-band tunneling CNTFET (T-CNTFET) with CNT source and drain regions with opposite doping types. T-CNTFET has super cut-off characteristics and also has low ON current. T-CNTFET is suitable for low stand-by power application but it is not appropriate for high-performance applications. The third type of CNTFETs is the MOSFET-like CNTFET, in which source and drain CNT regions are doped n þ for nCNTFET
3. Proposed designs 3.1. Ternary circuits In this section new ternary circuits based on CNTFETs are presented. The truth table of ternary functions is shown in Table 1. Ternary logic includes three significant logic levels which can be considered as “0”, “1” and “2” symbols; these symbols are counterpart to 0, ½VDD and VDD voltage levels respectively. The proposed ternary inverter circuit is shown in Fig. 2. Based on Eqs. (1) and (2), for the CNTFETs of this design with the diameters of 0.626, 0.783 and 1.487 nm, the chiral numbers would be (8,0), (10,0) and (19,0) and the threshold voltage values (|Vth|) would be 0.686 V, 0.559 V and 0.293 V, respectively. First consider the input voltage is near 0. For this value the output of inverter1 and inverter2 is VDD, so T3 is OFF and T1 is ON and consequently the output voltage will be VDD. When the input voltage is ½VDD, the output of first and second inverters is 0 and VDD respectively; therefore T3 and T4 are ON and the output voltage is ½VDD. Finally when the input voltage is VDD, output of both inverters is 0 and T4 is OFF, so T2 is ON and output voltage is 0. Based on the STNOT design methodology, STNAND and STNOR circuits are proposed which are shown in Figs. 3 and 4 respectively. Transient simulation results of the proposed STNOT, STNAND and STNOR are plotted in Fig. 5. These results, which are obtained by HSPICE simulations, show the correct operation of the proposed ternary circuits. 3.2. Quaternary circuits In this section, new quaternary logic gates including a quaternary inverter (QNOT), a quaternary NAND (QNAND) and a quaternary NOR (QNOR) are proposed. Quaternary logic consists of four significant logic levels which can be represented by “0”, “1”, “2” and “3” symbols. These logic levels are commonly counterpart to 0 V, ⅓VDD, ⅔VDD and VDD voltage levels, respectively. The functionalities of the quaternary gates can be described by Eqs. (4)–(6). QNOTðaÞ ¼ 3 a
ð4Þ
QNANDða; bÞ ¼ Minða; bÞ ¼ QNORða; bÞ ¼ Maxða; bÞ ¼
3a
if
3b
otherwise
3a 3b
arb
if a Zb otherwise
ð5Þ
ð6Þ
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
3
VDD
VDD T1 D=0.626nm IN D=0.626nm
STNOT
Dn=1.487nm
T3
1
T2
Dp=0.783nm
B
D=0.626 nm
A
D=0.626 nm Dn=0.783nm
IN
A
STNOR
T4
2 Dn=0.783nm
A
D=0.626 nm
Dp=1.487nm
B
B
1/2 VDD Dn=0.783nm
Fig. 2. The proposed ternary inverter.
Dp=0.783nm
Dp=0.783nm
A
B
VDD
Dn=1.487nm
A
1/2 VDD
B
D=0.626 nm
Dn=1.487nm
Fig. 4. The proposed ternary NOR.
Dn=1.487nm
A
D=0.626 STNAND nm
A Dp=0.783nm
B
D=0.626 nm
B Dn=1.487nm
Dp=1.487nm
Dp=1.487nm
B
A Dn=0.783nm
Dn=0.783nm 1/2 VDD Fig. 3. The proposed ternary NAND.
The proposed quaternary inverter, which can be considered as the cornerstone of the other proposed quaternary gates, is shown in Fig. 6. The operation of the proposed quaternary inverter gate can be briefly described as follows: when the input voltage is around 0 V, T1 is ON and T2–T5 are OFF. So the output voltage will be VDD. When the input voltage is around ⅓VDD, T1, T2 and T5 are OFF and T3 and T4 are ON and consequently the output voltage will be ⅔VDD. When the input voltage is around ⅔VDD, T1, T2 and T3 are OFF and T5 and T6 are ON. Consequently the output voltage will become ⅓VDD. Finally, if the input value becomes VDD, T1, T3 and T6 become OFF and T2 becomes ON and consequently the output is discharged to 0. Based on the proposed method for designing the QNOT circuit, a new quaternary NAND and a new quaternary NOR are also introduced. The operation principles of these two circuits are similar to the proposed quaternary inverter. The schematic of the proposed QNAND and QNOR circuits is shown in Figs. 7 and 8, respectively.
Operation of the proposed quaternary NAND can be summarized as follows: While both inputs are around VDD, T3 and T4 are ON, so the output will be 0. While one of the inputs is around ⅔VDD and the other one is equal or greater than ⅔VDD, T9, T10 and at least one of the T11 and T12 are ON based on the threshold voltage of the inverters connected to the transistors gate, therefore the output is ⅓VDD. If one of the inputs is around ⅓VDD and the other one is equal or greater than ⅓VDD, T7, T8 and at least one of the T5 and T6 are ON, so the output will be ⅔VDD. Moreover while one or both of the inputs is around 0, T1 or T2 are ON and other paths to the output are disconnected (T7 or T8, T9 or T10 are OFF), consequently output is VDD. The operation of the proposed QNOR is similar to QNAND circuit. It is worth mentioning that only two distinct diameters are utilized for the CNTFETs of the proposed quaternary designs, whereas the previous CNTFET-based quaternary gates have used at least three distinct diameters. This alleviates sensitivity to process variations and enhances manufacturability. In addition, the proposed quaternary 2-input NAND and NOR gates can also be extended to quaternary NAND and NOR circuits with more than two inputs by extending the proposed complementary CNTFET-based structures of Figs. 7 and 8. The transient responses of the proposed QNOT, QNAND and QNOR are shown in Fig. 9, which authenticate the correct operation of the proposed circuits.
4. Simulation results and comparisons In this section, the proposed designs are comprehensively examined and compared with the other state-of-the-art CNTFETbased designs. The circuits are simulated using Synopsys HSPICE with the commonly used compact SPICE model for unipolar MOSFET-like CNTFETs including all the non-idealities and parasitics [22–24] at 32 nm technology. Simulations are conducted at different power supplies and also at different temperatures to consider the voltage and temperature variations.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
4
Fig. 5. Transient response of the proposed STNOT, STNOR and STNAND.
2/3 VDD
2/ 3 VDD
T3 VDD
T4
T1 D=0.626nm IN
T5
D=2.27nm
B
D=0.626nm
Dn=2.27nm D=0.626nm QNOT D=2.27nm
A
D=2.27 nm
VDD
D=2.27nm
T2
T6
T5
T1
IN
Dp=2.27nm
D=2.27nm
T2
A
B T8
B
D=0.626 nm
A
T3 D=0.626nm
A
1/3 VDD Fig. 6. The proposed quaternary inverter.
The results of the simulations at 32 nm technology node and 0.9 V supply voltage including the worst-case delay, the average power consumption and the power-delay product (PDP) of the cascaded ternary and quaternary designs are presented in Tables 2 and 3, respectively. According to the simulation results, the proposed designs consume lower power and have lower PDP compared to the state-of-the-art CNTFET-based designs. The CNTFET-based circuits also have been simulated at 22 nm technology node and 0.8 V supply voltage. The results of this simulation are given in Tables 4 and 5 for the ternary and quaternary designs, respectively. According to the simulation results, the proposed designs consume lower power and are more energyefficient as compared to the state-of-the-art CNTFET-based designs even at 22 nm technology.
Dn=2.27nm
T9 D=0.626nm
A
D=2.27nm QNAND
T10
T4 B
Dp=0.626nm
D=2.27nm
T6 D=2.27nm
Dn=2.27nm
T7
D=0.626nm
Dp=2.27nm T11
B
B
D=2.27nm
T12
Dp=2.27nm
D=2.27 nm
A Dn=0.626nm
Dn=0.626nm 1/ 3 VDD Fig. 7. The proposed quaternary NAND.
Figs. 10 and 11 compare the performance of the designs at 32 nm technology and 0.9 V voltage considering different supply voltages and temperatures respectively. According to the results, the proposed quaternary designs have lower PDP at all supply voltages and temperatures compared to the other designs. The
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
proposed STNOT has higher PDP than other designs at supply voltage of 0.8 V. Since the results of ternary designs with pseudon-type CNTFETs [18] are very higher than the other designs we eliminate them in upcoming figures. The operation and performance of the ternary and quaternary gates are also examined in the presence of process variations. Nanotube density variations, mainly resulted from variations in the spacing between CNTs on the substrate (Pitch) and variations in the surviving CNT count after metallic CNT removal techniques, are proven experimentally to be the dominant source of variation 2/3 VDD
D=2.27 nm
B
A
Dn=2.27nm
B
D=0.626nm
A
D=0.626nm
in CNTFET circuits [25]. In addition, diameter variation is a significant issue in multi-diameter CNTFET circuits [17,26]. As a result, the Monte Carlo simulation has been conducted to evaluate these process variations with up to 715% Gaussian distributions and variation at the 73σ level. Figs. 12 and 13 demonstrate the maximum PDP variation of the designs in the presence of CNT density and diameter variations, respectively. According to the results, the pseudo-n-type QNOT [18] does not work when the diameter deviation reaches 15%. In
Table 2 Simulation results of the two cascaded ternary circuits (@ 32 nm and 0.9 V).
Dp=0.626nm
Dp=0.783nm VDD
5
Dn=2.27nm D=2.27nm
B
D=2.27nm
A
Cascaded ternary designs
Delay (e-12 s)
Power (e-6 W)
PDP (e-18 J)
Proposed STNOT STNOT [2] STNOT [7] STNOT [18] Proposed STNAND STNAND [2] STNAND [7] STNAND [18] Proposed STNOR STNOR [2] STNOR [7] STNOR [18]
26.1 23.3 15.1 16.2 12.2 23.3 9.20 29.3 41.8 18.2 28.5 23.1
0.06 0.19 0.29 1.51 0.04 0.19 0.23 1.71 0.04 0.22 0.35 3.51
1.71 4.49 4.39 24.7 0.56 4.49 2.20 51.8 2.01 4.01 10.1 82.1
Dn=0.626nm
A
QNOR D=2.27nm
A
D=0.626 nm
Dp=2.27nm
B
B
D=2.27nm
Dn=0.626nm
B
D=2.27 nm
1/3 VDD
A
Table 3 Simulation results of the two cascaded quaternary circuits (@ 32 nm and 0.9 V). Cascaded quaternary designs
Delay (e-10 s)
Power (e-6 W)
PDP (e-16 J)
Proposed QNOT QBuffer [17] QNOT [18] Proposed QNAND QAND [17] QNANAD [18] Proposed QNOR QOR [17] QNOR [18]
1.43 5.14 0.28 2.73 5.41 0.36 2.74 5.23 0.36
1.24 3.36 62.1 4.95 3.02 54.8 6.79 3.88 54.8
1.78 17.2 17.8 13.5 16.4 19.7 18.6 20.3 19.7
Fig. 8. The proposed quaternary NOR.
Fig. 9. Transient respond of the proposed QNOT, QNOR and QNAND.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
6
addition, the proposed designs work correctly with small parametric variations in the presence of process variations. It is worth pointing out that utilizing multiple supply voltages leads to some system-level costs related to power grids and
voltage generators. Moreover, the additional power supplies will not have ideal voltages and deviate from the ideal voltage levels provisional or permanently, which can affect the performance and robustness of the circuits. In order to examine the effect of supply
Table 4 Simulation results of the two cascaded ternary circuits (@ 22 nm and 0.8 V). Cascaded ternary designs
Delay (e-12 s)
Power (e-6 W)
PDP (e-18 J)
Proposed STNOT STNOT [2] STNOT [7] STNOT [18] Proposed STNAND STNAND [2] STNAND [7] STNAND [18] Proposed STNOR STNOR [2] STNOR [7] STNOR [18]
38.82 21.54 19.97 31.31 10.51 42.63 9.8734 53.429 69.38 25.31 14.46 38.04
0.022 0.038 0.066 0.557 0.016 0.051 0.056 0.538 0.016 0.065 0.082 1.080
0.875 0.822 1.335 17.44 0.178 2.211 0.559 0.287 1.128 1.670 1.186 41.08
Table 5 Simulation results of the two cascaded quaternary circuits (@ 22 nm and 0.8 V). Cascaded quaternary designs
Delay (e-10 s)
Power (e-6 W)
PDP (e-16 J)
Proposed QNOT QBuffer [17] QNOT [18] Proposed QNAND QAND [17] QNAND [18] Proposed QNOR QOR [17] QNOR [18]
3.410 0.380 12.84 9.480 0.490 13.24 5.474 12.98 0.491
0.752 50.36 1.052 1.806 44.37 0.957 2.760 1.182 44.45
2.566 19.14 13.51 17.12 21.74 12.68 15.11 15.35 21.86
1.6
2.5
1 0.8 0.6
Proposed STNAND STNAND[2] STNAND[19]
2.5 PDP (e-18J)
PDP (e-18J)
1.2
STNOT[2] STNOT[19] PDP (e-18J)
1.4
3
3
proposed STNOT
2 1.5 1
Proposed STNOR STNOR[2] STNOR[19]
2 1.5 1
0.4
0.8
0
0.9 1 Supply Voltage (V)
16
PDP (e-16 J)
12
0
0.9 1 Supply Voltage (V)
14 12
10 8 6
Proposed QNAND QAND[17] QNAND[18]
14 12
10 8 6
6 4
2
2
2
0
0
0.8
0.9 1 Supply Voltage (V)
Proposed QNOR QOR[17] QNOR[18]
8
4
0.9 1 Supply Voltage (V)
0.9 1 Supply Voltage (V)
10
4
0.8
0.8
16
16 Proposed QNOT QBuffer[17] QNOT[18] PDP (e-16 J)
14
0.8
PDP (e-16 J)
0
0.5
0.5
0.2
0
0.8
0.9 1 Supply Voltage (V)
Fig. 10. PDP of the ternary and quaternary gates vs. supply voltage variation.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
7
1.2 1.6
STNOT[19]
1.4
0.8 0.6 0.4
1 0.8 0.6
Proposed QNOT QBuffer[17] QNOT[18]
0 10 20 30 40 50 60 70 80 Temprature (oC)
20 18 16 14 12 10 8 6 4 2 0
0.8 0.6
0.2 0
0 10 20 30 40 50 60 70 80 Temprature (oC)
Proposed QNAND QAND[17] QNAND[18] PDP (e-16J)
0
0 10 20 30 40 50 60 70 80 Temprature (oC)
1
0.4
0.2
PDP (e-16J)
PDP (e-16J)
20 18 16 14 12 10 8 6 4 2 0
1.2
0.4
0.2 0
1.2
Proposed STNOR STNOR[19] STNOR[2]
1.4
Proposed STNAND STNAND[19] STNAND[2] PDP (e-18J)
STNOT[2]
PDP (e-18J)
PDP (e-18J)
1
Proposed STNOT
0 10 20 30 40 50 60 70 80 Temprature (oC)
16 15 14 13 12 11 10 9 8 7 6
0 10 20 30 40 50 60 70 80 Temprature (oC)
Proposed QNOR QOR[17] QNOR[18]
0 10 20 30 40 50 60 70 80 Temprature (oC)
Fig. 11. PDP of the ternary and quaternary gates vs. temperature variation.
0.08 0.06 0.04 0.02 5
Proposed QNOT QBuffer[17] QNOT[18]
7 6 5 4 3 2 1 0
5
10 15 Density Variation (%)
0.4 0.3 0.2 0.1 0
10 15 Density variation (%)
8
0.5
5
4
3 2.5 2 1.5 1 0.5 0
5
10 15 Density Variation (%)
0.9 Proposed STNOR STNOR[2] STNOR[19]
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
10 15 Density variation (%) Proposed QNAND QAND[17] QNAND[18]
3.5
Maximum PDP variation (e-18J)
0.1
Proposed STNAND STNAND[2] STNAND[19]
0.6
Maximum PDP Variation (e -17J)
0.12
Maximum PDP variation (e-18j)
0.14
0
Maximum PDP Variation (e -17J)
0.7 Proposed STNOT STNOT[2] STNOT[19]
0.16
Maximum PDP Variation (e -17J)
Maximum PDP variation (-18J)
0.18
5
10 15 Density variation (%) Proposed QNOR QOR[17] QNOR[18]
10 8 6 4 2 0
5
10 15 Density Variation (%)
Fig. 12. Parameter variations of the designs with respect to CNT density variations.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
1.8
1 0.8 0.6 0.4 0.2
3.5 3 2.5 2 1.5 1 0.5 0
10 15 Diameter Variation (%)
5
16 Proposed QNOT QBuffer[17] QNOT[18]
5
6 5 4 3 2 1 5
10 15 Diameter Variation (%)
8 Proposed QNAND QAND[17] QNAND[18]
14 12 10 8 6 4 2 0
10 15 Diameter Variation (%)
Proposed STNOR STNOR[2] STNOR[19]
7
0
10 15 Diameter Variation (%) Maximum PDP Variation (e -17J)
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0
5
Proposed STNAND STNAND[2] STNAND[19]
Maximum PDP Variation (e-18J)
1.2
0
Maximum PDP Variation (e -17J)
Maximum PDP Variation (e-18J)
1.4
8
4
Proposed STNOT STNOT[2] STNOT[19]
1.6
Maximum PDP Variation (e -17J)
Maximum PDP Variation (e-18J)
8
Proposed QNOR QOR[17] QNOR[18]
7 6 5 4 3 2 1 0
5 10 15 Diameter Variation (%)
5
10 15 Diameter Variation (%)
Fig. 13. Parameter variations of the designs with respect to CNT diameter variations.
Maximum PDP (e-18 J)
90 80 70
7 Proposed Design
Proposed Design Design [2] Design [19] Design [18]
6 Maximum PDP (e-15)
100
60 50 40 30
Design [17] Design [18]
5 4 3 2
20 1
10 0
0 STNOT
STNAND
STNOR
Standard Ternary Logic Circuits
QNOT/Buff
QNAND/AND
QNOR/OR
Quaternary Logic Circuits
Fig. 14. PDP variations of the designs with respect to supply voltages variations.
voltage variations on the energy efficiency of the circuits, the cascaded form of the MVL circuits is simulated in the presence of random supply voltage variations. For this purpose, the Monte Carlo simulation has been conducted using Gaussian distributions with 710% variation at the 7 3σ level. The results, shown in Fig. 14, indicate the lower energy consumption of the proposed circuits, except QNAND, even in the presence of random supply voltage variations. In addition, the results of the Monte Carlo DC analyses of the STNOT and QNOT circuits with Gaussian distribution considering 710% variations in process and supply voltages variations at the 73σ level are shown in Fig. 15. As demonstrated in Fig. 15, the voltage transfer characteristic (VTC) curves of the proposed STNOT and QNOT circuits have very steep transition regions and are quite less sensitive to the simultaneous variations of process and supply
voltage as compared to the state-of-the-art pseudo-n-type designs [18]. Noise immunity curve (NIC) is used for evaluating and comparing the noise tolerance of the proposed designs to the input noise pulses. NIC is the locus of noise pulse amplitude (Vnoise) and noise puleswidth (Tnoise). A noise pulse with sufficient width and amplitude may cause the circuit to have a logic error. The area below NIC indicates the safe region and above it indicates the unsafe region. It means that if the noise amplitude is higher at a point on NIC for a particular width then the circuit will output an error. Therefore, higher the NIC of a digital circuit, the more immune the circuit to noise. Noise immunity curves were obtained by simulation using a tunable noise injection circuit described in detail in previous works [27].
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
9
Fig. 15. The results of the Monte Carlo DC analyses considering both process and voltage variations. (a) The proposed QNOT. (b) Pseudo-n-type QNOT [18]. (c) Proposed QNOT. (d) Pseudo-n-type QNOT [18].
Table 6 Noise margins of the ternary STNOTs (VDD ¼ 0.9 V).
Table 7 Noise Margins of the Quaternary NOTs (VDD ¼0.9 V).
Design
NML 021 (mV)
NMH 021 (mV)
NML 122 (mV)
NMH 122 (mV)
Noise margin (mV)
Design
NML NMH NML NMH NML NMH 021 021 122 122 223 223 (mV) (mV) (mV) (mV) (mV) (mV)
Noise margin (mV)
Proposed STNOT STNOT [2] STNOT [18] STNOT [7]
160 150 120 120
280 300 310 180
270 290 220 210
160 150 160 160
160 150 120 120
Proposed QNOT QNOT [17] QNOT [18]
210
80
110
100
210
80
80
180 80
74 45
228 130
85 40
210 180
44 20
44 20
Moreover, noise margins of the ternary and quaternary circuits for all logic level transitions have been measured and are shown in Tables 6 and 7, respectively. According to the results, the proposed designs have larger noise margin as compared with the other state-of-the art CNTFET-based MVL designs. Fig. 16 shows the NIC curves of the ternary and quaternary inverters. The proposed QNOT shows good noise immunity as compared to the other quaternary inverters, also the proposed
STNOT has better noise immunity compared to pseudo-n-type STNOT [18] and complementary CNTFET STNOT [7].
5. Conclusion In this study new energy-efficient and PVT tolerant multiple valued logic (MVL) gates are proposed for nanoelectronics. The
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
10
300 Proposed STNOT STONOT[2] STNOT[18] STNOT[19]
325
Noise Amplitude (mV)
Noise Amplitude (mV)
350
300
275
250
50
100 150 200 Noise width (ps)
250
300
Proposed QNOT QNOT[17] QNOT[18] 250
200
150
50
100
150 200 250 Noise width (ps)
300
Fig. 16. Noise immunity curves for the ternary and quaternary inverters.
proposed CNTFET-based circuits have been designed based on multiple-Vth CNTFETs, using only two distinct CNT diameters for ternary and quaternary designs, which enhances the feasibility and manufacturability of the designs, while the previous quaternary gates require at least three different CNT diameters. The simulation results confirm the superiority of the proposed method compared to the other designs in various simulation conditions as well as in the presence of process, voltage and temperature variations. Based on the simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45% lower PDP as compared to the other designs, respectively. Also the proposed QNOT, QNAND and QNOR circuits have the average PDP enhancement of about 79%, 42% and 61% as compared to the other state-of-the-art designs, respectively.
References [1] S.L. Hurst, Multiple-valued logic—its status and its future, IEEE Trans. Comput. 100 (1984) 1160–1179. [2] M.H. Moaiyeri, A. Doostaregan, K. Navi, Design of energy-efficient and robust ternary circuits for nanotechnology, IET Circuits Devices Syst. 5 (2011) 285–296. [3] E. Dubrova, Multiple-valued logic in VLSI: challenges and opportunities, In: Proceedings of NORCHIP, 1999, pp. 340–350. [4] K. Navi, A. Doostaregan, M.H. Moaiyeri, O. Hashemipour, A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders, Fuzzy Sets Syst. 185 (2011) 111–124. [5] E. Alkaldy, K. Navi, F. Sharifi, M.H. Moaiyeri, An ultra-high-speed (4; 2) compressor with a new design approach for nanotechnology based on the multiinput majority function, J. Comput. Theor. Nanosci. 11 (2014) 1691–1696. [6] K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits, Proc. IEEE 91 (2003) 305–327. [7] S. Lin, Y.-B. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits, IEEE Trans. Nanotechnol. 10 (2011) 217–225. [8] A. Roychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiplevalued logic design, IEEE Trans. Nanotechnol. 4 (2) (2005) 168–179. [9] H. Mouftah, I. Jordan, Integrated circuits for ternary logic, in: Proceedings of the 1974 International Symposium on Multiple-Valued Logic, 1974, pp. 285–302. [10] H. Mouftah, K. Smith, Injected voltage low-power C MOS for 3-valued logic, IEE Proceedings G (Electronic Circuits and Systems), 1982, 270–272. [11] R.C.G. da Silva, H. Boudinov, L. Carro, A novel voltage-mode CMOS quaternary logic design, IEEE Trans. Electron Devices 53 (2006) 1480–1483.
[12] S. Raju Datla, M.A.Thornton, Quaternary voltage-mode logic cells and fixedpoint multiplication circuits in multiple-valued logic (ISMVL), In: Proceedings of the 40th IEEE International Symposium, 2010, pp. 128–133. [13] A. Heung, H. Mouftah, Depletion/enhancement CMOS for a lower power family of three-valued logic circuits, IEEE J. Solid-State Circuits 20 (1985) 609–616. [14] I. Thoidis, D. Soudris, I. Karafyllidis, S. Christoforidis, A. Thanailakis, Quaternary voltage-mode CMOS circuits for multiple-valued logic, IEE Proceedings Circuits Devices and Systems, 1998, pp. 71–77. [15] P. Vasundara, K. Gurumurthy, Quaternary CMOS combinational logic circuits, In: Proceeding of International Conference on Information and Multimedia Technology ICIMT'09, 2009, pp. 538–542. [16] Y. Yasuda, Y. Tokuda, S. Zaima, K. Pak, T. Nakamura, A. Yoshida, Realization of quaternary logic circuits by n-channel MOS devices, IEEE J. Solid-State Circuits 21 (1986) 162–168. [17] M.H. Moaiyeri, K. Navi, O. Hashemipour, Design and evaluation of CNFETbased quaternary circuits, Circuits Syst. Signal Process. 31 (2012) 1631–1652. [18] J. Liang, L. Chen, J. Han, F. Lombardi, Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs, IEEE Trans. Nanotechnol. 13 (2014) 695–708. [19] P.L. McEuen, M.S. Fuhrer, H. Park, Single-walled carbon nanotube electronics, IEEE Trans. Nanotechnol. 1 (2002) 78–85. [20] Y.B. Kim, Y.-B. Kim, F. Lombardi, A novel design methodology to optimize the speed and power of the CNTFET circuits, in: Proceedings of the 52nd IEEE International Midwest Symposium on Circuits and Systems MWSCAS'09, 2009, pp. 1130–1133. [21] A. Raychowdhury, K. Roy, Carbon nanotube electronics: design of highperformance and low-power digital circuits, IEEE Trans. Circuits Syst. I: Regul. Pap. 54 (2007) 2391–2401. [22] J. Deng, H.-S. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the intrinsic channel region, IEEE Trans. Electron Devices 54 (2007) 3186–3194. [23] J. Deng, H.-S. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking, IEEE Trans. Electron Devices 54 (2007) 3195–3205. [24] J. Deng, Device Modeling and Circuit Performance Evaluation for Nanoscale Devices: Silicon Technology Beyond 45 nm Node and Carbon Nanotube Field Effect Transistors (Doctoral dissertation), Stanford University, 2007. [25] J. Zhang, N. Patil, H.-S. Wong, S. Mitra, Overcoming carbon nanotube variations through co-optimized technology and circuit design, In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2011, pp. 4.6.1–4.6.4. [26] S. Lin, Y.-B. Kim, F. Lombardi, Design of a ternary memory cell using CNTFETs, IEEE Trans. Nanotechnol. 11 (2012) 1019–1025. [27] S. Goel, A. Kumar, M.A. Bayoumi, Design of robust, energy-efficient full adders for deep submicrometer design using hybrid-CMOS logic style, IEEE Trans. Very Larg. Scale Integr. Syst. 14 (12) (2006) 1309–1321.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach Fazel Sharifi a, Mohammad Hossein Moaiyeri a, Keivan Navi a,n, Nader Bagherzadeh b a b
Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran Department of Electrical Engineering and Computer Science, University of California, Irvine, United States
art ic l e i nf o
a b s t r a c t
Article history: Received 24 November 2014 Received in revised form 31 July 2015 Accepted 29 September 2015
In this paper energy-efficient multiple valued logic (MVL) circuits based on carbon nanotube field effect transistor (CNTFET) are proposed. These circuits are designed based on the unique properties of CNTFETs, such as having same mobility for electrons and holes and also capability of adopting desirable threshold voltage by adjusting the CNTs diameters. The proposed designs have high driving capability, larger noise margins and higher robustness as compared to the previous CNTFET-based designs. The proposed quaternary circuits are examined using HSPICE simulator with the standard CNTFET technology. Simulation results demonstrate more energy-efficient and robust operation of the proposed designs, as compared to the other state-of-the-art CNTFET-based MVL circuits, recently presented in the literature. According to the simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45% lower power-delay product (PDP), respectively as compared to their state-of-the-art counterparts. In addition, the proposed QNOT, QNAND and QNOR circuits have the average PDP improvements of 79%, 42% and 61%, respectively, as compared the other recently presented CNTFET-based quaternary designs. & 2015 Elsevier Ltd. All rights reserved.
Keywords: Nanoelectronics Multiple valued logic (MVL) CNTFET Low-power design
1. Introduction Digital computation is generally performed on two-valued (binary) logic. Powerful computational elements and tools have already supported binary logic to reach its present status. Multiple-valued logic (MVL) is an alternative logic which uses more than two logical values. MVL circuits have attracted the attention of researchers, due to some of their important features related to reduction of the number of interconnections and increased information content per unit area. In other word, MVL allows more information to be transmitted over a given set of lines or to be stored on a given register length, thus reducing the complexity of interconnects and chip area and achieving simplicity and energy efficiency in digital design [1–4]. Among MVL systems, using e base (eE 2.718) leads to the most efficient implementation of the switching systems [1]. However, due to the restrictions on hardware implementation, designers are limited to use natural numbers as the radices for computations. On the other hand, power-of-two radices take advantage of simple conversion between MVL signals and binary signals, generated by the existing binary circuits. Therefore researchers focus on radices 3 and 4 for hardware implementation. n
Corresponding author. E-mail address: [email protected] (K. Navi).
Carbon nanotube field effect transistor (CNTFET) is a promising alternative to silicon transistor for achieving low power and high performance. CNTFET avoids most problems of nanoscale MOSFET technology, such as very high leakage power dissipation, reduced gate control and velocity saturation [5,6]. The other advantage of CNTFET is that the threshold voltage of a CNTFET is determined dominantly based on the diameter of its CNT channels. Hence, multiple-threshold circuits can be achieved by utilizing CNTFETs with different diameters. This property is very useful in designing voltage-mode MVL circuits [7,8]. Some MOSFET and CNTFET-based MVL circuits, specifically for ternary and quaternary logics, have been presented so far in the literature [9–19]. However, they have some critical drawbacks such as using very large ohmic resistors [9,10], requiring obsolete depletion-mode MOSFET [11–16], high static power consumption [17–19] non-full swing nodes [9,10] and limited fan-out [19]. In this study, energy-efficient quaternary gates tolerant to process, voltage and temperature variations are proposed for nanoelectronics, which are designed based on the complementary CNTFET style. The rest of the paper is organized as follows: Section 2 briefly reviews the CNTFET device. The proposed designs are described in Section 3. In Section 4, the simulation results, analyses and comparisons are presented and finally Section 5 concludes this paper.
http://dx.doi.org/10.1016/j.mejo.2015.09.018 0026-2692/& 2015 Elsevier Ltd. All rights reserved.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
2
Table 1 The truth table of standard ternary NOT, NAND and NOR. a
b
STNOT (a)
STNAND (a,b)
STNOR (a,b)
0 0 0 1 1 1 2 2 2
0 1 2 0 1 2 0 1 2
2 2 2 1 1 1 0 0 0
2 2 2 2 1 1 2 1 0
2 1 0 1 1 0 0 0 0
and p þ for pCNTFET. MOSFET-like CNTFET has very high ION/IOFF ratio which makes it suitable for high-performance and energyefficient applications [21]. In this paper MOSFET-like CNTFETs are used for designing and simulating the circuits.
Fig. 1. Schematic of CNTFET.
2. Carbon nanotube field effect transistor (CNTFET) Carbon nanotube (CNT) is a sheet of graphene rolled up along a wrapping vector, which can be single-wall (SWCNT) or multi-wall (MWCNT). Single-wall CNT is a single nanotube and multi-wall CNT is made of two or more coaxial nanotubes. Rolling up the graphene sheet into a tube is assumed based on a vector called the chiral vector (n1, n2). Based on (n1, n2), if n1 n2 ¼3k (kA Z), then SWCNT becomes conductor and otherwise it becomes semiconductor. Conductive CNTs are used as on-chip interconnects and semiconducting CNTs are used as the channel of transistors [7]. The schematic of a typical CNTFET device is illustrated in Fig. 1. The gate width of a CNTFET (Wgate) is approximately calculated based on the following equation: W gate MaxðW min ; N PitchÞ
ð1Þ
where Pitch is the distance between the centers of two neighboring SWCNTs under the same gate, Wmin is the minimum gate width, determined by lithography and N is the number of nanotubes under the gate. The threshold voltage of a CNTFET is an inverse function of the diameter of its CNTs. This capability is utilized to adopt the desired threshold voltage (Vth) by choosing the correct DCNT. The CNTFET threshold voltage is calculated based on Eq. (3). pffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3a0 n1 2 þn1 n2 þ n2 2 DCNT ¼ 0:0783 n1 2 þ n1 n2 þ n2 2 ð2Þ
π
V th
Ebg a0 V π 0:43 ¼ 2e eDCNT DCNT ðnmÞ
ð3Þ
where e is the unit electron charge, Ebg is the CNT bandgap, a0 ( 0.142 nm) is the carbon to carbon bond length in a CNT and Vπ ( 3.033 eV) is the carbon π–π bond energy in the tight bonding model [20]. Based on the type of connections between source/drain regions and CNT channels and the type of source/drain regions there are three main categories of CNTFETs. The first type is Schottky Barrier CNTFET (SB-CNTFET) which has metallic source/drain regions. In this type of CNTFET, the Schottky barrier junctions limit the transconductance in the ON state and increase the reverse currents in the OFF state; thus ION/IOFF ratio becomes rather low. SBCNTFET is appropriate for medium to high-performance applications. The second type of CNTFET is the band-to-band tunneling CNTFET (T-CNTFET) with CNT source and drain regions with opposite doping types. T-CNTFET has super cut-off characteristics and also has low ON current. T-CNTFET is suitable for low stand-by power application but it is not appropriate for high-performance applications. The third type of CNTFETs is the MOSFET-like CNTFET, in which source and drain CNT regions are doped n þ for nCNTFET
3. Proposed designs 3.1. Ternary circuits In this section new ternary circuits based on CNTFETs are presented. The truth table of ternary functions is shown in Table 1. Ternary logic includes three significant logic levels which can be considered as “0”, “1” and “2” symbols; these symbols are counterpart to 0, ½VDD and VDD voltage levels respectively. The proposed ternary inverter circuit is shown in Fig. 2. Based on Eqs. (1) and (2), for the CNTFETs of this design with the diameters of 0.626, 0.783 and 1.487 nm, the chiral numbers would be (8,0), (10,0) and (19,0) and the threshold voltage values (|Vth|) would be 0.686 V, 0.559 V and 0.293 V, respectively. First consider the input voltage is near 0. For this value the output of inverter1 and inverter2 is VDD, so T3 is OFF and T1 is ON and consequently the output voltage will be VDD. When the input voltage is ½VDD, the output of first and second inverters is 0 and VDD respectively; therefore T3 and T4 are ON and the output voltage is ½VDD. Finally when the input voltage is VDD, output of both inverters is 0 and T4 is OFF, so T2 is ON and output voltage is 0. Based on the STNOT design methodology, STNAND and STNOR circuits are proposed which are shown in Figs. 3 and 4 respectively. Transient simulation results of the proposed STNOT, STNAND and STNOR are plotted in Fig. 5. These results, which are obtained by HSPICE simulations, show the correct operation of the proposed ternary circuits. 3.2. Quaternary circuits In this section, new quaternary logic gates including a quaternary inverter (QNOT), a quaternary NAND (QNAND) and a quaternary NOR (QNOR) are proposed. Quaternary logic consists of four significant logic levels which can be represented by “0”, “1”, “2” and “3” symbols. These logic levels are commonly counterpart to 0 V, ⅓VDD, ⅔VDD and VDD voltage levels, respectively. The functionalities of the quaternary gates can be described by Eqs. (4)–(6). QNOTðaÞ ¼ 3 a
ð4Þ
QNANDða; bÞ ¼ Minða; bÞ ¼ QNORða; bÞ ¼ Maxða; bÞ ¼
3a
if
3b
otherwise
3a 3b
arb
if a Zb otherwise
ð5Þ
ð6Þ
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
3
VDD
VDD T1 D=0.626nm IN D=0.626nm
STNOT
Dn=1.487nm
T3
1
T2
Dp=0.783nm
B
D=0.626 nm
A
D=0.626 nm Dn=0.783nm
IN
A
STNOR
T4
2 Dn=0.783nm
A
D=0.626 nm
Dp=1.487nm
B
B
1/2 VDD Dn=0.783nm
Fig. 2. The proposed ternary inverter.
Dp=0.783nm
Dp=0.783nm
A
B
VDD
Dn=1.487nm
A
1/2 VDD
B
D=0.626 nm
Dn=1.487nm
Fig. 4. The proposed ternary NOR.
Dn=1.487nm
A
D=0.626 STNAND nm
A Dp=0.783nm
B
D=0.626 nm
B Dn=1.487nm
Dp=1.487nm
Dp=1.487nm
B
A Dn=0.783nm
Dn=0.783nm 1/2 VDD Fig. 3. The proposed ternary NAND.
The proposed quaternary inverter, which can be considered as the cornerstone of the other proposed quaternary gates, is shown in Fig. 6. The operation of the proposed quaternary inverter gate can be briefly described as follows: when the input voltage is around 0 V, T1 is ON and T2–T5 are OFF. So the output voltage will be VDD. When the input voltage is around ⅓VDD, T1, T2 and T5 are OFF and T3 and T4 are ON and consequently the output voltage will be ⅔VDD. When the input voltage is around ⅔VDD, T1, T2 and T3 are OFF and T5 and T6 are ON. Consequently the output voltage will become ⅓VDD. Finally, if the input value becomes VDD, T1, T3 and T6 become OFF and T2 becomes ON and consequently the output is discharged to 0. Based on the proposed method for designing the QNOT circuit, a new quaternary NAND and a new quaternary NOR are also introduced. The operation principles of these two circuits are similar to the proposed quaternary inverter. The schematic of the proposed QNAND and QNOR circuits is shown in Figs. 7 and 8, respectively.
Operation of the proposed quaternary NAND can be summarized as follows: While both inputs are around VDD, T3 and T4 are ON, so the output will be 0. While one of the inputs is around ⅔VDD and the other one is equal or greater than ⅔VDD, T9, T10 and at least one of the T11 and T12 are ON based on the threshold voltage of the inverters connected to the transistors gate, therefore the output is ⅓VDD. If one of the inputs is around ⅓VDD and the other one is equal or greater than ⅓VDD, T7, T8 and at least one of the T5 and T6 are ON, so the output will be ⅔VDD. Moreover while one or both of the inputs is around 0, T1 or T2 are ON and other paths to the output are disconnected (T7 or T8, T9 or T10 are OFF), consequently output is VDD. The operation of the proposed QNOR is similar to QNAND circuit. It is worth mentioning that only two distinct diameters are utilized for the CNTFETs of the proposed quaternary designs, whereas the previous CNTFET-based quaternary gates have used at least three distinct diameters. This alleviates sensitivity to process variations and enhances manufacturability. In addition, the proposed quaternary 2-input NAND and NOR gates can also be extended to quaternary NAND and NOR circuits with more than two inputs by extending the proposed complementary CNTFET-based structures of Figs. 7 and 8. The transient responses of the proposed QNOT, QNAND and QNOR are shown in Fig. 9, which authenticate the correct operation of the proposed circuits.
4. Simulation results and comparisons In this section, the proposed designs are comprehensively examined and compared with the other state-of-the-art CNTFETbased designs. The circuits are simulated using Synopsys HSPICE with the commonly used compact SPICE model for unipolar MOSFET-like CNTFETs including all the non-idealities and parasitics [22–24] at 32 nm technology. Simulations are conducted at different power supplies and also at different temperatures to consider the voltage and temperature variations.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
4
Fig. 5. Transient response of the proposed STNOT, STNOR and STNAND.
2/3 VDD
2/ 3 VDD
T3 VDD
T4
T1 D=0.626nm IN
T5
D=2.27nm
B
D=0.626nm
Dn=2.27nm D=0.626nm QNOT D=2.27nm
A
D=2.27 nm
VDD
D=2.27nm
T2
T6
T5
T1
IN
Dp=2.27nm
D=2.27nm
T2
A
B T8
B
D=0.626 nm
A
T3 D=0.626nm
A
1/3 VDD Fig. 6. The proposed quaternary inverter.
The results of the simulations at 32 nm technology node and 0.9 V supply voltage including the worst-case delay, the average power consumption and the power-delay product (PDP) of the cascaded ternary and quaternary designs are presented in Tables 2 and 3, respectively. According to the simulation results, the proposed designs consume lower power and have lower PDP compared to the state-of-the-art CNTFET-based designs. The CNTFET-based circuits also have been simulated at 22 nm technology node and 0.8 V supply voltage. The results of this simulation are given in Tables 4 and 5 for the ternary and quaternary designs, respectively. According to the simulation results, the proposed designs consume lower power and are more energyefficient as compared to the state-of-the-art CNTFET-based designs even at 22 nm technology.
Dn=2.27nm
T9 D=0.626nm
A
D=2.27nm QNAND
T10
T4 B
Dp=0.626nm
D=2.27nm
T6 D=2.27nm
Dn=2.27nm
T7
D=0.626nm
Dp=2.27nm T11
B
B
D=2.27nm
T12
Dp=2.27nm
D=2.27 nm
A Dn=0.626nm
Dn=0.626nm 1/ 3 VDD Fig. 7. The proposed quaternary NAND.
Figs. 10 and 11 compare the performance of the designs at 32 nm technology and 0.9 V voltage considering different supply voltages and temperatures respectively. According to the results, the proposed quaternary designs have lower PDP at all supply voltages and temperatures compared to the other designs. The
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
proposed STNOT has higher PDP than other designs at supply voltage of 0.8 V. Since the results of ternary designs with pseudon-type CNTFETs [18] are very higher than the other designs we eliminate them in upcoming figures. The operation and performance of the ternary and quaternary gates are also examined in the presence of process variations. Nanotube density variations, mainly resulted from variations in the spacing between CNTs on the substrate (Pitch) and variations in the surviving CNT count after metallic CNT removal techniques, are proven experimentally to be the dominant source of variation 2/3 VDD
D=2.27 nm
B
A
Dn=2.27nm
B
D=0.626nm
A
D=0.626nm
in CNTFET circuits [25]. In addition, diameter variation is a significant issue in multi-diameter CNTFET circuits [17,26]. As a result, the Monte Carlo simulation has been conducted to evaluate these process variations with up to 715% Gaussian distributions and variation at the 73σ level. Figs. 12 and 13 demonstrate the maximum PDP variation of the designs in the presence of CNT density and diameter variations, respectively. According to the results, the pseudo-n-type QNOT [18] does not work when the diameter deviation reaches 15%. In
Table 2 Simulation results of the two cascaded ternary circuits (@ 32 nm and 0.9 V).
Dp=0.626nm
Dp=0.783nm VDD
5
Dn=2.27nm D=2.27nm
B
D=2.27nm
A
Cascaded ternary designs
Delay (e-12 s)
Power (e-6 W)
PDP (e-18 J)
Proposed STNOT STNOT [2] STNOT [7] STNOT [18] Proposed STNAND STNAND [2] STNAND [7] STNAND [18] Proposed STNOR STNOR [2] STNOR [7] STNOR [18]
26.1 23.3 15.1 16.2 12.2 23.3 9.20 29.3 41.8 18.2 28.5 23.1
0.06 0.19 0.29 1.51 0.04 0.19 0.23 1.71 0.04 0.22 0.35 3.51
1.71 4.49 4.39 24.7 0.56 4.49 2.20 51.8 2.01 4.01 10.1 82.1
Dn=0.626nm
A
QNOR D=2.27nm
A
D=0.626 nm
Dp=2.27nm
B
B
D=2.27nm
Dn=0.626nm
B
D=2.27 nm
1/3 VDD
A
Table 3 Simulation results of the two cascaded quaternary circuits (@ 32 nm and 0.9 V). Cascaded quaternary designs
Delay (e-10 s)
Power (e-6 W)
PDP (e-16 J)
Proposed QNOT QBuffer [17] QNOT [18] Proposed QNAND QAND [17] QNANAD [18] Proposed QNOR QOR [17] QNOR [18]
1.43 5.14 0.28 2.73 5.41 0.36 2.74 5.23 0.36
1.24 3.36 62.1 4.95 3.02 54.8 6.79 3.88 54.8
1.78 17.2 17.8 13.5 16.4 19.7 18.6 20.3 19.7
Fig. 8. The proposed quaternary NOR.
Fig. 9. Transient respond of the proposed QNOT, QNOR and QNAND.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
6
addition, the proposed designs work correctly with small parametric variations in the presence of process variations. It is worth pointing out that utilizing multiple supply voltages leads to some system-level costs related to power grids and
voltage generators. Moreover, the additional power supplies will not have ideal voltages and deviate from the ideal voltage levels provisional or permanently, which can affect the performance and robustness of the circuits. In order to examine the effect of supply
Table 4 Simulation results of the two cascaded ternary circuits (@ 22 nm and 0.8 V). Cascaded ternary designs
Delay (e-12 s)
Power (e-6 W)
PDP (e-18 J)
Proposed STNOT STNOT [2] STNOT [7] STNOT [18] Proposed STNAND STNAND [2] STNAND [7] STNAND [18] Proposed STNOR STNOR [2] STNOR [7] STNOR [18]
38.82 21.54 19.97 31.31 10.51 42.63 9.8734 53.429 69.38 25.31 14.46 38.04
0.022 0.038 0.066 0.557 0.016 0.051 0.056 0.538 0.016 0.065 0.082 1.080
0.875 0.822 1.335 17.44 0.178 2.211 0.559 0.287 1.128 1.670 1.186 41.08
Table 5 Simulation results of the two cascaded quaternary circuits (@ 22 nm and 0.8 V). Cascaded quaternary designs
Delay (e-10 s)
Power (e-6 W)
PDP (e-16 J)
Proposed QNOT QBuffer [17] QNOT [18] Proposed QNAND QAND [17] QNAND [18] Proposed QNOR QOR [17] QNOR [18]
3.410 0.380 12.84 9.480 0.490 13.24 5.474 12.98 0.491
0.752 50.36 1.052 1.806 44.37 0.957 2.760 1.182 44.45
2.566 19.14 13.51 17.12 21.74 12.68 15.11 15.35 21.86
1.6
2.5
1 0.8 0.6
Proposed STNAND STNAND[2] STNAND[19]
2.5 PDP (e-18J)
PDP (e-18J)
1.2
STNOT[2] STNOT[19] PDP (e-18J)
1.4
3
3
proposed STNOT
2 1.5 1
Proposed STNOR STNOR[2] STNOR[19]
2 1.5 1
0.4
0.8
0
0.9 1 Supply Voltage (V)
16
PDP (e-16 J)
12
0
0.9 1 Supply Voltage (V)
14 12
10 8 6
Proposed QNAND QAND[17] QNAND[18]
14 12
10 8 6
6 4
2
2
2
0
0
0.8
0.9 1 Supply Voltage (V)
Proposed QNOR QOR[17] QNOR[18]
8
4
0.9 1 Supply Voltage (V)
0.9 1 Supply Voltage (V)
10
4
0.8
0.8
16
16 Proposed QNOT QBuffer[17] QNOT[18] PDP (e-16 J)
14
0.8
PDP (e-16 J)
0
0.5
0.5
0.2
0
0.8
0.9 1 Supply Voltage (V)
Fig. 10. PDP of the ternary and quaternary gates vs. supply voltage variation.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
7
1.2 1.6
STNOT[19]
1.4
0.8 0.6 0.4
1 0.8 0.6
Proposed QNOT QBuffer[17] QNOT[18]
0 10 20 30 40 50 60 70 80 Temprature (oC)
20 18 16 14 12 10 8 6 4 2 0
0.8 0.6
0.2 0
0 10 20 30 40 50 60 70 80 Temprature (oC)
Proposed QNAND QAND[17] QNAND[18] PDP (e-16J)
0
0 10 20 30 40 50 60 70 80 Temprature (oC)
1
0.4
0.2
PDP (e-16J)
PDP (e-16J)
20 18 16 14 12 10 8 6 4 2 0
1.2
0.4
0.2 0
1.2
Proposed STNOR STNOR[19] STNOR[2]
1.4
Proposed STNAND STNAND[19] STNAND[2] PDP (e-18J)
STNOT[2]
PDP (e-18J)
PDP (e-18J)
1
Proposed STNOT
0 10 20 30 40 50 60 70 80 Temprature (oC)
16 15 14 13 12 11 10 9 8 7 6
0 10 20 30 40 50 60 70 80 Temprature (oC)
Proposed QNOR QOR[17] QNOR[18]
0 10 20 30 40 50 60 70 80 Temprature (oC)
Fig. 11. PDP of the ternary and quaternary gates vs. temperature variation.
0.08 0.06 0.04 0.02 5
Proposed QNOT QBuffer[17] QNOT[18]
7 6 5 4 3 2 1 0
5
10 15 Density Variation (%)
0.4 0.3 0.2 0.1 0
10 15 Density variation (%)
8
0.5
5
4
3 2.5 2 1.5 1 0.5 0
5
10 15 Density Variation (%)
0.9 Proposed STNOR STNOR[2] STNOR[19]
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
10 15 Density variation (%) Proposed QNAND QAND[17] QNAND[18]
3.5
Maximum PDP variation (e-18J)
0.1
Proposed STNAND STNAND[2] STNAND[19]
0.6
Maximum PDP Variation (e -17J)
0.12
Maximum PDP variation (e-18j)
0.14
0
Maximum PDP Variation (e -17J)
0.7 Proposed STNOT STNOT[2] STNOT[19]
0.16
Maximum PDP Variation (e -17J)
Maximum PDP variation (-18J)
0.18
5
10 15 Density variation (%) Proposed QNOR QOR[17] QNOR[18]
10 8 6 4 2 0
5
10 15 Density Variation (%)
Fig. 12. Parameter variations of the designs with respect to CNT density variations.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
1.8
1 0.8 0.6 0.4 0.2
3.5 3 2.5 2 1.5 1 0.5 0
10 15 Diameter Variation (%)
5
16 Proposed QNOT QBuffer[17] QNOT[18]
5
6 5 4 3 2 1 5
10 15 Diameter Variation (%)
8 Proposed QNAND QAND[17] QNAND[18]
14 12 10 8 6 4 2 0
10 15 Diameter Variation (%)
Proposed STNOR STNOR[2] STNOR[19]
7
0
10 15 Diameter Variation (%) Maximum PDP Variation (e -17J)
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0
5
Proposed STNAND STNAND[2] STNAND[19]
Maximum PDP Variation (e-18J)
1.2
0
Maximum PDP Variation (e -17J)
Maximum PDP Variation (e-18J)
1.4
8
4
Proposed STNOT STNOT[2] STNOT[19]
1.6
Maximum PDP Variation (e -17J)
Maximum PDP Variation (e-18J)
8
Proposed QNOR QOR[17] QNOR[18]
7 6 5 4 3 2 1 0
5 10 15 Diameter Variation (%)
5
10 15 Diameter Variation (%)
Fig. 13. Parameter variations of the designs with respect to CNT diameter variations.
Maximum PDP (e-18 J)
90 80 70
7 Proposed Design
Proposed Design Design [2] Design [19] Design [18]
6 Maximum PDP (e-15)
100
60 50 40 30
Design [17] Design [18]
5 4 3 2
20 1
10 0
0 STNOT
STNAND
STNOR
Standard Ternary Logic Circuits
QNOT/Buff
QNAND/AND
QNOR/OR
Quaternary Logic Circuits
Fig. 14. PDP variations of the designs with respect to supply voltages variations.
voltage variations on the energy efficiency of the circuits, the cascaded form of the MVL circuits is simulated in the presence of random supply voltage variations. For this purpose, the Monte Carlo simulation has been conducted using Gaussian distributions with 710% variation at the 7 3σ level. The results, shown in Fig. 14, indicate the lower energy consumption of the proposed circuits, except QNAND, even in the presence of random supply voltage variations. In addition, the results of the Monte Carlo DC analyses of the STNOT and QNOT circuits with Gaussian distribution considering 710% variations in process and supply voltages variations at the 73σ level are shown in Fig. 15. As demonstrated in Fig. 15, the voltage transfer characteristic (VTC) curves of the proposed STNOT and QNOT circuits have very steep transition regions and are quite less sensitive to the simultaneous variations of process and supply
voltage as compared to the state-of-the-art pseudo-n-type designs [18]. Noise immunity curve (NIC) is used for evaluating and comparing the noise tolerance of the proposed designs to the input noise pulses. NIC is the locus of noise pulse amplitude (Vnoise) and noise puleswidth (Tnoise). A noise pulse with sufficient width and amplitude may cause the circuit to have a logic error. The area below NIC indicates the safe region and above it indicates the unsafe region. It means that if the noise amplitude is higher at a point on NIC for a particular width then the circuit will output an error. Therefore, higher the NIC of a digital circuit, the more immune the circuit to noise. Noise immunity curves were obtained by simulation using a tunable noise injection circuit described in detail in previous works [27].
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
9
Fig. 15. The results of the Monte Carlo DC analyses considering both process and voltage variations. (a) The proposed QNOT. (b) Pseudo-n-type QNOT [18]. (c) Proposed QNOT. (d) Pseudo-n-type QNOT [18].
Table 6 Noise margins of the ternary STNOTs (VDD ¼ 0.9 V).
Table 7 Noise Margins of the Quaternary NOTs (VDD ¼0.9 V).
Design
NML 021 (mV)
NMH 021 (mV)
NML 122 (mV)
NMH 122 (mV)
Noise margin (mV)
Design
NML NMH NML NMH NML NMH 021 021 122 122 223 223 (mV) (mV) (mV) (mV) (mV) (mV)
Noise margin (mV)
Proposed STNOT STNOT [2] STNOT [18] STNOT [7]
160 150 120 120
280 300 310 180
270 290 220 210
160 150 160 160
160 150 120 120
Proposed QNOT QNOT [17] QNOT [18]
210
80
110
100
210
80
80
180 80
74 45
228 130
85 40
210 180
44 20
44 20
Moreover, noise margins of the ternary and quaternary circuits for all logic level transitions have been measured and are shown in Tables 6 and 7, respectively. According to the results, the proposed designs have larger noise margin as compared with the other state-of-the art CNTFET-based MVL designs. Fig. 16 shows the NIC curves of the ternary and quaternary inverters. The proposed QNOT shows good noise immunity as compared to the other quaternary inverters, also the proposed
STNOT has better noise immunity compared to pseudo-n-type STNOT [18] and complementary CNTFET STNOT [7].
5. Conclusion In this study new energy-efficient and PVT tolerant multiple valued logic (MVL) gates are proposed for nanoelectronics. The
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
10
300 Proposed STNOT STONOT[2] STNOT[18] STNOT[19]
325
Noise Amplitude (mV)
Noise Amplitude (mV)
350
300
275
250
50
100 150 200 Noise width (ps)
250
300
Proposed QNOT QNOT[17] QNOT[18] 250
200
150
50
100
150 200 250 Noise width (ps)
300
Fig. 16. Noise immunity curves for the ternary and quaternary inverters.
proposed CNTFET-based circuits have been designed based on multiple-Vth CNTFETs, using only two distinct CNT diameters for ternary and quaternary designs, which enhances the feasibility and manufacturability of the designs, while the previous quaternary gates require at least three different CNT diameters. The simulation results confirm the superiority of the proposed method compared to the other designs in various simulation conditions as well as in the presence of process, voltage and temperature variations. Based on the simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45% lower PDP as compared to the other designs, respectively. Also the proposed QNOT, QNAND and QNOR circuits have the average PDP enhancement of about 79%, 42% and 61% as compared to the other state-of-the-art designs, respectively.
References [1] S.L. Hurst, Multiple-valued logic—its status and its future, IEEE Trans. Comput. 100 (1984) 1160–1179. [2] M.H. Moaiyeri, A. Doostaregan, K. Navi, Design of energy-efficient and robust ternary circuits for nanotechnology, IET Circuits Devices Syst. 5 (2011) 285–296. [3] E. Dubrova, Multiple-valued logic in VLSI: challenges and opportunities, In: Proceedings of NORCHIP, 1999, pp. 340–350. [4] K. Navi, A. Doostaregan, M.H. Moaiyeri, O. Hashemipour, A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders, Fuzzy Sets Syst. 185 (2011) 111–124. [5] E. Alkaldy, K. Navi, F. Sharifi, M.H. Moaiyeri, An ultra-high-speed (4; 2) compressor with a new design approach for nanotechnology based on the multiinput majority function, J. Comput. Theor. Nanosci. 11 (2014) 1691–1696. [6] K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits, Proc. IEEE 91 (2003) 305–327. [7] S. Lin, Y.-B. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits, IEEE Trans. Nanotechnol. 10 (2011) 217–225. [8] A. Roychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiplevalued logic design, IEEE Trans. Nanotechnol. 4 (2) (2005) 168–179. [9] H. Mouftah, I. Jordan, Integrated circuits for ternary logic, in: Proceedings of the 1974 International Symposium on Multiple-Valued Logic, 1974, pp. 285–302. [10] H. Mouftah, K. Smith, Injected voltage low-power C MOS for 3-valued logic, IEE Proceedings G (Electronic Circuits and Systems), 1982, 270–272. [11] R.C.G. da Silva, H. Boudinov, L. Carro, A novel voltage-mode CMOS quaternary logic design, IEEE Trans. Electron Devices 53 (2006) 1480–1483.
[12] S. Raju Datla, M.A.Thornton, Quaternary voltage-mode logic cells and fixedpoint multiplication circuits in multiple-valued logic (ISMVL), In: Proceedings of the 40th IEEE International Symposium, 2010, pp. 128–133. [13] A. Heung, H. Mouftah, Depletion/enhancement CMOS for a lower power family of three-valued logic circuits, IEEE J. Solid-State Circuits 20 (1985) 609–616. [14] I. Thoidis, D. Soudris, I. Karafyllidis, S. Christoforidis, A. Thanailakis, Quaternary voltage-mode CMOS circuits for multiple-valued logic, IEE Proceedings Circuits Devices and Systems, 1998, pp. 71–77. [15] P. Vasundara, K. Gurumurthy, Quaternary CMOS combinational logic circuits, In: Proceeding of International Conference on Information and Multimedia Technology ICIMT'09, 2009, pp. 538–542. [16] Y. Yasuda, Y. Tokuda, S. Zaima, K. Pak, T. Nakamura, A. Yoshida, Realization of quaternary logic circuits by n-channel MOS devices, IEEE J. Solid-State Circuits 21 (1986) 162–168. [17] M.H. Moaiyeri, K. Navi, O. Hashemipour, Design and evaluation of CNFETbased quaternary circuits, Circuits Syst. Signal Process. 31 (2012) 1631–1652. [18] J. Liang, L. Chen, J. Han, F. Lombardi, Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs, IEEE Trans. Nanotechnol. 13 (2014) 695–708. [19] P.L. McEuen, M.S. Fuhrer, H. Park, Single-walled carbon nanotube electronics, IEEE Trans. Nanotechnol. 1 (2002) 78–85. [20] Y.B. Kim, Y.-B. Kim, F. Lombardi, A novel design methodology to optimize the speed and power of the CNTFET circuits, in: Proceedings of the 52nd IEEE International Midwest Symposium on Circuits and Systems MWSCAS'09, 2009, pp. 1130–1133. [21] A. Raychowdhury, K. Roy, Carbon nanotube electronics: design of highperformance and low-power digital circuits, IEEE Trans. Circuits Syst. I: Regul. Pap. 54 (2007) 2391–2401. [22] J. Deng, H.-S. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the intrinsic channel region, IEEE Trans. Electron Devices 54 (2007) 3186–3194. [23] J. Deng, H.-S. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking, IEEE Trans. Electron Devices 54 (2007) 3195–3205. [24] J. Deng, Device Modeling and Circuit Performance Evaluation for Nanoscale Devices: Silicon Technology Beyond 45 nm Node and Carbon Nanotube Field Effect Transistors (Doctoral dissertation), Stanford University, 2007. [25] J. Zhang, N. Patil, H.-S. Wong, S. Mitra, Overcoming carbon nanotube variations through co-optimized technology and circuit design, In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2011, pp. 4.6.1–4.6.4. [26] S. Lin, Y.-B. Kim, F. Lombardi, Design of a ternary memory cell using CNTFETs, IEEE Trans. Nanotechnol. 11 (2012) 1019–1025. [27] S. Goel, A. Kumar, M.A. Bayoumi, Design of robust, energy-efficient full adders for deep submicrometer design using hybrid-CMOS logic style, IEEE Trans. Very Larg. Scale Integr. Syst. 14 (12) (2006) 1309–1321.
Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i