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n diodes reverse characteristics fabricated by platinum assisted dopant activation
Solid-State Electronics 81 (2013) 19–26
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Room temperature analysis of Ge p+/n diodes reverse characteristics fabricated by platinum assisted dopant activation Vassilios Ioannou-Sougleridis a,⇑, Nikolaos Poulakis a, Panagiotis Dimitrakis a, Pascal Normand a, George P. Patsis b, Athanasios Dimoulas c, Eddy Simoen d a
NSCR ‘‘Demokritos’’, Division of Microelectronics, 153-10 Athens, Greece Technological and Educational Institution (TEI) of Athens, Department of Electronics, Aegaleo, Attiki, Greece NSCR ‘‘Demokritos’’, Division of Materials Science, 153-10 Athens, Greece d Imec, Kapeldreef 75, B-3001 Leuven, Belgium b c
a r t i c l e
i n f o
Article history: Received 24 July 2012 Received in revised form 14 November 2012 Accepted 26 November 2012 Available online 28 February 2013 The review of this paper was arranged by Prof. A. Zaslavsky Keywords: Germanium Junction diodes Generation lifetime Recombination lifetime Diffusion current
a b s t r a c t This work examines the influence of the annealing time at 350 °C to the reverse current and capacitance characteristics of p+/n junction diodes fabricated by platinum assisted dopant activation. The reverse current and capacitance characteristics are first separated into bulk and peripheral components. The bulk or volume component is further analyzed in terms of diffusion and generation currents which constitute the physical components of the bulk reverse current. This allows the extraction of the generation and recombination lifetimes as well as the effective position of the energy levels of the generation–recombination centers. The results indicate that for the used active area geometry, the periphery and the bulk current components coexist in comparable magnitudes. Annealing for 10 min provides the lowest reverse current with the highest generation and recombination lifetimes. Higher annealing times deteriorate the diode due to the formation of defects within the depletion region which reduce the generation and recombination lifetimes. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction As the complementary metal oxide semiconductor (CMOS) devices advance to lower technological nodes, silicon channel devices face significant performance limitations [1–3]. The high electron and hole mobility of germanium offers therefore an alternative channel material for future high-performance CMOS applications [4]. However, germanium front-end processes confront significant integration obstacles, most important of which are the control of the interface properties between the gate dielectric and the germanium channel [5] as well as the formation of functional n+/p shallow junctions [6,7]. Both issues are essential for the successful fabrication of MOS field effect devices. The formation of high drive current shallow n+/p junction diodes under the standard ion-implantation and annealing scheme is impeded by the behavior of the donor dopant atoms (P, As, Sb). These dopants have a low solubility limit in germanium and in addition they exhibit a concentration-enhanced-diffusion effect which results to fastin- and fastout-diffusion thus reducing the attainable dopant concentration in the near surface region
⇑ Corresponding author. Tel.: +30 210 650 3240. E-mail address: [email protected] (V. Ioannou-Sougleridis). 0038-1101/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2012.11.012
[8–11]. As a result typical activated n-type dopant concentrations marginally exceed 5 1019 cm3 after annealing [12]. Nonetheless, alternative approaches have been developed for the realization of functional n+/p diodes. Co-implantation of phosphorus and antimony followed by annealing at 500 °C results to an enhanced solid solubility of the dopants, allowing n-type activation over 1020 cm3 [13]. In addition, well behaved p+/n junctions have been obtained by utilizing local diffusion techniques from a spin-on dopant phosphorus source activated at 700 °C [14]. In our previous work we demonstrated that functional Ge diodes can be fabricated by a Pt-assisted process using annealing temperatures within the range of 300–350 °C. During annealing the platinum layer is transformed into a platinum germanide, as a result of the diffusion of Ge and Pt atoms into the Pt material and the Ge substrate, respectively [15]. This intermixing of the Pt and Ge atoms depends strongly upon the implanted species of the underlying substrate region. Phosphorus implanted regions react very easily with Pt at temperatures as low as 300 °C, leading to fast germanidation rates. In addition, during the transformation process the phosphorus dopants segregate at the boundaries of the germanide layer, which suggests that a snow-plough effect activates the donors. In the case of boron implanted regions the germanidation reaction is slow which is attributed to the negligible boron diffusion in Ge. For both P and B implanted Ge, annealing
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V. Ioannou-Sougleridis et al. / Solid-State Electronics 81 (2013) 19–26 Table 1 List of samples and annealing treatments used in the current study. Sample
Annealing
P1 P2 P3 P4 P5
Un-annealed 350 °C, 5 min 350 °C, 10 min 350 °C, 20 min 350 °C, 30 min
temperatures as low as 300 °C for durations on the order of 10 min, appear to remove implantation damage and improve the series resistance of the diodes. The main advantage of the Pt-assisted dopant activation approach is the low thermal budget required for the formation of the platinum germanide, which allows the fabrication of junctions diodes with high drive current capabilities reaching 400 A/cm2 at less than 1 V forward bias, and acceptable leakage currents in the reverse bias regime. It should be mentioned that a recent review which compares different methods of Ge diode formation showed that for p+/n diodes the approach of Pt assisted p+/n diode formation exhibits very good performance metrics [16]. Our previous work [15] showed that p+/n diodes annealed at 350 °C exhibit high Ion/Ioff ratio but deteriorate for annealing times longer than 10 min. In the present work, we examine the limitations of the Pt-assisted p+/n diode formation encountered during prolonged annealing time at a temperature of 350 °C, by extracting the generation and recombination lifetimes from the reverse-current characteristics of the diodes. The reverse current of a p–n junction constitutes an important indicator of the p–n junction quality. The reverse current that flows through the junction is consisted from the bulk and the periphery components: The former arises from the diffusion and generation current components which flow through the area of the diode and the latter from the diffusion and bulk generation components at the periphery of the junction plus the surface generation component. Therefore, for the extraction of the material parameters such as generation and recombination lifetimes from the reverse current characteristics, a separation of the bulk and the periphery components should be carried out. This is accomplished via a separation of the reverse current and capacitance characteristics into bulk and periphery components. Furthermore, by combining the above data, the bulk current can be separated into diffusion and generation parts via the so-called bulk current versus depletion width graphical method [17,18]. The determination of the physical current components allows for the extraction of the diode generation and recombination lifetimes. Analysis of the experimental results by the above procedure provides a detailed characterization of the diodes at room temperature and reveals that a time limit exists in the annealing process above which defect generation phenomena occur within the diode depletion region (see Table 1). 2. Experimental For the fabrication of the p+/n junction diodes, (1 0 0) germanium substrates were used. After removal of the native oxide, a 100 nm SiOx layer was deposited by sputtering onto the Ge substrate, followed by a densification annealing at 450 °C for 30 min in O2 ambient. The active areas were defined by photolithography and wet etching. Three square diode sets with different edge lengths (EL) have been used in this study and are referred hereafter to as A (EL = 300 lm), B (100 lm) and C (50 lm). Subsequently, 50 keV BF2 ion implantation was performed to a dose of 2 1015 cm2 at a low current for avoiding photoresist degradation. Then, a 50 nm-thick Pt layer was e-beam deposited and a lift-off process was applied to the samples, which further received an isothermal furnace annealing step at 350 °C for times ranging from 5 to
30 min (see Table 1). A non-annealed sample was used as a reference to determine the initial status of the diodes and the influence of annealing. Finally, the ohmic back contact was formed by InGa paste. Further details about the fabrication sequence of the samples can be found in [15]. Current–voltage (I–V) and capacitance–voltage (C–V) measurements were performed at room temperature (297 K) within a probe station in dark conditions, using a 4140B picoammeter and a 4284A LCR meter, respectively. The I–V measurements were performed within the range of 2 V to 2 V, starting from the reverse regime, with a 20 mV step. The C–V measurements were performed from 0 V to 5 V with a 20 mV step and a frequency of 1 MHz. The noise floors of the measurement systems are 0.03 pF for the C–V and 0.05 pA for the I–V measurements. 3. Results and discussion 3.1. Reverse current and capacitance separation into bulk and periphery components The separation of the diode reverse current into bulk and peripheral components is based upon the assumption that the total diode current is a linear combination of these components. More detailed analysis considers also the influence of the parasitic current originating from the measurement system, as well as the current flowing through the corners of the diode [19]. Furthermore, the typical analysis requires special test structures to minimize calculation errors [20,21]. The analysis that has been performed in this study utilizes three sets of square diodes with different edge lengths. Initially, the reverse current of the junction diodes of the three sets was measured to establish the typical behavior of the diodes. The bulk and peripheral currents were extracted using the data from the A and B sets according to the equations [17]:
ImeasA ¼ AA J B þ PA J P
ð1Þ
ImeasB ¼ AB J B þ PB J P
ð2Þ 2
where JB is the bulk current density (A/cm ), JP refers to the peripheral current density (A/cm), and AA (AB) and PA (PB) are, respectively, the area (cm2) and periphery (cm) of the set A (B). The extracted JB and JP values were used to calculate the reverse current of the third set (C), IC = AC JB + PC JP which was then compared to the experimental results in order to validate the consistency of the calculation procedure. Fig. 1a and b shows the reverse diode currents of the 350 °C/5 min-annealed sample A and B sets, while Fig. 1c shows the comparison between the measured (ImeasC) and the calculated (IC) currents of the third set (C). Fig. 1d shows the relative error between the measured and calculated currents which is lower than 1%. This outcome provide confidence for the employed approach, despite the lack of special test structures. Similar results were obtained from the rest of the samples with the values of the relative error being lower than 1% at diode bias higher than 0.5 V. The diode capacitance measurements were initially checked for series resistance (Rs) distortions. Rs was extracted from the high-forward current regime as can be seen in the inset of Fig. 2. The corrected capacitance Ccor for series resistance is provided by [22]:
C cor ¼ F cor C m
ð3Þ
with;F cor ¼ ½ð1 Rs Gm Þ2 þ ðRs xC m Þ2 1 where Cm and Gm are, respectively, the measured capacitance and conductance values, and x is the angular frequency (x = 2pf, with f = 1 MHz) employed in the measurement. This calculation revealed that the correction factor (Fcor) is very close to unity and therefore,
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Fig. 1. Reverse I–V average characteristics of set A (a) and B (b) diodes of the sample annealed at 350 °C/5 min. These two characteristics were used to calculate the bulk and periphery contributions to the total diode current. (c) Comparison between the calculated and the measured average current of set C. (d) Relative error between the measured and the calculated data. The above result signifies the validity of the used separation procedure.
Fig. 2. Measured and series resistance corrected C–V curves for the case of 350 °C/10 min annealed sample. Inset: series resistance extraction from the high forward current region.
the series resistance does not distort the C–V measurements as can be seen in Fig. 2. Subsequently, the diode capacitance was separated into bulk (CB) and peripheral (CP) components using the previous approach. Fig. 3a shows the capacitance characteristics in the reverse bias regime of the A and B sets which was used to extract the CB and CP components, while in Fig. 3b a comparison is made between the calculated and the measured capacitance characteristics of the third diode set (C). In this case a good matching between the calculated and measured C–V curves can be obtained after adding to the calculated capacitance 0.1 pF which has been attributed to a parasitic capacitance of the measured device. Fig. 4 shows the total reverse current of the 5 min-annealed sample which flows through the diodes together with the bulk and periphery currents. For the A set (Fig. 4a), the bulk current is higher than the peripheral one, in the B set both currents are com-
parable, while for the C set the peripheral current is two times higher than the bulk current. It is therefore evident that in all examined sets the two current components co-exist and there is no case where one component is significantly the dominant one. The capacitance component contribution of the three sets is shown in Fig. 5. The peripheral capacitance for all sets is rather constant with the applied reverse bias and scales with the periphery. Therefore, the bulk capacitance provides the variation of the total capacitance with the reverse bias. The relative magnitude of the capacitance components follows the trend of the currents depicted in Fig. 4. In set A the bulk component is higher that the peripheral one, in the B set both components are comparable, and in the C set the peripheral component is the highest one. Fig. 6a and b shows the extracted bulk and peripheral current components of all samples under study. The observed trend of the bulk current component as a function of the annealing time follows that of the total reverse current, where the smallest current was obtained after 10 min annealing time. The peripheral current components can be separated into two groups. The lowest currents are those of the 5 and 10 min annealing times while the higher currents are those of the 20 and 30 min. The results of the capacitance separation procedure into bulk and peripheral components are provided in Fig. 7a and b. In comparison to the unannealed sample the bulk capacitance increases after 5 min annealing and then remains unaltered for annealing times up to 30 min. While, the peripheral capacitance component undergoes a significant reduction upon 5 min annealing compared with the unannealed samples, no significant dependence on the annealing time is detected for the other set of samples. 3.2. Extraction of bulk physical parameters The above analysis of the diode current and capacitance in the reverse bias regime into bulk and periphery components was used to evaluate important physical parameters which determine the
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Fig. 3. (a) Reverse C–V characteristics of set A and B diodes of sample annealed at 350 °C/5 min, which were used to extract the bulk and periphery components to the total capacitance. (b) Comparison between the calculated and the measured capacitance components of set DC. A good between the two capacitances is obtained after adding 0.1 pF which was attributed to a parasitic capacitance of the measured device.
diode operation. Using the bulk capacitance component per unit area (CB), the depletion layer width, WB, and the apparent free carrier density (NB) profile of the junction diodes can be extracted according to the relations [23]:
WB ¼
NB ¼
eGe eo
ð4Þ
CB 2
q eGe eo
dC 2 B dV
ð5Þ
where q is the electronic charge, eGe is the permittivity of germanium and eo the dielectric constant of vacuum. Fig. 8 shows the apparent carrier density profile as a function of the depletion width of the samples under study. As evident the accessible depletion depth by the C–V profiling reaches 500 nm from the junction. For the unannealed sample the substrate carrier density is 2 1014 cm3 at a depth of 2 lm. Towards the junction the carrier density drops to 1 1014 cm3. This is attributed to ionimplantation induced defects. After 5 min annealing at 350 °C, the carrier density increases to 4 1014 cm3 at a distance of about 1.3 lm. The extracted carrier density of the annealed samples corresponds to a resistivity of 3 X cm, which is very close to the initial substrate resistivity. Towards the junction the carrier density decreases again to 2 1014 cm3 probably due to remaining ion implantation-related-defects. Further annealing does not induce major improvements in the carrier density profile. The profiles of the annealed samples after 2–2.5 lm show significant noise due to the small capacitances values and a reduction tendency towards the bulk. Finally, the difference in carrier density deep in the substrate between the as-implanted and the annealed samples can be attributed to parasitic elements of the asimplanted samples such as shunt resistances [24].
Fig. 4. Comparison between bulk, periphery and total reverse currents of sample annealed at 350 °C/10 min. (a) Set A. (b) Set B. (c) Set C. In all cases comparable magnitudes of the bulk and periphery currents are encountered.
The reverse bulk current consists from a diffusion current component (JBDiff) and a generation component (JBGen) [17]:
J B ¼ J BDiff þ J BGen
ð6Þ
The typical assumption is that the diffusion part is bias independent and the generation part increases linearly with the reverse bias or with the depletion width. Therefore, by constructing a JB vs WB plot the diffusion component can be obtained from the linear interpolation to zero depletion width, while the slope of the linear part of the graph provides the generation rate (dJB/dWB) of the carriers within the junction depletion region [17]. Fig. 9 shows the resulting JB–WB plot of all examined annealing regimes. The unannealed samples exhibit a stronger than linear dependence of JB on WB, which can be attributed to electric field assisted thermal generation, or to a profile in the generation lifetime [20]. The annealed samples, however, show a clear linear dependence allowing therefore the determination of both the diffusion current and the generation rate. As the annealing time increases from 5 to 10 min the diffusion current decreases marginally and then shows a pronounced increase for 20 and 30 min annealing. The bulk diffusion current is given by [21]:
J BDiff ¼
qn2i
sffiffiffiffiffiffi "sffiffiffiffiffiffiffiffi # Dn 1 Dp 1 þ sn N A sp N D
ð7Þ
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Fig. 6. Bulk (a) and periphery (b) reverse current components of all measured samples.
Fig. 5. Comparison between bulk, periphery and total capacitance of sample annealed at 350 °C/5 min. (a) Set A. (b) Set B. (c) Set C.
where Dn is the electron diffusion constant and sn the electron recombination lifetime in the p-side of the junction. Dp is the hole diffusion constant and sp the hole recombination lifetime in the n-side of the junction. Eq. (5) shows that the diffusion current is determined by the doping density in both sides of the junction and the corresponding recombination lifetimes. Since the diode is herein asymmetric (p+/n) the first term is usually neglected and the diffusion current is mainly determined by the low-doped region. The diffusion current is regarded as a fundamental lower limit of the reverse current at room temperature and, in a first approximation, is independent of the reverse bias [17]. Therefore, the marginal decrease of the diffusion current after 10 min annealing can be attributed to the beneficial effects of annealing which reduces the process induced damage thus increasing the recombination lifetimes and the doping density in both sides of the junction. Moreover, the pronounced increase of the diffusion current at longer annealing times indicates a deterioration of the diode, due to an effective increase of the active recombination–generation centers within the germanium band-gap. Fig. 9 indicates that the generation current in the annealed samples constitutes a significant portion of the total reverse current, which at 2 V reaches almost 50%. The generation lifetime of the diodes can be calculated by [17]:
sg ¼
q ni dJB dW B
ð8Þ
Fig. 7. Bulk (a) and periphery (b) capacitance components of all measured samples.
In addition, the recombination lifetime can also be evaluated under the assumption of a realistic diffusion length (Dp) according to [17]:
sr
q2 n4i J 2BDiff
N2D
Dp
ð9Þ
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Fig. 8. Apparent carrier density profile of all measured samples extracted using the bulk capacitance component.
Fig. 9. Plot of bulk current density as a function of the depletion width.
Eq. (7) derives from (5) after omitting the terms of the heavily doped boron side. Therefore the calculated recombination lifetime corresponds to the recombination of holes within the low-doped nside. A Dp value of 50 cm2/s was used which corresponds to a hole mobility of 2000 cm2/V s [25]. Fig. 10 compares the diffusion current with the corresponding generation and recombination lifetimes. The graphs indicate that all these parameters follow the same trend. As the diffusion current takes the lowest value for the 10 min annealing regime, sg and sr acquire their highest values while for longer annealing times both lifetimes decrease. Finally from sg and sr it is possible to estimate the quantity |Et Ei| which gives the position of the effective generation recombination level, Et, with respect to the intrinsic Fermi level, Ei, in accordance with [18]:
sg jEt Ei j ffi exp kT sr
ð10Þ
As it has been noticed in the case where multiple trap levels coexist within a diode, Et represents an effective trap level which is the weighted influence of all these energy levels [21]. Fig. 10c shows the behavior of the effective energy level with the annealing time. As the annealing time increases, Et has a tendency to shift by 0.007 eV from the mid-gap. The above results are also consistent with the diodes ideality factor where the lowest value (1.31) was obtained for the case of the 350 °C/10 min annealing sample. Table 2 summarizes all the key results of the present study. The peripheral capacitance characteristics indicate a rather constant response to the reverse bias. Taking also into account the fact that no particular measures were taken to passivate the
Fig. 10. Bulk diffusion current (a), generation lifetime, and recombination lifetime (b) and (c) effective trap energy level shift with annealing time of all annealed samples.
Table 2 Bulk diffusion current, generation and recombination lifetimes, effective trap level distance from midgap, and ideality factor of all diodes examined in this study. Sample
Annealing at 350 °C
JB (A/cm2)
sg (ls)
sr (ls)
|Et Ei| (eV)
n
P2 P3 P4 P5
5 min 10 min 20 min 30 min
7.58 104 6.96 104 8.95 104 1.2 103
1.76 1.945 1.249 0.9
2.22 2.64 1.6 0.9
0.018 0.016 0.017 0.024
1.35 1.31 1.36 1.41
surface region at the edges of the diodes, the constant capacitance suggests a rather constant lateral depletion width due to Fermi level pinning at the exposed surface states. Such a condition provides an interpretation of the relatively high peripheral current component. 3.3. Temperature dependent measurements Fig. 11 shows the reverse diode current Arrhenius plots of the unannealed sample and samples annealed at 350 °C for 10 and 30 min, all recorded from the A set diodes at reverse bias of 1 V. In the case of the unannealed sample the Arrhenius plot of the reverse current shows two distinct linear regions. The first, from 170 K to 270 K, corresponds to an activation energy of EA2 = 0.38 eV which indicates that the reverse current is due to a trap assisted generation mechanism. Above 270 K the activation energy is EA1 = 0.68 eV, which suggests a diffusion current via a
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Fig. 11. Arrhenius plots of the reverse current recorded from set A diodes at a reverse bias of 1 V. (a) Unannealed, (b) 350 °C/10 min and (c) 350 °C/30 min samples.
band-to-band mechanism. For the sample annealed for 10 min the transition between the two mechanisms occurs at 250 K, denoting the suppression of the midgap-state generation mechanism. While the value of EA2 remains the same, EA1 decreases to 0.53 eV. This change in EA1 value from the Ge band-gap energy may indicate the involvement of shallow hole-traps in the band-gap which determine the high-temperature mechanism of electron–hole generation, i.e. the value of EA1. Finally, the reverse current in the case of the 30 min annealing sample shows a single activation energy of 0.43 eV up to 290 K. This new energy level may be attributed to the interaction of the initial midgap state with the shallow states induced by the annealing process. Therefore the dominant contribution of the reverse current at room temperature for the case of the 30 min annealed sample arises from defect states with an effective activation energy of 0.43 eV. In addition, at room temperature the reverse current of the unannealed and the 350 °C/10 min annealed samples is actually controlled from diffusion while for the 350 °C/ 30 min annealed sample it is still controlled from deep centers. Additional information was provided from deep level transient spectroscopy measurements (DLTS) performed on diodes from the same split, which revealed the presence of several deep levels at the limits of the system detection [26]. Upon annealing for 30 min at 350 °C the DLTS height of these levels was found to decrease slightly, while a pronounced hole trap was recorded. This behavior is consistent with the previously mentioned activation energies and indicates that these defects must not be related to Pt in diffusion but possibly associated with the evolution and clustering of ion-implantation and/or sputtering related defects. The creation of such defects is probably the reason for the higher reverse current observed for annealing times longer than 10 min. Although Sockley–Read–Hall theory anticipates that the most efficient recombination centers should lie close to the midgap of a semiconductor the increased density of defects with an effective activation energy of 0.43 eV may explain the deterioration of the diode characteristics at longer annealing times. Recombination lifetimes in Ge substrates has been thoroughly studied using optical excitation methods [27,28]. These studies showed that the recombination lifetime is strongly substrate doping dependent. For the case of a n-type Ge substrate with a doping density within the range of 1 1015 cm3 the estimated recombination lifetime is about 20 ls. Previous studies performed on Ge diodes during the 1950’s reported lifetime values around 1– 100 ls [29]. It is therefore evident that the values extracted in this study (1–2 ls) are quite reasonable and expected, considering that defect states are present due to the sputtering and ion-implantation processes. In addition, comparison with silicon lifetimes in Czochralski type substrates also show that either recombination or generation lifetimes within the ls range are also typical [17].
4. Conclusions In this work we studied the influence of the annealing time at 350 °C to the reverse characteristics of p+/n junctions fabricated by platinum assisted dopant activation. At first the diode current and capacitance characteristics in the reverse bias regime were separated into bulk and peripheral components. This analysis indicated that in all examined geometries both components have comparable magnitudes. Further analysis of the bulk diode characteristics revealed that the generation current component has a significant contribution to the overall reverse current. The generation and recombination lifetimes were found within the range of the microsecond regime with the highest values after an annealing time of 10 min which for the 350 °C regime constitutes a compromise between two opposite trends, the annealing of process related defects and the creation of defect centers within the diode active region. It should be finally mentioned that the low process temperature of the diode formation assisted by metals such as Co or Pt may constitute a promising approach for Ge transistor fabrication towards the realization of 3-D integrated circuits [30]. References [1] Kamata Y. Mater Today 2008;11:30. [2] Heyns M, Tsai W. MRS Bull 2009;34:485. [3] Saraswat K, Chui CO, Krishnamohan T, Kim D, Nayfeh A, Pethe A. Mater Sci Eng B 2005;135:242. [4] Claeys C, Mitard J, Eneman G, Meuris M, Simoen E. Thin Solid Films 2010;518:2301. [5] Toriumi A, Tabata T, Lee CH, Nishimura T, Kita K, Nagashio K. Microelectron Eng 2009;86:1571. [6] Chui CC, Kulig L, Moran J, Tsai W, Saraswat KC. Appl Phys Lett 2005;87:091909. [7] Satta A, Janssens T, Clarysse T, Simoen E, Meuris M, Benedetti A, et al. J Vac Sci Technol B 2006;24:494. [8] Ioannou N, Skarlatos D, Tsamis C, Krontiras CA, Georga SN, Christofi A, et al. Appl Phys Lett 2008;93:101910. [9] Simoen E et al. Mater Sci Semicond Proc 2006;9:634. [10] Tsouroutas P, Tsoukalas D, Zergioti I, Cherkaskin N, Claverie A. J Appl Phys 2009;105:094910. [11] Satta A, D’Amore A, Simoen E, Anward W, Skorupa W, Clarysse T, et al. Nucl Instr Method B 2007;257:157. [12] Wundisch C, Posselt M, Schmidt B, Heera V, Schumann T, Mucklich A, et al. Appl Phys Lett 2009;95:252107. [13] Kim J, Bedell SW, Maurer SL, Loesing R, Sadana DK. Electrochem Solid-State Lett 2010;13:H12. [14] Jamil M, Mantey J, Onyegam EU, Carpenter GD, Tutuc E, Banerjee SK. IEEE Electron Device Lett 2011;32:1203. [15] Ioannou-Sougleridis V, Galata SF, Golias E, Speliotis T, Dimoulas A, Giubertoni D, et al. Microelectron Eng 2012;88:254. [16] Duffy R, Shayesteh M. ECS Trans 2012;45:189. [17] Murakami Y, Shingyouji T. J Appl Phys 1994;75:3548. [18] Simoen E, Claeys C, Czerwinski A, Katcki J. Appl Phys Lett 1988;72:1054. [19] Poyai A, Simoen E, Clayes C, Rooyackers R, Badenes G. J Electrochem Soc 2001;148:G507.
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[20] Claeys C, Poyai A, Simoen E, Czerwinski A, Katcki J. J Electrochem Soc 1999;146:1151. [21] Aharoni H, Ohmi T, Oka MM, Nakada A, Tamai Y. J Appl Phys 1997;81:1270. [22] Poyai A, Claeys C, Simoen E. Appl Phys Lett 2002;80:1192. [23] Schroder DK. Semiconductor material and device characterization. 2nd ed. New York: Wiley; 1998. p. 64. [24] Straub A, Habenicht R, Trunk S, Bardos RA, Sproul AB, Aberle AG. J Appl Phys 2005;97:083703.
[25] Sze SM. Physics of semiconductor devices. 2nd ed. New York: Wiley; 1981. [26] Simoen E, Lauwaert J, Vrielinck H, Ioannou-Sougleridis V, Dimoulas A. ECS Trans 2011;41:299. [27] Gaubas E, Vanhellemont J. J Electrochem Soc 2007;154:H231. [28] Poelman D, Clauws P, Depuydt B. Sol Energy Mater Sol Cells 2003;76:167. [29] Hall RN. Phys Rev 1952;87:387. [30] Park JH, Kuzum D, Jung WS, Saraswat KC. IEEE Trans Electron Device Lett 2011;32:234.
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Room temperature analysis of Ge p+/n diodes reverse characteristics fabricated by platinum assisted dopant activation Vassilios Ioannou-Sougleridis a,⇑, Nikolaos Poulakis a, Panagiotis Dimitrakis a, Pascal Normand a, George P. Patsis b, Athanasios Dimoulas c, Eddy Simoen d a
NSCR ‘‘Demokritos’’, Division of Microelectronics, 153-10 Athens, Greece Technological and Educational Institution (TEI) of Athens, Department of Electronics, Aegaleo, Attiki, Greece NSCR ‘‘Demokritos’’, Division of Materials Science, 153-10 Athens, Greece d Imec, Kapeldreef 75, B-3001 Leuven, Belgium b c
a r t i c l e
i n f o
Article history: Received 24 July 2012 Received in revised form 14 November 2012 Accepted 26 November 2012 Available online 28 February 2013 The review of this paper was arranged by Prof. A. Zaslavsky Keywords: Germanium Junction diodes Generation lifetime Recombination lifetime Diffusion current
a b s t r a c t This work examines the influence of the annealing time at 350 °C to the reverse current and capacitance characteristics of p+/n junction diodes fabricated by platinum assisted dopant activation. The reverse current and capacitance characteristics are first separated into bulk and peripheral components. The bulk or volume component is further analyzed in terms of diffusion and generation currents which constitute the physical components of the bulk reverse current. This allows the extraction of the generation and recombination lifetimes as well as the effective position of the energy levels of the generation–recombination centers. The results indicate that for the used active area geometry, the periphery and the bulk current components coexist in comparable magnitudes. Annealing for 10 min provides the lowest reverse current with the highest generation and recombination lifetimes. Higher annealing times deteriorate the diode due to the formation of defects within the depletion region which reduce the generation and recombination lifetimes. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction As the complementary metal oxide semiconductor (CMOS) devices advance to lower technological nodes, silicon channel devices face significant performance limitations [1–3]. The high electron and hole mobility of germanium offers therefore an alternative channel material for future high-performance CMOS applications [4]. However, germanium front-end processes confront significant integration obstacles, most important of which are the control of the interface properties between the gate dielectric and the germanium channel [5] as well as the formation of functional n+/p shallow junctions [6,7]. Both issues are essential for the successful fabrication of MOS field effect devices. The formation of high drive current shallow n+/p junction diodes under the standard ion-implantation and annealing scheme is impeded by the behavior of the donor dopant atoms (P, As, Sb). These dopants have a low solubility limit in germanium and in addition they exhibit a concentration-enhanced-diffusion effect which results to fastin- and fastout-diffusion thus reducing the attainable dopant concentration in the near surface region
⇑ Corresponding author. Tel.: +30 210 650 3240. E-mail address: [email protected] (V. Ioannou-Sougleridis). 0038-1101/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2012.11.012
[8–11]. As a result typical activated n-type dopant concentrations marginally exceed 5 1019 cm3 after annealing [12]. Nonetheless, alternative approaches have been developed for the realization of functional n+/p diodes. Co-implantation of phosphorus and antimony followed by annealing at 500 °C results to an enhanced solid solubility of the dopants, allowing n-type activation over 1020 cm3 [13]. In addition, well behaved p+/n junctions have been obtained by utilizing local diffusion techniques from a spin-on dopant phosphorus source activated at 700 °C [14]. In our previous work we demonstrated that functional Ge diodes can be fabricated by a Pt-assisted process using annealing temperatures within the range of 300–350 °C. During annealing the platinum layer is transformed into a platinum germanide, as a result of the diffusion of Ge and Pt atoms into the Pt material and the Ge substrate, respectively [15]. This intermixing of the Pt and Ge atoms depends strongly upon the implanted species of the underlying substrate region. Phosphorus implanted regions react very easily with Pt at temperatures as low as 300 °C, leading to fast germanidation rates. In addition, during the transformation process the phosphorus dopants segregate at the boundaries of the germanide layer, which suggests that a snow-plough effect activates the donors. In the case of boron implanted regions the germanidation reaction is slow which is attributed to the negligible boron diffusion in Ge. For both P and B implanted Ge, annealing
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V. Ioannou-Sougleridis et al. / Solid-State Electronics 81 (2013) 19–26 Table 1 List of samples and annealing treatments used in the current study. Sample
Annealing
P1 P2 P3 P4 P5
Un-annealed 350 °C, 5 min 350 °C, 10 min 350 °C, 20 min 350 °C, 30 min
temperatures as low as 300 °C for durations on the order of 10 min, appear to remove implantation damage and improve the series resistance of the diodes. The main advantage of the Pt-assisted dopant activation approach is the low thermal budget required for the formation of the platinum germanide, which allows the fabrication of junctions diodes with high drive current capabilities reaching 400 A/cm2 at less than 1 V forward bias, and acceptable leakage currents in the reverse bias regime. It should be mentioned that a recent review which compares different methods of Ge diode formation showed that for p+/n diodes the approach of Pt assisted p+/n diode formation exhibits very good performance metrics [16]. Our previous work [15] showed that p+/n diodes annealed at 350 °C exhibit high Ion/Ioff ratio but deteriorate for annealing times longer than 10 min. In the present work, we examine the limitations of the Pt-assisted p+/n diode formation encountered during prolonged annealing time at a temperature of 350 °C, by extracting the generation and recombination lifetimes from the reverse-current characteristics of the diodes. The reverse current of a p–n junction constitutes an important indicator of the p–n junction quality. The reverse current that flows through the junction is consisted from the bulk and the periphery components: The former arises from the diffusion and generation current components which flow through the area of the diode and the latter from the diffusion and bulk generation components at the periphery of the junction plus the surface generation component. Therefore, for the extraction of the material parameters such as generation and recombination lifetimes from the reverse current characteristics, a separation of the bulk and the periphery components should be carried out. This is accomplished via a separation of the reverse current and capacitance characteristics into bulk and periphery components. Furthermore, by combining the above data, the bulk current can be separated into diffusion and generation parts via the so-called bulk current versus depletion width graphical method [17,18]. The determination of the physical current components allows for the extraction of the diode generation and recombination lifetimes. Analysis of the experimental results by the above procedure provides a detailed characterization of the diodes at room temperature and reveals that a time limit exists in the annealing process above which defect generation phenomena occur within the diode depletion region (see Table 1). 2. Experimental For the fabrication of the p+/n junction diodes, (1 0 0) germanium substrates were used. After removal of the native oxide, a 100 nm SiOx layer was deposited by sputtering onto the Ge substrate, followed by a densification annealing at 450 °C for 30 min in O2 ambient. The active areas were defined by photolithography and wet etching. Three square diode sets with different edge lengths (EL) have been used in this study and are referred hereafter to as A (EL = 300 lm), B (100 lm) and C (50 lm). Subsequently, 50 keV BF2 ion implantation was performed to a dose of 2 1015 cm2 at a low current for avoiding photoresist degradation. Then, a 50 nm-thick Pt layer was e-beam deposited and a lift-off process was applied to the samples, which further received an isothermal furnace annealing step at 350 °C for times ranging from 5 to
30 min (see Table 1). A non-annealed sample was used as a reference to determine the initial status of the diodes and the influence of annealing. Finally, the ohmic back contact was formed by InGa paste. Further details about the fabrication sequence of the samples can be found in [15]. Current–voltage (I–V) and capacitance–voltage (C–V) measurements were performed at room temperature (297 K) within a probe station in dark conditions, using a 4140B picoammeter and a 4284A LCR meter, respectively. The I–V measurements were performed within the range of 2 V to 2 V, starting from the reverse regime, with a 20 mV step. The C–V measurements were performed from 0 V to 5 V with a 20 mV step and a frequency of 1 MHz. The noise floors of the measurement systems are 0.03 pF for the C–V and 0.05 pA for the I–V measurements. 3. Results and discussion 3.1. Reverse current and capacitance separation into bulk and periphery components The separation of the diode reverse current into bulk and peripheral components is based upon the assumption that the total diode current is a linear combination of these components. More detailed analysis considers also the influence of the parasitic current originating from the measurement system, as well as the current flowing through the corners of the diode [19]. Furthermore, the typical analysis requires special test structures to minimize calculation errors [20,21]. The analysis that has been performed in this study utilizes three sets of square diodes with different edge lengths. Initially, the reverse current of the junction diodes of the three sets was measured to establish the typical behavior of the diodes. The bulk and peripheral currents were extracted using the data from the A and B sets according to the equations [17]:
ImeasA ¼ AA J B þ PA J P
ð1Þ
ImeasB ¼ AB J B þ PB J P
ð2Þ 2
where JB is the bulk current density (A/cm ), JP refers to the peripheral current density (A/cm), and AA (AB) and PA (PB) are, respectively, the area (cm2) and periphery (cm) of the set A (B). The extracted JB and JP values were used to calculate the reverse current of the third set (C), IC = AC JB + PC JP which was then compared to the experimental results in order to validate the consistency of the calculation procedure. Fig. 1a and b shows the reverse diode currents of the 350 °C/5 min-annealed sample A and B sets, while Fig. 1c shows the comparison between the measured (ImeasC) and the calculated (IC) currents of the third set (C). Fig. 1d shows the relative error between the measured and calculated currents which is lower than 1%. This outcome provide confidence for the employed approach, despite the lack of special test structures. Similar results were obtained from the rest of the samples with the values of the relative error being lower than 1% at diode bias higher than 0.5 V. The diode capacitance measurements were initially checked for series resistance (Rs) distortions. Rs was extracted from the high-forward current regime as can be seen in the inset of Fig. 2. The corrected capacitance Ccor for series resistance is provided by [22]:
C cor ¼ F cor C m
ð3Þ
with;F cor ¼ ½ð1 Rs Gm Þ2 þ ðRs xC m Þ2 1 where Cm and Gm are, respectively, the measured capacitance and conductance values, and x is the angular frequency (x = 2pf, with f = 1 MHz) employed in the measurement. This calculation revealed that the correction factor (Fcor) is very close to unity and therefore,
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Fig. 1. Reverse I–V average characteristics of set A (a) and B (b) diodes of the sample annealed at 350 °C/5 min. These two characteristics were used to calculate the bulk and periphery contributions to the total diode current. (c) Comparison between the calculated and the measured average current of set C. (d) Relative error between the measured and the calculated data. The above result signifies the validity of the used separation procedure.
Fig. 2. Measured and series resistance corrected C–V curves for the case of 350 °C/10 min annealed sample. Inset: series resistance extraction from the high forward current region.
the series resistance does not distort the C–V measurements as can be seen in Fig. 2. Subsequently, the diode capacitance was separated into bulk (CB) and peripheral (CP) components using the previous approach. Fig. 3a shows the capacitance characteristics in the reverse bias regime of the A and B sets which was used to extract the CB and CP components, while in Fig. 3b a comparison is made between the calculated and the measured capacitance characteristics of the third diode set (C). In this case a good matching between the calculated and measured C–V curves can be obtained after adding to the calculated capacitance 0.1 pF which has been attributed to a parasitic capacitance of the measured device. Fig. 4 shows the total reverse current of the 5 min-annealed sample which flows through the diodes together with the bulk and periphery currents. For the A set (Fig. 4a), the bulk current is higher than the peripheral one, in the B set both currents are com-
parable, while for the C set the peripheral current is two times higher than the bulk current. It is therefore evident that in all examined sets the two current components co-exist and there is no case where one component is significantly the dominant one. The capacitance component contribution of the three sets is shown in Fig. 5. The peripheral capacitance for all sets is rather constant with the applied reverse bias and scales with the periphery. Therefore, the bulk capacitance provides the variation of the total capacitance with the reverse bias. The relative magnitude of the capacitance components follows the trend of the currents depicted in Fig. 4. In set A the bulk component is higher that the peripheral one, in the B set both components are comparable, and in the C set the peripheral component is the highest one. Fig. 6a and b shows the extracted bulk and peripheral current components of all samples under study. The observed trend of the bulk current component as a function of the annealing time follows that of the total reverse current, where the smallest current was obtained after 10 min annealing time. The peripheral current components can be separated into two groups. The lowest currents are those of the 5 and 10 min annealing times while the higher currents are those of the 20 and 30 min. The results of the capacitance separation procedure into bulk and peripheral components are provided in Fig. 7a and b. In comparison to the unannealed sample the bulk capacitance increases after 5 min annealing and then remains unaltered for annealing times up to 30 min. While, the peripheral capacitance component undergoes a significant reduction upon 5 min annealing compared with the unannealed samples, no significant dependence on the annealing time is detected for the other set of samples. 3.2. Extraction of bulk physical parameters The above analysis of the diode current and capacitance in the reverse bias regime into bulk and periphery components was used to evaluate important physical parameters which determine the
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Fig. 3. (a) Reverse C–V characteristics of set A and B diodes of sample annealed at 350 °C/5 min, which were used to extract the bulk and periphery components to the total capacitance. (b) Comparison between the calculated and the measured capacitance components of set DC. A good between the two capacitances is obtained after adding 0.1 pF which was attributed to a parasitic capacitance of the measured device.
diode operation. Using the bulk capacitance component per unit area (CB), the depletion layer width, WB, and the apparent free carrier density (NB) profile of the junction diodes can be extracted according to the relations [23]:
WB ¼
NB ¼
eGe eo
ð4Þ
CB 2
q eGe eo
dC 2 B dV
ð5Þ
where q is the electronic charge, eGe is the permittivity of germanium and eo the dielectric constant of vacuum. Fig. 8 shows the apparent carrier density profile as a function of the depletion width of the samples under study. As evident the accessible depletion depth by the C–V profiling reaches 500 nm from the junction. For the unannealed sample the substrate carrier density is 2 1014 cm3 at a depth of 2 lm. Towards the junction the carrier density drops to 1 1014 cm3. This is attributed to ionimplantation induced defects. After 5 min annealing at 350 °C, the carrier density increases to 4 1014 cm3 at a distance of about 1.3 lm. The extracted carrier density of the annealed samples corresponds to a resistivity of 3 X cm, which is very close to the initial substrate resistivity. Towards the junction the carrier density decreases again to 2 1014 cm3 probably due to remaining ion implantation-related-defects. Further annealing does not induce major improvements in the carrier density profile. The profiles of the annealed samples after 2–2.5 lm show significant noise due to the small capacitances values and a reduction tendency towards the bulk. Finally, the difference in carrier density deep in the substrate between the as-implanted and the annealed samples can be attributed to parasitic elements of the asimplanted samples such as shunt resistances [24].
Fig. 4. Comparison between bulk, periphery and total reverse currents of sample annealed at 350 °C/10 min. (a) Set A. (b) Set B. (c) Set C. In all cases comparable magnitudes of the bulk and periphery currents are encountered.
The reverse bulk current consists from a diffusion current component (JBDiff) and a generation component (JBGen) [17]:
J B ¼ J BDiff þ J BGen
ð6Þ
The typical assumption is that the diffusion part is bias independent and the generation part increases linearly with the reverse bias or with the depletion width. Therefore, by constructing a JB vs WB plot the diffusion component can be obtained from the linear interpolation to zero depletion width, while the slope of the linear part of the graph provides the generation rate (dJB/dWB) of the carriers within the junction depletion region [17]. Fig. 9 shows the resulting JB–WB plot of all examined annealing regimes. The unannealed samples exhibit a stronger than linear dependence of JB on WB, which can be attributed to electric field assisted thermal generation, or to a profile in the generation lifetime [20]. The annealed samples, however, show a clear linear dependence allowing therefore the determination of both the diffusion current and the generation rate. As the annealing time increases from 5 to 10 min the diffusion current decreases marginally and then shows a pronounced increase for 20 and 30 min annealing. The bulk diffusion current is given by [21]:
J BDiff ¼
qn2i
sffiffiffiffiffiffi "sffiffiffiffiffiffiffiffi # Dn 1 Dp 1 þ sn N A sp N D
ð7Þ
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Fig. 6. Bulk (a) and periphery (b) reverse current components of all measured samples.
Fig. 5. Comparison between bulk, periphery and total capacitance of sample annealed at 350 °C/5 min. (a) Set A. (b) Set B. (c) Set C.
where Dn is the electron diffusion constant and sn the electron recombination lifetime in the p-side of the junction. Dp is the hole diffusion constant and sp the hole recombination lifetime in the n-side of the junction. Eq. (5) shows that the diffusion current is determined by the doping density in both sides of the junction and the corresponding recombination lifetimes. Since the diode is herein asymmetric (p+/n) the first term is usually neglected and the diffusion current is mainly determined by the low-doped region. The diffusion current is regarded as a fundamental lower limit of the reverse current at room temperature and, in a first approximation, is independent of the reverse bias [17]. Therefore, the marginal decrease of the diffusion current after 10 min annealing can be attributed to the beneficial effects of annealing which reduces the process induced damage thus increasing the recombination lifetimes and the doping density in both sides of the junction. Moreover, the pronounced increase of the diffusion current at longer annealing times indicates a deterioration of the diode, due to an effective increase of the active recombination–generation centers within the germanium band-gap. Fig. 9 indicates that the generation current in the annealed samples constitutes a significant portion of the total reverse current, which at 2 V reaches almost 50%. The generation lifetime of the diodes can be calculated by [17]:
sg ¼
q ni dJB dW B
ð8Þ
Fig. 7. Bulk (a) and periphery (b) capacitance components of all measured samples.
In addition, the recombination lifetime can also be evaluated under the assumption of a realistic diffusion length (Dp) according to [17]:
sr
q2 n4i J 2BDiff
N2D
Dp
ð9Þ
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Fig. 8. Apparent carrier density profile of all measured samples extracted using the bulk capacitance component.
Fig. 9. Plot of bulk current density as a function of the depletion width.
Eq. (7) derives from (5) after omitting the terms of the heavily doped boron side. Therefore the calculated recombination lifetime corresponds to the recombination of holes within the low-doped nside. A Dp value of 50 cm2/s was used which corresponds to a hole mobility of 2000 cm2/V s [25]. Fig. 10 compares the diffusion current with the corresponding generation and recombination lifetimes. The graphs indicate that all these parameters follow the same trend. As the diffusion current takes the lowest value for the 10 min annealing regime, sg and sr acquire their highest values while for longer annealing times both lifetimes decrease. Finally from sg and sr it is possible to estimate the quantity |Et Ei| which gives the position of the effective generation recombination level, Et, with respect to the intrinsic Fermi level, Ei, in accordance with [18]:
sg jEt Ei j ffi exp kT sr
ð10Þ
As it has been noticed in the case where multiple trap levels coexist within a diode, Et represents an effective trap level which is the weighted influence of all these energy levels [21]. Fig. 10c shows the behavior of the effective energy level with the annealing time. As the annealing time increases, Et has a tendency to shift by 0.007 eV from the mid-gap. The above results are also consistent with the diodes ideality factor where the lowest value (1.31) was obtained for the case of the 350 °C/10 min annealing sample. Table 2 summarizes all the key results of the present study. The peripheral capacitance characteristics indicate a rather constant response to the reverse bias. Taking also into account the fact that no particular measures were taken to passivate the
Fig. 10. Bulk diffusion current (a), generation lifetime, and recombination lifetime (b) and (c) effective trap energy level shift with annealing time of all annealed samples.
Table 2 Bulk diffusion current, generation and recombination lifetimes, effective trap level distance from midgap, and ideality factor of all diodes examined in this study. Sample
Annealing at 350 °C
JB (A/cm2)
sg (ls)
sr (ls)
|Et Ei| (eV)
n
P2 P3 P4 P5
5 min 10 min 20 min 30 min
7.58 104 6.96 104 8.95 104 1.2 103
1.76 1.945 1.249 0.9
2.22 2.64 1.6 0.9
0.018 0.016 0.017 0.024
1.35 1.31 1.36 1.41
surface region at the edges of the diodes, the constant capacitance suggests a rather constant lateral depletion width due to Fermi level pinning at the exposed surface states. Such a condition provides an interpretation of the relatively high peripheral current component. 3.3. Temperature dependent measurements Fig. 11 shows the reverse diode current Arrhenius plots of the unannealed sample and samples annealed at 350 °C for 10 and 30 min, all recorded from the A set diodes at reverse bias of 1 V. In the case of the unannealed sample the Arrhenius plot of the reverse current shows two distinct linear regions. The first, from 170 K to 270 K, corresponds to an activation energy of EA2 = 0.38 eV which indicates that the reverse current is due to a trap assisted generation mechanism. Above 270 K the activation energy is EA1 = 0.68 eV, which suggests a diffusion current via a
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Fig. 11. Arrhenius plots of the reverse current recorded from set A diodes at a reverse bias of 1 V. (a) Unannealed, (b) 350 °C/10 min and (c) 350 °C/30 min samples.
band-to-band mechanism. For the sample annealed for 10 min the transition between the two mechanisms occurs at 250 K, denoting the suppression of the midgap-state generation mechanism. While the value of EA2 remains the same, EA1 decreases to 0.53 eV. This change in EA1 value from the Ge band-gap energy may indicate the involvement of shallow hole-traps in the band-gap which determine the high-temperature mechanism of electron–hole generation, i.e. the value of EA1. Finally, the reverse current in the case of the 30 min annealing sample shows a single activation energy of 0.43 eV up to 290 K. This new energy level may be attributed to the interaction of the initial midgap state with the shallow states induced by the annealing process. Therefore the dominant contribution of the reverse current at room temperature for the case of the 30 min annealed sample arises from defect states with an effective activation energy of 0.43 eV. In addition, at room temperature the reverse current of the unannealed and the 350 °C/10 min annealed samples is actually controlled from diffusion while for the 350 °C/ 30 min annealed sample it is still controlled from deep centers. Additional information was provided from deep level transient spectroscopy measurements (DLTS) performed on diodes from the same split, which revealed the presence of several deep levels at the limits of the system detection [26]. Upon annealing for 30 min at 350 °C the DLTS height of these levels was found to decrease slightly, while a pronounced hole trap was recorded. This behavior is consistent with the previously mentioned activation energies and indicates that these defects must not be related to Pt in diffusion but possibly associated with the evolution and clustering of ion-implantation and/or sputtering related defects. The creation of such defects is probably the reason for the higher reverse current observed for annealing times longer than 10 min. Although Sockley–Read–Hall theory anticipates that the most efficient recombination centers should lie close to the midgap of a semiconductor the increased density of defects with an effective activation energy of 0.43 eV may explain the deterioration of the diode characteristics at longer annealing times. Recombination lifetimes in Ge substrates has been thoroughly studied using optical excitation methods [27,28]. These studies showed that the recombination lifetime is strongly substrate doping dependent. For the case of a n-type Ge substrate with a doping density within the range of 1 1015 cm3 the estimated recombination lifetime is about 20 ls. Previous studies performed on Ge diodes during the 1950’s reported lifetime values around 1– 100 ls [29]. It is therefore evident that the values extracted in this study (1–2 ls) are quite reasonable and expected, considering that defect states are present due to the sputtering and ion-implantation processes. In addition, comparison with silicon lifetimes in Czochralski type substrates also show that either recombination or generation lifetimes within the ls range are also typical [17].
4. Conclusions In this work we studied the influence of the annealing time at 350 °C to the reverse characteristics of p+/n junctions fabricated by platinum assisted dopant activation. At first the diode current and capacitance characteristics in the reverse bias regime were separated into bulk and peripheral components. This analysis indicated that in all examined geometries both components have comparable magnitudes. Further analysis of the bulk diode characteristics revealed that the generation current component has a significant contribution to the overall reverse current. The generation and recombination lifetimes were found within the range of the microsecond regime with the highest values after an annealing time of 10 min which for the 350 °C regime constitutes a compromise between two opposite trends, the annealing of process related defects and the creation of defect centers within the diode active region. It should be finally mentioned that the low process temperature of the diode formation assisted by metals such as Co or Pt may constitute a promising approach for Ge transistor fabrication towards the realization of 3-D integrated circuits [30]. References [1] Kamata Y. Mater Today 2008;11:30. [2] Heyns M, Tsai W. MRS Bull 2009;34:485. [3] Saraswat K, Chui CO, Krishnamohan T, Kim D, Nayfeh A, Pethe A. Mater Sci Eng B 2005;135:242. [4] Claeys C, Mitard J, Eneman G, Meuris M, Simoen E. Thin Solid Films 2010;518:2301. [5] Toriumi A, Tabata T, Lee CH, Nishimura T, Kita K, Nagashio K. Microelectron Eng 2009;86:1571. [6] Chui CC, Kulig L, Moran J, Tsai W, Saraswat KC. Appl Phys Lett 2005;87:091909. [7] Satta A, Janssens T, Clarysse T, Simoen E, Meuris M, Benedetti A, et al. J Vac Sci Technol B 2006;24:494. [8] Ioannou N, Skarlatos D, Tsamis C, Krontiras CA, Georga SN, Christofi A, et al. Appl Phys Lett 2008;93:101910. [9] Simoen E et al. Mater Sci Semicond Proc 2006;9:634. [10] Tsouroutas P, Tsoukalas D, Zergioti I, Cherkaskin N, Claverie A. J Appl Phys 2009;105:094910. [11] Satta A, D’Amore A, Simoen E, Anward W, Skorupa W, Clarysse T, et al. Nucl Instr Method B 2007;257:157. [12] Wundisch C, Posselt M, Schmidt B, Heera V, Schumann T, Mucklich A, et al. Appl Phys Lett 2009;95:252107. [13] Kim J, Bedell SW, Maurer SL, Loesing R, Sadana DK. Electrochem Solid-State Lett 2010;13:H12. [14] Jamil M, Mantey J, Onyegam EU, Carpenter GD, Tutuc E, Banerjee SK. IEEE Electron Device Lett 2011;32:1203. [15] Ioannou-Sougleridis V, Galata SF, Golias E, Speliotis T, Dimoulas A, Giubertoni D, et al. Microelectron Eng 2012;88:254. [16] Duffy R, Shayesteh M. ECS Trans 2012;45:189. [17] Murakami Y, Shingyouji T. J Appl Phys 1994;75:3548. [18] Simoen E, Claeys C, Czerwinski A, Katcki J. Appl Phys Lett 1988;72:1054. [19] Poyai A, Simoen E, Clayes C, Rooyackers R, Badenes G. J Electrochem Soc 2001;148:G507.
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