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Selective alignment of a ZnO nanowire in a magnetic field for the fabrication of an air-gap field-effect transistor
Microelectronic Engineering 87 (2010) 10–14
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Selective alignment of a ZnO nanowire in a magnetic field for the fabrication of an air-gap field-effect transistor Sang-Won Lee a, Moon-Ho Ham a,1, Jyoti Prakash Kar a, Woong Lee b, Jae-Min Myoung a,* a
Information and Electronic Materials Research Laboratory, Department of Materials Science and Engineering, Yonsei University, 134 Shinchon-dong, Seodaemun-gu, Seoul 120-749, Republic of Korea b School of Nano and Advanced Materials Engineering, Changwon National University, 9 Sarim-dong, Changwon, Gyoungnam 641-773, Republic of Korea
a r t i c l e
i n f o
Article history: Received 4 October 2008 Received in revised form 7 April 2009 Accepted 8 May 2009 Available online 18 May 2009 PACS: 81.07.b 73.63.Nm 85.35.p 85.30.Tv
a b s t r a c t An air-gap field-effect transistor (FET) was prepared by selectively aligning a Ni-capped ZnO nanowire in a magnetic field on a pre-fabricated electrode patterns formed by lithography. It was demonstrated that the magnetic alignment technique could be applied effectively to the fabrication of air-gap nanowire FETs with desired circuit configurations. This device showed operational characteristic strongly dependent on the possible surface adsorbates originating from the negatively charged oxygen related species, as compared to the back-gate nanowire FET separately prepared for comparison. These results will illuminate the prospect of realizing producible matrix-type devices based on one-dimensional nanostructures such as logic circuits and biochemical sensors. Ó 2009 Elsevier B.V. All rights reserved.
Keywords: ZnO nanowire Field-effect transistor Air-gap structure Magnetic alignment
1. Introduction One-dimensional (1D) nanostructures such as nanowires, nanocables, nanotubes, etc. are regarded as promising candidates for the building blocks of various micro/nano-electronic, photonic, and spintronic devices due to their unique properties originating from the reduced dimensionality as well as their small diameters [1–5]. Early works on the 1D nano-devices were focused on the fabrication techniques for the realization of functioning device structures such as light-emitting diodes (LEDs), sensors, and fieldeffect transistors (FETs) [6–10]. It was demonstrated that 1D nanostructures including carbon nanotubes (CNTs) and nanowires of Si, ZnO, GaN, etc. could be integrated into the device structures having sufficient performances. Despite of these promising results, their application to the integrated circuit has been hindered due to the difficulties involved in manipulating individual 1D nanostructures precisely to form reproducible matrix-type device patterns.
* Corresponding author. Tel.: +82 2 2123 2843; fax: +82 2 365 2680. E-mail address: [email protected] (J.-M. Myoung). 1 Present address: Department of Chemical Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139, USA. 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.05.008
In order to overcome this difficulty, micro-fluidic alignment [11,12], electric field alignment [13,14], and magnetic field alignment [13,15,16] techniques were developed. Among these techniques, the magnetic alignment technique previously demonstrated a possibility of placing a single nanowire on a desired location in a patterned substrate [9] with relative ease and simplicity as compared to other alignment techniques. However, the model device structure presented in the previous work is a simple bridge-like pattern in which ZnO nanowires connected two long electrode strips. Therefore, on the extension of the previous work, to demonstrate a feasibility of producing practical device structures, an air-gap nanowire FET has been prepared using the magnetic alignment technique in this study. In the air-gap FET structure, air plays the role of the gate insulator due to its infinite bandgap energy to minimize the gate leakage current, a technical difficulty accompanying the scaling-down the FETs in integrated circuits [17]. In addition, suspended nanowire channels in the air-gap devices can provide higher surface area for sensor applications as compared to other device configurations. Since the difficulty of positioning individual nanowires in the desired locations within the patterned device structure has been the major obstacle to exploit the advantages of the suspended channel configuration, the air-gap structure was chosen
S.-W. Lee et al. / Microelectronic Engineering 87 (2010) 10–14
to demonstrate the usefulness of the magnetic alignment technique. As the nanowire channel material, ZnO was chosen since it has strong application potential in various types of devices including LEDs, FETs, sensors [1,18–20], etc. exploiting their wide bandgap of 3.37 eV and high exciton binding energy of 60 meV as well as their electrical properties dependent on the surface states. It was possible to control selectively the position of the nanowire on the pre-fabricated electrode pattern with precision and simplicity, illuminating the applicability of this technique to the matrix-type integrated nanowire device. Advantages of the airgap FET structure have been addressed by comparing the operation of this device to a typical back-gate nanowire FET with regard to the roles of surface species in the operation of the FETs based on ZnO nanowires.
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subsequently deposited on both ends of the aligned nanowire by DC magnetron sputtering to give the final air-gap FET structure. For comparison, back-gate nanowire FET was also prepared on degenerately doped p-type Si substrate capped with a thermally grown 300 nm-thick SiO2 layer. In this control device, p-type Si substrate functions as a global gate. Operation of these devices was evaluated by measuring current–voltage (I–V) characteristics using a semiconductor parameter analyzer (HP4145B). 3. Results and discussion The effectiveness and advantage of the magnetic alignment technique for nanowire-based device processing was first verified by preparing an air-gap FET with a single ZnO nanowire. Fig. 2a is the
2. Experimental As channel materials, ZnO nanowires were synthesized on a cplane Al2O3 substrate by metalorganic chemical vapor deposition (MOCVD) [21]. Thereafter, the nanowires were capped by a thin Ni layer using sputter deposition. The nanowires had the typical diameter of 150 nm and length of 8 lm. Magnetic alignment, detailed elsewhere [9], was subsequently applied to prepare the air-gap FET in the following manner. First, basic device pattern, schematically shown in Fig. 1a with the dimensions, was fabricated by e-beam lithography on the sputtered metal layers on a 300 nmthick SiO2/p-Si substrate. In this pattern, Ni pad plays the role of attracting the Ni-capped ZnO nanowire in a magnetic field during the alignment process. On this basic device structure, Ni-capped ZnO nanowire was dispersed by applying a suspension prepared by immersing nanowires in isopropyl alcohol via sonication for 30 min which was sufficient to suspend individually nanowires, in a magnetic field of 1.6 T as schematically illustrated in Fig. 1b. As demonstrated in the previous work [9], the number of the dispersed nanowires was systematically controlled by changing the size (width) of the Ni patterns. Based on the work, a specific size (width) of the Ni patterns could be employed to put only one nanowire as a channel on the electrodes. Ti/Au upper electrodes were
Fig. 1. (a) Schematic drawing of the pre-fabricated device electrode structure for the air-gap FET and (b) schematic illustration of the alignment of a single Ni-capped ZnO nanowire on the electrode in a magnetic field (inset) and the resulting air-gap nanowire FET structure.
Fig. 2. (a) 80°-Tilt view of the SEM images of the air-gap gate structure formed by the magnetic alignment technique. (b) Air-gap FET structure with 65 nm-gap air dielectric layer and (c) back-gate nanowire FET structure with 300 nm-think SiO2 dielectric layer for the control experiment.
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S.-W. Lee et al. / Microelectronic Engineering 87 (2010) 10–14
80°-tilt view SEM micrographs showing the overall shape of the airgap FET. It can be seen that the ZnO nanowire is placed between the source and drain electrodes over the gate electrode indicating that the nanowire was selectively positioned on the desired location of the pre-fabricated device pattern. Also seen in Fig. 2a is the shade on the surface region between the source and drain electrodes, especially on the gate electrode surface. This is a clear indication that there exists a gap below the nanowire that was formed simply by the height difference between the bottom gate electrode and the source/drain electrodes. Once the nanowire channel is assembled to the electrode pattern, the device structure can be completed through typical lithography process to add other components or electrical wiring as shown in Fig. 2b. Therefore, it is confirmed that the suspended device structure of ZnO nanowire/air-gap/Pt can be produced without any complicated process through the application of a magnetic field to the suitably designed device pattern, which subsequently results in the controlled alignment and positioning of a single nanowire over the desired location. Noting that typical techniques to prepare nanowire-based devices, in which mapping of the nanowires by time-consuming imaging process after the dispersion is required, has practically no reproducibility of the same device patterns in the forms of integrated circuits due to the randomness of nanowire distributions on dispersion, it is proposed that the magnetic alignment technique employed herein can be a potentially useful method to realize the ‘reproducible’ patterned integrated circuit based on 1D nanostructures by relieving the randomness of the nanowire distribution. The magnetic metal electrode patterns are successively fabricated at the desired positions on a substrate, and the nanowires are subsequently dispersed under a magnetic field, resulting in the self-alignment of the nanowires with respect to the electrodes. Based on this controlled positioning technique, the fabrication of high-density nanowire device array could be feasible. Further, when compared with the electric field method, it is believed that the magnetic method herein has some advantage in that the alignment is dependent not on the dielectric property of the nanowire itself but on the magnetic property of the small metallic tip at the growing end of the wire since the wire is aligned in the magnetic field due to the attraction of that metallic tip region to the electrode. Therefore, once the nanowires are grown through VLS mechanism employing magnetic catalysts, any semiconductor nanowire could be aligned individually on the device pattern. The advantage of the process employed in this study is illustrated in Table 1 in which the process herein and typical process are compared. In Fig. 2c, the back-gate nanowire FET for the control experiment is shown. Following the demonstration of the practical advantage of the magnetic alignment technique for the preparation of potentially reproducible patterned integrated devices with ZnO nanowires, the application potential of the air-gap ZnO nanowire FET was explored by measuring their operational characteristics. Fig. 3a shows the output characteristic of the air-gap ZnO nanowire FET in terms of the drain current vs. drain voltage (Ids–Vds) curves, obtained as functions of gate voltage (Vg). In Fig. 3a, while the drain current is very low when Vg = 0, application of the negative gate voltage down to 20 V results in the almost unnoticeable change in drain current. On the other hand, when the positive gate voltage is applied, it increases substantially. These output characteristics indicate that the ZnO nanowire channel is n-type and that the
Fig. 3. (a) Output curves and (b) transfer curve of the ZnO nanowire FET based on the air-gap gate dielectric structure.
FET operates in the enhancement mode. Fig. 3b shows the transfer characteristic of the air-gap FET at Vds = 0.4 V. From Fig. 3b, threshold voltage (Vth), on/off current ratio, sub-threshold slope, and the transconductance are estimated to be about 13 V, 40, 3 V/decade, and 3.7 nS, respectively. The carrier concentration, n, of the ZnO nanowire channel can be calculated using [22]
n¼
CV th epr2 L
ð1Þ
where r, C, and L are the wire radius, capacitance, and the channel length, respectively. C is given by C = 2pee0L/ln(2h/r), where h is a thickness of dielectric layer. Taking r = 75 nm, L = 3 lm, and h = 65 nm which is determined by subtracting the thickness of the bottom metal gate from the thickness of the bottom electrodes gives the carrier concentration of 4.65 1017 cm3. The field-effect mobility, le, can be estimated using [22]
l¼
dIds L2 dV g CV ds
ð2Þ
Taking the transconductance (dIds/dVg) of 3.7 nS for the air-gap FET gives the field-effect mobility of about 3 cm2 V1 s1.
Table 1 Comparison of the processes for the fabrication of two different types of nanowire FETs. Device structure
Dispersion method
Lithography process
Imaging
Mapping
Ni pattern
Array structure for matrix device
Typical device This study
Random dispersion Magnetic alignment
e-Beam lithography Photo or e-beam lithography
O X
O X
X O
X O
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Fig. 4. (a) Output curves and (b) transfer curve of the back-gate ZnO nanowire FET.
For further discussion on the characteristics of the air-gap FET described above, the output and transfer characteristics of the back-gate ZnO nanowire FET, separately prepared for control experiments (Fig. 2c), were measured and the results are shown in Fig. 4a and b. In the output characteristics shown in Fig. 4a, it is seen that the FET has a substantial off-state current. Thus, the device will be ‘turned off’ when the gate voltage is negative whereas the positive gate voltages increase the drain current for a given drain voltage. Such Ids–Vds behavior is similar to what has been reported previously reported for ZnO nanowire-based back-gate FETs [4] while it indicates that this nanowire FET is an n-channel device. From the transfer characteristic shown in Fig. 4b, the threshold voltage, on/off current ratio, sub-threshold slope, and transconductance are estimated to be 13 V, 10, 26 V/decade, and 140.4 nS, respectively. Using these values and Eqs. (1) and (2), the carrier concentration and field-effect mobility are estimated to be 4.80 1017 cm3 and 13 cm2 V1 s1, respectively. When the device characteristics shown in Figs. 3 and 4 are compared, marked differences in the device operations are noticed even though both the air-gap FET and the back-gate FET are based on the same ZnO nanowires. First, there is a significant difference in the threshold voltages between the two devices: the air-gap FET has a positive Vth while the back-gate FET has a negative Vth. For an n-channel device, it is typical to have negative threshold voltages and the positive contributions to the threshold voltage come from negative depletion charge at strong inversion and negative charge at the interface between the channel and the gate dielectrics [23]. In case of ZnO, it is generally accepted that the
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electrical conduction is dependent on the negatively charged species adsorbed on the surfaces and this effect becomes more salient for the low-dimensional structures such as nanowires [4,24,25]. In the air-gap FET structure, ZnO nanowire channel is exposed to the air around the whole surface whereas the nanowire channel is partially in contact with the SiO2 dielectric layer in the back-gate FET structure. This means that the effective ‘interface charge’ contribution to the threshold voltage in the air-gap FET could be positive if the ZnO nanowire channel adsorbs negatively charged surface adsorbates. To the contrary, in the back-gate FET structure, there can be positive trap charge in the SiO2 layer yielding negative contribution to the threshold voltage. Significance of the surface charge can also be seen in the output characteristics shown in Figs. 3a and 4a. The air-gap device is ‘‘normally off” type and the back-gate device is ‘‘normally on” type. In the air ambient, if the diameter of ZnO nanowire is substantially small, it is possible that the formation of the depletion region in the ZnO nanowire due to the surface species is sufficient to block the conduction path along the nanowire. However, in the back-gate device, the nanowire is in contact with SiO2 layer which contains positive trap charges that can prevent the expansion of the depletion region in the ZnO nanowire. Such trap charges could be generated by the sputtering of Ni capping on the nanowires since the Ni atoms could adsorb on the nanowire surface and nanowire tip could be damaged during sputtering, resulting in the degradation of the device performance compared with the air-gap device. Then, it is possible that the off-state conduction is partially maintained in the nanowire channel. Thus, at Vg = 0 V, the drain current is almost 0 in the air-gap device whereas that in the back-gate device has non-zero value. In addition to such differences in the on/off output characteristics between two devices due to the different charge loss ability to the substrate, the configurational differences results in the different channel conductances attributable to the surface adsorbates effect. The mobility of the air-gap FET was estimated to be about 3 cm2 V1 s1 whereas that of the back-gate FET to be 13 cm2 V1 s1. Since the carrier concentrations are almost the same (4.65 1017 cm3 vs. 4.80 1017 cm3), it is expected that the source–drain conductance of the back-gate FET would be higher than that of the air-gap FET. The differences in the carrier mobility are again attributed to the scattering effect due to the presence of the negatively charged surface adsorbates on the air-gap device. The results and deductions regarding the operational characteristics of the air-gap FET and the back-gate FET so far have some practical implications in the application of the ZnO nanowire FET to sensors. For sensor applications, it should be guaranteed that the device functions reproducibly with given amount of chemical or biological species on the sensing channel. In this respect, airgap device will have an advantage that some uncertainty related to the contact with SiO2 layer in the back-gate configuration, which seems to have noticeable effect on the device operation, can be eliminated. Further, in case of the air-gap configuration, when any chemical species is adsorbed on the nanowire channel surface, it will change the capacitance of the air ‘‘dielectric” layer resulting in the changes in the on/off behavior and threshold voltages, as demonstrated above, which will have another significance in the sensor application of the air-gap FET structures.
4. Conclusion A novel fabrication process based on the magnetic alignment method has been adopted to prepare a device structure applicable to the matrix-type integrated electronic devices based on ZnO nanowires and suspension channels over air-gap gates configuration. It was possible to arrange a single ZnO nanowire selectively on a pre-fabricated device pattern by the magnetic alignment
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method to form the air-gap FET structure. Although this air-gap FET showed relatively poorer performance over typical back-gate nanowire FETs, its operational characteristics were strongly dependent on the possible surface states and the changes in the capacitance of the air ‘‘dielectric” layer originating from the adsorbed oxygen related species, which was not observed on the back-gate nanowire FET separately prepared for comparison purpose. Such operational characteristics shed light on the potential applicability of this aligned air-gap FET structure to the various biochemical sensors. Acknowledgements This work was supported by the Korea Science and Engineering Foundation (KOSEF) Grant funded by the Korea Government (MOST) (No. R01-2007-000-20143-0) and by the academic-industrial cooperation program funded by LG Display. References [1] M.H. Huang, S. Mao, H. Feick, H. Yan, Y. Wu, H. Kind, E. Weber, R. Russo, P. Yang, Science 292 (2001) 1897. [2] X.D. Bai, P.X. Gao, Z.L. Wang, E.G. Wang, Appl. Phys. Lett. 82 (2003) 4806. [3] Y.K. Tseng, C.J. Huang, H.M. Cheng, I.N. Lin, K.S. Liu, I.C. Chen, Adv. Funct. Mater. 13 (2003) 811.
[4] Z. Fan, D. Wang, P.C. Chang, W.Y. Tseng, J.G. Lu, Appl. Phys. Lett. 85 (2004) 5923. [5] M.H. Ham, J.M. Myoung, Appl. Phys. Lett. 89 (2006) 173117. [6] H. Kind, H. Yan, B. Messer, M. Law, P. Yang, Adv. Mater. 14 (2002) 158. [7] T.H. Moon, M.C. Jeong, B.Y. Oh, M.H. Ham, M.H. Jeun, W.Y. Lee, J.M. Myoung, Nanotechnology 17 (2006) 2116. [8] Y. Cui, Q. Wei, H. Park, C.M. Lieber, Science 293 (2001) 1289. [9] S.W. Lee, M.C. Jeong, J.M. Myoung, G.S. Chae, I.J. Chung, Appl. Phys. Lett. 90 (2007) 133115. [10] M.H. Ham, D.K. Oh, J.M. Myoung, J. Phys. Chem. C 111 (2007) 11480. [11] Y. Huang, X. Duan, Q. Wei, Y. Cui, L.J. Lauhon, K.H. Kim, C.M. Lieber, Science 294 (2001) 1313. [12] Y. Huang, X. Duan, Q. Wei, C.M. Lieber, Science 291 (2001) 630. [13] X. Duan, Y. Huang, Y. Cui, J. Wang, C.M. Lieber, Nature 409 (2001) 66. [14] P.A. Smith, C.D. Nordquist, T.N. Jackson, T.S. Mayer, Appl. Phys. Lett. 77 (2000) 1399. [15] A.K. Bentley, J.S. Trethewey, A.B. Ellis, W.C. Crone, Nano Lett. 4 (2004) 487. [16] S.W. Jung, W.I. Park, G.C. Yi, M.Y. Kim, Adv. Mater. 15 (2003) 1358. [17] S.N. Cha, J.E. Jang, Y. Choi, G.W. Ho, M.E. Welland, D.G. Hasko, D.J. Kang, J.M. Kim, G.A.J. Amaratunga, Appl. Phys. Lett. 89 (2006) 263102. [18] M.C. Jeong, B.Y. Oh, M.H. Ham, S.W. Lee, J.M. Myoung, Small 3 (2007) 568. [19] J. Zang, C.M. Li, X. Cui, J. Wang, X. Sun, H. Dong, C.Q. Sun, Electroanalysis 19 (2007) 1008. [20] Z. Fan, J.G. Lu, Appl. Phys. Lett. 86 (2005) 123510. [21] M.C. Jeong, B.Y. Oh, W. Lee, J.M. Myoung, J. Cryst. Growth 268 (2004) 149. [22] M.H. Ham, J.H. Choi, W. Hwang, C. Park, W.Y. Lee, J.M. Myoung, Nanotechnology 17 (2006) 2203. [23] B.G. Streetman, S. Banerjee, Solid State Electronic Device, Prentice Hall, Upper Saddle River, 2000. [24] H.Z. Zhang, R.M. Wang, Y.W. Zhu, J. Appl. Phys. 96 (2004) 624. [25] M.C. Jeong, B.Y. Oh, W. Lee, J.M. Myoung, Appl. Phys. Lett. 86 (2005) 103105.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Selective alignment of a ZnO nanowire in a magnetic field for the fabrication of an air-gap field-effect transistor Sang-Won Lee a, Moon-Ho Ham a,1, Jyoti Prakash Kar a, Woong Lee b, Jae-Min Myoung a,* a
Information and Electronic Materials Research Laboratory, Department of Materials Science and Engineering, Yonsei University, 134 Shinchon-dong, Seodaemun-gu, Seoul 120-749, Republic of Korea b School of Nano and Advanced Materials Engineering, Changwon National University, 9 Sarim-dong, Changwon, Gyoungnam 641-773, Republic of Korea
a r t i c l e
i n f o
Article history: Received 4 October 2008 Received in revised form 7 April 2009 Accepted 8 May 2009 Available online 18 May 2009 PACS: 81.07.b 73.63.Nm 85.35.p 85.30.Tv
a b s t r a c t An air-gap field-effect transistor (FET) was prepared by selectively aligning a Ni-capped ZnO nanowire in a magnetic field on a pre-fabricated electrode patterns formed by lithography. It was demonstrated that the magnetic alignment technique could be applied effectively to the fabrication of air-gap nanowire FETs with desired circuit configurations. This device showed operational characteristic strongly dependent on the possible surface adsorbates originating from the negatively charged oxygen related species, as compared to the back-gate nanowire FET separately prepared for comparison. These results will illuminate the prospect of realizing producible matrix-type devices based on one-dimensional nanostructures such as logic circuits and biochemical sensors. Ó 2009 Elsevier B.V. All rights reserved.
Keywords: ZnO nanowire Field-effect transistor Air-gap structure Magnetic alignment
1. Introduction One-dimensional (1D) nanostructures such as nanowires, nanocables, nanotubes, etc. are regarded as promising candidates for the building blocks of various micro/nano-electronic, photonic, and spintronic devices due to their unique properties originating from the reduced dimensionality as well as their small diameters [1–5]. Early works on the 1D nano-devices were focused on the fabrication techniques for the realization of functioning device structures such as light-emitting diodes (LEDs), sensors, and fieldeffect transistors (FETs) [6–10]. It was demonstrated that 1D nanostructures including carbon nanotubes (CNTs) and nanowires of Si, ZnO, GaN, etc. could be integrated into the device structures having sufficient performances. Despite of these promising results, their application to the integrated circuit has been hindered due to the difficulties involved in manipulating individual 1D nanostructures precisely to form reproducible matrix-type device patterns.
* Corresponding author. Tel.: +82 2 2123 2843; fax: +82 2 365 2680. E-mail address: [email protected] (J.-M. Myoung). 1 Present address: Department of Chemical Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139, USA. 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.05.008
In order to overcome this difficulty, micro-fluidic alignment [11,12], electric field alignment [13,14], and magnetic field alignment [13,15,16] techniques were developed. Among these techniques, the magnetic alignment technique previously demonstrated a possibility of placing a single nanowire on a desired location in a patterned substrate [9] with relative ease and simplicity as compared to other alignment techniques. However, the model device structure presented in the previous work is a simple bridge-like pattern in which ZnO nanowires connected two long electrode strips. Therefore, on the extension of the previous work, to demonstrate a feasibility of producing practical device structures, an air-gap nanowire FET has been prepared using the magnetic alignment technique in this study. In the air-gap FET structure, air plays the role of the gate insulator due to its infinite bandgap energy to minimize the gate leakage current, a technical difficulty accompanying the scaling-down the FETs in integrated circuits [17]. In addition, suspended nanowire channels in the air-gap devices can provide higher surface area for sensor applications as compared to other device configurations. Since the difficulty of positioning individual nanowires in the desired locations within the patterned device structure has been the major obstacle to exploit the advantages of the suspended channel configuration, the air-gap structure was chosen
S.-W. Lee et al. / Microelectronic Engineering 87 (2010) 10–14
to demonstrate the usefulness of the magnetic alignment technique. As the nanowire channel material, ZnO was chosen since it has strong application potential in various types of devices including LEDs, FETs, sensors [1,18–20], etc. exploiting their wide bandgap of 3.37 eV and high exciton binding energy of 60 meV as well as their electrical properties dependent on the surface states. It was possible to control selectively the position of the nanowire on the pre-fabricated electrode pattern with precision and simplicity, illuminating the applicability of this technique to the matrix-type integrated nanowire device. Advantages of the airgap FET structure have been addressed by comparing the operation of this device to a typical back-gate nanowire FET with regard to the roles of surface species in the operation of the FETs based on ZnO nanowires.
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subsequently deposited on both ends of the aligned nanowire by DC magnetron sputtering to give the final air-gap FET structure. For comparison, back-gate nanowire FET was also prepared on degenerately doped p-type Si substrate capped with a thermally grown 300 nm-thick SiO2 layer. In this control device, p-type Si substrate functions as a global gate. Operation of these devices was evaluated by measuring current–voltage (I–V) characteristics using a semiconductor parameter analyzer (HP4145B). 3. Results and discussion The effectiveness and advantage of the magnetic alignment technique for nanowire-based device processing was first verified by preparing an air-gap FET with a single ZnO nanowire. Fig. 2a is the
2. Experimental As channel materials, ZnO nanowires were synthesized on a cplane Al2O3 substrate by metalorganic chemical vapor deposition (MOCVD) [21]. Thereafter, the nanowires were capped by a thin Ni layer using sputter deposition. The nanowires had the typical diameter of 150 nm and length of 8 lm. Magnetic alignment, detailed elsewhere [9], was subsequently applied to prepare the air-gap FET in the following manner. First, basic device pattern, schematically shown in Fig. 1a with the dimensions, was fabricated by e-beam lithography on the sputtered metal layers on a 300 nmthick SiO2/p-Si substrate. In this pattern, Ni pad plays the role of attracting the Ni-capped ZnO nanowire in a magnetic field during the alignment process. On this basic device structure, Ni-capped ZnO nanowire was dispersed by applying a suspension prepared by immersing nanowires in isopropyl alcohol via sonication for 30 min which was sufficient to suspend individually nanowires, in a magnetic field of 1.6 T as schematically illustrated in Fig. 1b. As demonstrated in the previous work [9], the number of the dispersed nanowires was systematically controlled by changing the size (width) of the Ni patterns. Based on the work, a specific size (width) of the Ni patterns could be employed to put only one nanowire as a channel on the electrodes. Ti/Au upper electrodes were
Fig. 1. (a) Schematic drawing of the pre-fabricated device electrode structure for the air-gap FET and (b) schematic illustration of the alignment of a single Ni-capped ZnO nanowire on the electrode in a magnetic field (inset) and the resulting air-gap nanowire FET structure.
Fig. 2. (a) 80°-Tilt view of the SEM images of the air-gap gate structure formed by the magnetic alignment technique. (b) Air-gap FET structure with 65 nm-gap air dielectric layer and (c) back-gate nanowire FET structure with 300 nm-think SiO2 dielectric layer for the control experiment.
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S.-W. Lee et al. / Microelectronic Engineering 87 (2010) 10–14
80°-tilt view SEM micrographs showing the overall shape of the airgap FET. It can be seen that the ZnO nanowire is placed between the source and drain electrodes over the gate electrode indicating that the nanowire was selectively positioned on the desired location of the pre-fabricated device pattern. Also seen in Fig. 2a is the shade on the surface region between the source and drain electrodes, especially on the gate electrode surface. This is a clear indication that there exists a gap below the nanowire that was formed simply by the height difference between the bottom gate electrode and the source/drain electrodes. Once the nanowire channel is assembled to the electrode pattern, the device structure can be completed through typical lithography process to add other components or electrical wiring as shown in Fig. 2b. Therefore, it is confirmed that the suspended device structure of ZnO nanowire/air-gap/Pt can be produced without any complicated process through the application of a magnetic field to the suitably designed device pattern, which subsequently results in the controlled alignment and positioning of a single nanowire over the desired location. Noting that typical techniques to prepare nanowire-based devices, in which mapping of the nanowires by time-consuming imaging process after the dispersion is required, has practically no reproducibility of the same device patterns in the forms of integrated circuits due to the randomness of nanowire distributions on dispersion, it is proposed that the magnetic alignment technique employed herein can be a potentially useful method to realize the ‘reproducible’ patterned integrated circuit based on 1D nanostructures by relieving the randomness of the nanowire distribution. The magnetic metal electrode patterns are successively fabricated at the desired positions on a substrate, and the nanowires are subsequently dispersed under a magnetic field, resulting in the self-alignment of the nanowires with respect to the electrodes. Based on this controlled positioning technique, the fabrication of high-density nanowire device array could be feasible. Further, when compared with the electric field method, it is believed that the magnetic method herein has some advantage in that the alignment is dependent not on the dielectric property of the nanowire itself but on the magnetic property of the small metallic tip at the growing end of the wire since the wire is aligned in the magnetic field due to the attraction of that metallic tip region to the electrode. Therefore, once the nanowires are grown through VLS mechanism employing magnetic catalysts, any semiconductor nanowire could be aligned individually on the device pattern. The advantage of the process employed in this study is illustrated in Table 1 in which the process herein and typical process are compared. In Fig. 2c, the back-gate nanowire FET for the control experiment is shown. Following the demonstration of the practical advantage of the magnetic alignment technique for the preparation of potentially reproducible patterned integrated devices with ZnO nanowires, the application potential of the air-gap ZnO nanowire FET was explored by measuring their operational characteristics. Fig. 3a shows the output characteristic of the air-gap ZnO nanowire FET in terms of the drain current vs. drain voltage (Ids–Vds) curves, obtained as functions of gate voltage (Vg). In Fig. 3a, while the drain current is very low when Vg = 0, application of the negative gate voltage down to 20 V results in the almost unnoticeable change in drain current. On the other hand, when the positive gate voltage is applied, it increases substantially. These output characteristics indicate that the ZnO nanowire channel is n-type and that the
Fig. 3. (a) Output curves and (b) transfer curve of the ZnO nanowire FET based on the air-gap gate dielectric structure.
FET operates in the enhancement mode. Fig. 3b shows the transfer characteristic of the air-gap FET at Vds = 0.4 V. From Fig. 3b, threshold voltage (Vth), on/off current ratio, sub-threshold slope, and the transconductance are estimated to be about 13 V, 40, 3 V/decade, and 3.7 nS, respectively. The carrier concentration, n, of the ZnO nanowire channel can be calculated using [22]
n¼
CV th epr2 L
ð1Þ
where r, C, and L are the wire radius, capacitance, and the channel length, respectively. C is given by C = 2pee0L/ln(2h/r), where h is a thickness of dielectric layer. Taking r = 75 nm, L = 3 lm, and h = 65 nm which is determined by subtracting the thickness of the bottom metal gate from the thickness of the bottom electrodes gives the carrier concentration of 4.65 1017 cm3. The field-effect mobility, le, can be estimated using [22]
l¼
dIds L2 dV g CV ds
ð2Þ
Taking the transconductance (dIds/dVg) of 3.7 nS for the air-gap FET gives the field-effect mobility of about 3 cm2 V1 s1.
Table 1 Comparison of the processes for the fabrication of two different types of nanowire FETs. Device structure
Dispersion method
Lithography process
Imaging
Mapping
Ni pattern
Array structure for matrix device
Typical device This study
Random dispersion Magnetic alignment
e-Beam lithography Photo or e-beam lithography
O X
O X
X O
X O
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Fig. 4. (a) Output curves and (b) transfer curve of the back-gate ZnO nanowire FET.
For further discussion on the characteristics of the air-gap FET described above, the output and transfer characteristics of the back-gate ZnO nanowire FET, separately prepared for control experiments (Fig. 2c), were measured and the results are shown in Fig. 4a and b. In the output characteristics shown in Fig. 4a, it is seen that the FET has a substantial off-state current. Thus, the device will be ‘turned off’ when the gate voltage is negative whereas the positive gate voltages increase the drain current for a given drain voltage. Such Ids–Vds behavior is similar to what has been reported previously reported for ZnO nanowire-based back-gate FETs [4] while it indicates that this nanowire FET is an n-channel device. From the transfer characteristic shown in Fig. 4b, the threshold voltage, on/off current ratio, sub-threshold slope, and transconductance are estimated to be 13 V, 10, 26 V/decade, and 140.4 nS, respectively. Using these values and Eqs. (1) and (2), the carrier concentration and field-effect mobility are estimated to be 4.80 1017 cm3 and 13 cm2 V1 s1, respectively. When the device characteristics shown in Figs. 3 and 4 are compared, marked differences in the device operations are noticed even though both the air-gap FET and the back-gate FET are based on the same ZnO nanowires. First, there is a significant difference in the threshold voltages between the two devices: the air-gap FET has a positive Vth while the back-gate FET has a negative Vth. For an n-channel device, it is typical to have negative threshold voltages and the positive contributions to the threshold voltage come from negative depletion charge at strong inversion and negative charge at the interface between the channel and the gate dielectrics [23]. In case of ZnO, it is generally accepted that the
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electrical conduction is dependent on the negatively charged species adsorbed on the surfaces and this effect becomes more salient for the low-dimensional structures such as nanowires [4,24,25]. In the air-gap FET structure, ZnO nanowire channel is exposed to the air around the whole surface whereas the nanowire channel is partially in contact with the SiO2 dielectric layer in the back-gate FET structure. This means that the effective ‘interface charge’ contribution to the threshold voltage in the air-gap FET could be positive if the ZnO nanowire channel adsorbs negatively charged surface adsorbates. To the contrary, in the back-gate FET structure, there can be positive trap charge in the SiO2 layer yielding negative contribution to the threshold voltage. Significance of the surface charge can also be seen in the output characteristics shown in Figs. 3a and 4a. The air-gap device is ‘‘normally off” type and the back-gate device is ‘‘normally on” type. In the air ambient, if the diameter of ZnO nanowire is substantially small, it is possible that the formation of the depletion region in the ZnO nanowire due to the surface species is sufficient to block the conduction path along the nanowire. However, in the back-gate device, the nanowire is in contact with SiO2 layer which contains positive trap charges that can prevent the expansion of the depletion region in the ZnO nanowire. Such trap charges could be generated by the sputtering of Ni capping on the nanowires since the Ni atoms could adsorb on the nanowire surface and nanowire tip could be damaged during sputtering, resulting in the degradation of the device performance compared with the air-gap device. Then, it is possible that the off-state conduction is partially maintained in the nanowire channel. Thus, at Vg = 0 V, the drain current is almost 0 in the air-gap device whereas that in the back-gate device has non-zero value. In addition to such differences in the on/off output characteristics between two devices due to the different charge loss ability to the substrate, the configurational differences results in the different channel conductances attributable to the surface adsorbates effect. The mobility of the air-gap FET was estimated to be about 3 cm2 V1 s1 whereas that of the back-gate FET to be 13 cm2 V1 s1. Since the carrier concentrations are almost the same (4.65 1017 cm3 vs. 4.80 1017 cm3), it is expected that the source–drain conductance of the back-gate FET would be higher than that of the air-gap FET. The differences in the carrier mobility are again attributed to the scattering effect due to the presence of the negatively charged surface adsorbates on the air-gap device. The results and deductions regarding the operational characteristics of the air-gap FET and the back-gate FET so far have some practical implications in the application of the ZnO nanowire FET to sensors. For sensor applications, it should be guaranteed that the device functions reproducibly with given amount of chemical or biological species on the sensing channel. In this respect, airgap device will have an advantage that some uncertainty related to the contact with SiO2 layer in the back-gate configuration, which seems to have noticeable effect on the device operation, can be eliminated. Further, in case of the air-gap configuration, when any chemical species is adsorbed on the nanowire channel surface, it will change the capacitance of the air ‘‘dielectric” layer resulting in the changes in the on/off behavior and threshold voltages, as demonstrated above, which will have another significance in the sensor application of the air-gap FET structures.
4. Conclusion A novel fabrication process based on the magnetic alignment method has been adopted to prepare a device structure applicable to the matrix-type integrated electronic devices based on ZnO nanowires and suspension channels over air-gap gates configuration. It was possible to arrange a single ZnO nanowire selectively on a pre-fabricated device pattern by the magnetic alignment
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method to form the air-gap FET structure. Although this air-gap FET showed relatively poorer performance over typical back-gate nanowire FETs, its operational characteristics were strongly dependent on the possible surface states and the changes in the capacitance of the air ‘‘dielectric” layer originating from the adsorbed oxygen related species, which was not observed on the back-gate nanowire FET separately prepared for comparison purpose. Such operational characteristics shed light on the potential applicability of this aligned air-gap FET structure to the various biochemical sensors. Acknowledgements This work was supported by the Korea Science and Engineering Foundation (KOSEF) Grant funded by the Korea Government (MOST) (No. R01-2007-000-20143-0) and by the academic-industrial cooperation program funded by LG Display. References [1] M.H. Huang, S. Mao, H. Feick, H. Yan, Y. Wu, H. Kind, E. Weber, R. Russo, P. Yang, Science 292 (2001) 1897. [2] X.D. Bai, P.X. Gao, Z.L. Wang, E.G. Wang, Appl. Phys. Lett. 82 (2003) 4806. [3] Y.K. Tseng, C.J. Huang, H.M. Cheng, I.N. Lin, K.S. Liu, I.C. Chen, Adv. Funct. Mater. 13 (2003) 811.
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