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Self-aligned multi-level air gap integration
Microelectronic Engineering 83 (2006) 2150–2154 www.elsevier.com/locate/mee
Self-aligned multi-level air gap integration R.J.O.M. Hoofman a,*, R. Caluwaerts b, J. Michelon a, P. Herrero Bernabe´ c, J.P. Gueneau de Mussy b, C. Bruynseraede b, J.M. Lee d, S. List e, P.H.L. Bancken a, G. Beyer b a
c
Philips Research Leuven, Kapeldreef 75, B-3001 Leuven, Belgium b IMEC, Kapeldreef 75, B-3001 Leuven, Belgium University of Valladolid, Department of Electronics, Camino del Cementerio s/n , 47011 Valladolid, Spain d Samsung assignee at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium e Intel assignee at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium Available online 17 October 2006
Abstract Dual damascene self-aligned air gap structures have been fabricated through selective removal of interline plasma-damaged SiOC material using dilute HF solutions after metal CMP. The extent of the gaps was shown to be tuneable. The creation of interline air gaps through removal of damaged dielectric yielded significant capacitance reduction plus in addition dielectric reliability improvement. The via-reliability of 2 metal-build air gap structures was tested by thermal cycling and constant thermal stress. No significant difference in via reliability was observed between SiOC interconnects with and without air gaps. However, failure analysis showed weak spots near the bottom of the barrier, which could be detrimental for dual damascene reliability. These weak spots at the barrier bottom could lead to catastrophic failures in both via and lines during electromigration stressing. Moreover, process-related issues such as bottom liner undercut and copper corrosion need to be controlled more stringent before this air gap approach can be successfully implemented. Ó 2006 Elsevier B.V. All rights reserved. Keywords: Self-aligned air gaps; Plasma damaged SiOC; Capacitance reduction; Dielectric reliability; Via reliability
1. Introduction The continuous downscaling of device dimensions requires the introduction of porous low-k materials as intermetal-dielectric, in order to compensate for the increasing interline capacitances. The integration of porous low-k materials into copper dual-damascene structures is accompanied by a tremendous number of challenges [1], delaying the introduction of these dielectrics as compared with the ITRS roadmap requirements [2,3]. One of the showstoppers in the integration of porous low-k materials is known to be plasma damage during etch and/or strip, in which the exposed material is partially modified [1,4]. In the case of SiOC-based low-k materials, the *
Corresponding author. Tel.: +32 16 288309; fax: +32 16 281214. E-mail address: [email protected] (R.J.O.M. Hoofman).
0167-9317/$ - see front matter Ó 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2006.09.025
modification can be translated to carbon-depletion of these layers. Carbon-depletion results in increasing k-values, higher sensitivity to moisture absorption and reliability degradation of these low-k dielectrics. These carbon-depleted layers are ‘oxide’-like and can therefore easily and selectively wet-etched in dilute HF-solutions. Therefore, one could opt for the selective removal of these layers prior to barrier deposition. However, these layers could also act as ‘pore sealant’ [5] and will therefore facilitate a thin, continuous barrier deposition on the porous low-k sidewall. Removal of this layer will open up the pore structure again, which might be detrimental for barrier reliability. Recently, it has been shown that it is also possible to selectively remove the carbon-depleted layer directly after chemical mechanical planarization (CMP) [6]. The latter approach in combination with a subsequent non-conformal chemical vapor deposition (CVD) [7] enables the selective formation
R.J.O.M. Hoofman et al. / Microelectronic Engineering 83 (2006) 2150–2154
of air gaps at the sidewalls. Selective replacement of the damaged low-k region with air could be a viable integration option. Air or vacuum is known to be the ultimate scalable ‘porous’ inter-metal dielectric, since its k-value equals unity. Nonetheless, the introduction of air gaps in future interconnects may introduce various challenges, such as degradation of reliability performance. In this paper the authors will present the pros and cons of self-aligned multilevel air gaps structures, which were fabricated using the combination of selective damage-removal by HF and non-conformal CVD capping. 2. Experimental Single damascene interconnects were fabricated in two different SiOC-dielectrics (containing either 6% or 18% porosity). It is important to note that both dry etch and resist strip were carried out in a Lam Exelan2300TM chamber using different plasma chemistries (mainly CF4/O2 based). After CMP, the damaged low-k material on the sidewall can be selectively removed by exposure to diluted HF solutions for 30 to 120 s. HF concentrations between 0.5% and 2% have been used. After selective removal of the damaged sidewall material, the gaps are closed by a non-conformal SiC-deposition. The integration scheme is schematically shown in. After CVD-capping of the gaps, the next dielectric layer can be deposited. In all cases, the final step is the deposition of a 50/330/500 nm SiC/SiO2/ Si3N4 passivation stack on top. In the TEM micrograph of Fig. 1, it can be seen that the air-gaps are symmetrically formed directly next to the copper lines. The fabricated interconnects were parametrically characterized, followed by a more thorough reliability screening. For the SD M1 interconnects, leakage current, voltage ramp and time-dependent-dielectric-breakdown (TDDB) measurements have been performed at wafer level on at least 25 dies using centimetre-long meander-fork structures with varying dimensions (80–500 nm line width/spacing). The chuck temperature can be varied between room temdamaged SiOC Cu
Cu
SiOC SiC(N)
2151
perature and 200 °C. Air gaps-containing dual damascene interconnects were subjected to different stresses, such as thermal cycles of 1 h at 400 °C and continuous thermal stress at 250 °C (in order to investigate stress-induced voiding). All reliability measurements were performed under nitrogen ambient. 3. Results and discussion 3.1. Multilevel air gap integration and related process issues The size of the self-aligned air gaps can be tuned through the extent of the plasma damage at the sidewall. As can be seen in Fig. 2, air gaps formed in porous SiOC dielectrics are substantially wider than for ‘dense’ SiOC. Therefore, wider air gaps can be obtained either by using a more porous SiOC dielectric or changing the plasma etch- and strip-conditions (higher powers and more oxidizing chemistries). By tuning the size of the air gaps, a multilevel interconnect can be fabricated with high performance without compromising the mechanical integrity of the construction. In Fig. 3 a STEM (scanning transmission electron microscope) crosssection image of a dual damascene via-chain is shown, where self-aligned air gaps were formed in a ‘dense’ SiOC at metal-1 level. Unfortunately, during the integration of these selfaligned air gaps, process-related issues were also observed. One of the issues encountered was the attack of HF on the SiC(N) dielectric bottom layer, resulting in an undercut and eventually in delamination of the copper lines. The vulnerability of SiC(N) to HF is the direct result of exposure to ‘hard’ etch- and strip plasmas, since they can also cause carbon-depletion in the bottom-liners during the patterning process, which facilitates HF-attack. Therefore, a trade-off needs to be made between the extent of the plasma damage in the SiOC low-k and the preservation of the SiC(N) liner material. The latter could be achieved by using a metal hard mask approach [8,9], which enables the shift of the resist strip process to an earlier phase in the patterning process and consequently prevents severe damage to the bottom liners. Finally, HF in the presence of oxygen is also found to attack copper [10], resulting in increasing resistances (up to 5%). Therefore, a stringent process control is necessary in order to prevent the above-mentioned issues. 3.2. Performance improvement
(1) M1-stack (SiOC)
(3) Dielectric capping
(2) HF wet etch
(4) Integrated airgaps
Fig. 1. Schematic representation of selective air gap-formation in a single damascene SiOC stack.
System level performance can be significantly improved by integrating air gaps in several metal levels due to lower intra- and inter-level capacitances. Experimentally, it has been found that the effect of the self-aligned air gaps on the capacitance-reduction is larger for the narrower spaces (see Fig. 4), since for this case a larger fraction of interline material will be removed. In this experiment the extent of air gaps was also varied by increasing the HF-exposure time, evidenced by larger capacitance reductions. For the
2152
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Fig. 2. Cross-section SEM pictures of self-aligned gaps formed in a porous SiOC (left) and a dense SiOC dielectric (right).
Fig. 3. STEM image of a dual damascene via-chain embedded in a SiOC material. At metal-1 self-aligned air gaps have been created.
spaces and/or in combination with a more porous SiOC material could result in even larger capacitance reductions. However, the appearance of the previously discussed process integration issues and high-porosity related reliability challenges might put limits to this further downscaling.
Relative capacitance decrease (%)
20
1' HF 2' HF 4' HF 15
3.3. Reliability 10
5
0
0
50
100
150
200
250
300
350
Spacing (nm)
Fig. 4. Relative capacitance decrease as function of different dielectric spacings at M1. Different sized air gaps have been created in a porous SiOC material by wet-etching in a 1% HF solution for different times.
50 nm spaces, the latter resulted in a capacitance decrease of 7% for 1 min exposure, while 12% and 20% decreases were achieved by extending the exposure to HF to 2 and 4 min, respectively. Further downscaling of the dielectric
At single damascene level, the reliability has been investigated by screening both the electromigration (EM) and the time-dependent dielectric breakdown (TDDB) behaviour. Earlier work showed typical abrupt EM failures, resulting in tight monomodal distributions [6]. In this work it has been found that the failures could mainly be attributed to extrusions extending from the bottom corners of the SiC(N) liner towards the top interface (see SEM-picture on the left in Fig. 5). The right illustration in Fig. 5 shows finite element analysis (FEA) results of Von-Mises (VM) stresses in the region neighbouring the air gap. This result shows high stress spots in the barriers at the bottom corner, which could explain the extrusion behaviour. TDDB lifetimes were measured for different spacings of a porous SiOC material in which self-aligned air gaps were created optionally. As can be seen in Fig. 6, the 150 nm structures with air gaps incorporated (30 years at user conditions) are outperforming the structures which contain only porous SiOC material (2 years at user conditions).
R.J.O.M. Hoofman et al. / Microelectronic Engineering 83 (2006) 2150–2154
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Fig. 5. (left) FIB cross-section of a typical electromigration failure showing copper extrusions; (right) finite element analysis showing Von Mises stresses in the region close to the self aligned air gaps containing self-aligned airgaps. On the entire right a detail is presented of the Von Mises stresses in the metallic barrier bordering the air gap. 1E+04
99.99
small bubble size indicates large shape factor
99.9
Air gaps (s=150nm)
1E+02
99 95 90
1E+01
1E+00
1E-01
1E-02 0.0
SiOC low-k (s=150nm) 1.0
Percent
Expected lifetime a[s]
1E+03
Air gaps (s=50nm)
80 70 50 30 20 10 5
2.0
3.0
4.0
5.0
Breakdown field [MV/cm]
Fig. 6. t63% Failure time versus electric field extracted from TDDB measurements on 50 and 150 nm dielectric spacings of a porous SiOC material containing self-aligned airgaps. The bubble size represents 1/b (shape parameter extracted from Weibull distributions).
The latter can be explained knowing that the damaged material degrades the dielectric reliability significantly [11,12]. Unfortunately, downscaling of the dielectric spacings (containing self-aligned air gaps) results in significant reliability degradation (as can be seen from comparing the TDDB data in Fig. 6 for the 150 nm with the 50 nm spacings). Finally, dual damascene reliability issues associated with unlanded via have been investigated by varying the enclosure of the via landing on metal-1 from 100 to +100 nm (in either one direction or in both the x- and y-directions). The electrical results obtained on these structures are presented in Fig. 7. As can be seen from this figure, the resistance increases for the more negatively enclosed vias due to a smaller contact area, while the +50 and +100 nm enclosed via chains show identical resistance distributions. A yield loss is recorded for the most negatively enclosed
-50nm
-100nm
+50nm/ +100nm
1 .1
zero
.01 1
10 via resistance
100
Fig. 7. Cumulative distribution of via-resistance of a via-chain with 150 nm-sized vias, in which the enclosure has been systematically varied from 100 to +100 nm. The metal-1 dielectric contains self-aligned airgaps. Thermal cycling experiments with dense Cu/low-k structures without air gaps show comparable trends.
vias. Thermal cycling of the dual damascene structures between room temperature and 400 °C was carried out to simulate multilayer deposition. As can be seen in Fig. 8, the resistance increase per cycle depends on the via enclosure. The negatively aligned vias exhibit the largest via increase. Thermal cycling experiments with dense Cu/lowk structures without air gaps incorporated show a comparable trend. These findings suggest that the incorporation of air gaps into a dense low-k material does not have a detrimental effect on the via reliability. Similar trends were observed for SIV stressing. For the misaligned via, failure
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+100nm
+50nm
zero
1st cycle
2nd cycle
3rd cycle
-50nm
0
10
20
30
40
50
Via resistance increase (%)
Fig. 8. Via-resistance increase upon thermal cycling for different enclosure via-chains. The metal-1 dielectric contains self-aligned airgaps.
at the trench sidewall of SiOC low-k materials using diluted HF. The extent of the gaps was shown to be tuneable by either varying the plasma damage in SiOC low-k materials or by exposure to different HF etch conditions. The incorporation of air gaps into porous SiOC materials yielded significant capacitance reduction without a loss of dielectric reliability performance. Thermal stressing of viachains containing negatively-enclosed vias landing on metal-1 air gaps was found to have a comparable effect on via-yield and -resistance as for vias landing on dense low-k. However, failure analysis showed weak spots at the bottom of the barrier, which could be detrimental for dual damascene reliability. In addition, process-related issues were also observed, such as bottom liner undercut and copper corrosion. While this simple self-aligned air gap process flow appears to offer significant capacitance reduction with no obvious reliability issues for dual damascene structures, much better process control and more reliability studies would be required to successfully implement this flow. References
Fig. 9. Post-stress STEM analysis of a zero-overlap via-chain embedded in a ‘dense’ SiOC dielectric containing air gaps at metal-1.
analysis of the stressed via-structures showed discontinuous barriers at the via-bottoms accompanied with copper extrusions (see Fig. 9). This could point to a serious reliability issue, which could show up especially during electromigration stressing of such structures. 4. Conclusion Self-aligned multilevel air gap integration has been demonstrated by selective removal of the plasma-damage
[1] R.J.O.M. Hoofman, G.J.A.M. Verheijden, J. Michelon, F. Iacopi, Y. Travaly, M.R. Baklanov, Zs. Tokei, G.P. Beyer, Microelectron. Eng. 80 (2005) 337–344. [2] International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1994. [3] International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2004. [4] M.R. Baklanov, Q.T. Le, E. Kesters, F. Iacopi, J. Van Aelst, H. Struyf, W. Boullart, S. Vanhaelemeersch, K. Maex, in: Proceedings of the IEEE 2004 International Interconnect Technology Conference (IITC2004), pp. 187–189. [5] T. Abell, K. Maex, Microelectron. Eng. 76 (2004) 16–19. [6] J.P. Gueneau de Mussy, C. Bruynseraede, Zs. Tokei, G.P. Beyer, K. Maex, in: Proceedings of the IEEE 2005 International Interconnect Technology Conference (IITC2005), pp. 150–152. [7] V. Arnal, J. Torres, P. Gayet, R. Gonella, P. Spinelli, M. Guillermet, J.-P. Reynard, C. Verove, in: Proceedings of the IEEE 2001 International Interconnect Technology Conference (IITC2001), pp. 298–300. [8] O. Hinsinger, R. Fox, E. Sabouret, C. Goldberg, C. Verove, W. Besling, P. Brun, E. Josse, C. Monget, O. Belmont, J. Van Hasselt, B.G. Sharma, J.P. Jacquemin, P. Vannier, A. Humbert, D. Bunel, R. Gonella, E. Mastromatteo, D. Reber, A. Farcy, J. Mueller, P. Christie, V.H. Nguyen, C. Cregut, T. Berger, Technical Digest, International Electron Devices Meeting (IEDM 2004), pp. 317–320. [9] T. Furusawa, S. Machida, D. Ryuzaki, K. Sameshima, T. Ishida, K. Ishikawa, N. Miura, N. Konishi, T. Saito, H. Yamaguchi, in: Proceedings of the International Interconnect Technology Conference (IITC2003), pp. 195–197. [10] S. Zhong, Z.G. Yang, J.J. Cai, J. Electrochem. Soc. 152 (2005) C143– C148. [11] M. Aimadeddine, V. Arnal, A. Farcy, C. Guedj, T. Chevolleau, N. Posseme, T. David, M. Assous, O. Louveau, F. Volpi, J. Torres, Microelectron. Eng. 82 (2005) 341–347. [12] Zs. Tokei, Y.L. Li, G.P. Beyer, Microelectron. Reliab. 45 (2005) 1436–1442.
Self-aligned multi-level air gap integration R.J.O.M. Hoofman a,*, R. Caluwaerts b, J. Michelon a, P. Herrero Bernabe´ c, J.P. Gueneau de Mussy b, C. Bruynseraede b, J.M. Lee d, S. List e, P.H.L. Bancken a, G. Beyer b a
c
Philips Research Leuven, Kapeldreef 75, B-3001 Leuven, Belgium b IMEC, Kapeldreef 75, B-3001 Leuven, Belgium University of Valladolid, Department of Electronics, Camino del Cementerio s/n , 47011 Valladolid, Spain d Samsung assignee at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium e Intel assignee at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium Available online 17 October 2006
Abstract Dual damascene self-aligned air gap structures have been fabricated through selective removal of interline plasma-damaged SiOC material using dilute HF solutions after metal CMP. The extent of the gaps was shown to be tuneable. The creation of interline air gaps through removal of damaged dielectric yielded significant capacitance reduction plus in addition dielectric reliability improvement. The via-reliability of 2 metal-build air gap structures was tested by thermal cycling and constant thermal stress. No significant difference in via reliability was observed between SiOC interconnects with and without air gaps. However, failure analysis showed weak spots near the bottom of the barrier, which could be detrimental for dual damascene reliability. These weak spots at the barrier bottom could lead to catastrophic failures in both via and lines during electromigration stressing. Moreover, process-related issues such as bottom liner undercut and copper corrosion need to be controlled more stringent before this air gap approach can be successfully implemented. Ó 2006 Elsevier B.V. All rights reserved. Keywords: Self-aligned air gaps; Plasma damaged SiOC; Capacitance reduction; Dielectric reliability; Via reliability
1. Introduction The continuous downscaling of device dimensions requires the introduction of porous low-k materials as intermetal-dielectric, in order to compensate for the increasing interline capacitances. The integration of porous low-k materials into copper dual-damascene structures is accompanied by a tremendous number of challenges [1], delaying the introduction of these dielectrics as compared with the ITRS roadmap requirements [2,3]. One of the showstoppers in the integration of porous low-k materials is known to be plasma damage during etch and/or strip, in which the exposed material is partially modified [1,4]. In the case of SiOC-based low-k materials, the *
Corresponding author. Tel.: +32 16 288309; fax: +32 16 281214. E-mail address: [email protected] (R.J.O.M. Hoofman).
0167-9317/$ - see front matter Ó 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2006.09.025
modification can be translated to carbon-depletion of these layers. Carbon-depletion results in increasing k-values, higher sensitivity to moisture absorption and reliability degradation of these low-k dielectrics. These carbon-depleted layers are ‘oxide’-like and can therefore easily and selectively wet-etched in dilute HF-solutions. Therefore, one could opt for the selective removal of these layers prior to barrier deposition. However, these layers could also act as ‘pore sealant’ [5] and will therefore facilitate a thin, continuous barrier deposition on the porous low-k sidewall. Removal of this layer will open up the pore structure again, which might be detrimental for barrier reliability. Recently, it has been shown that it is also possible to selectively remove the carbon-depleted layer directly after chemical mechanical planarization (CMP) [6]. The latter approach in combination with a subsequent non-conformal chemical vapor deposition (CVD) [7] enables the selective formation
R.J.O.M. Hoofman et al. / Microelectronic Engineering 83 (2006) 2150–2154
of air gaps at the sidewalls. Selective replacement of the damaged low-k region with air could be a viable integration option. Air or vacuum is known to be the ultimate scalable ‘porous’ inter-metal dielectric, since its k-value equals unity. Nonetheless, the introduction of air gaps in future interconnects may introduce various challenges, such as degradation of reliability performance. In this paper the authors will present the pros and cons of self-aligned multilevel air gaps structures, which were fabricated using the combination of selective damage-removal by HF and non-conformal CVD capping. 2. Experimental Single damascene interconnects were fabricated in two different SiOC-dielectrics (containing either 6% or 18% porosity). It is important to note that both dry etch and resist strip were carried out in a Lam Exelan2300TM chamber using different plasma chemistries (mainly CF4/O2 based). After CMP, the damaged low-k material on the sidewall can be selectively removed by exposure to diluted HF solutions for 30 to 120 s. HF concentrations between 0.5% and 2% have been used. After selective removal of the damaged sidewall material, the gaps are closed by a non-conformal SiC-deposition. The integration scheme is schematically shown in. After CVD-capping of the gaps, the next dielectric layer can be deposited. In all cases, the final step is the deposition of a 50/330/500 nm SiC/SiO2/ Si3N4 passivation stack on top. In the TEM micrograph of Fig. 1, it can be seen that the air-gaps are symmetrically formed directly next to the copper lines. The fabricated interconnects were parametrically characterized, followed by a more thorough reliability screening. For the SD M1 interconnects, leakage current, voltage ramp and time-dependent-dielectric-breakdown (TDDB) measurements have been performed at wafer level on at least 25 dies using centimetre-long meander-fork structures with varying dimensions (80–500 nm line width/spacing). The chuck temperature can be varied between room temdamaged SiOC Cu
Cu
SiOC SiC(N)
2151
perature and 200 °C. Air gaps-containing dual damascene interconnects were subjected to different stresses, such as thermal cycles of 1 h at 400 °C and continuous thermal stress at 250 °C (in order to investigate stress-induced voiding). All reliability measurements were performed under nitrogen ambient. 3. Results and discussion 3.1. Multilevel air gap integration and related process issues The size of the self-aligned air gaps can be tuned through the extent of the plasma damage at the sidewall. As can be seen in Fig. 2, air gaps formed in porous SiOC dielectrics are substantially wider than for ‘dense’ SiOC. Therefore, wider air gaps can be obtained either by using a more porous SiOC dielectric or changing the plasma etch- and strip-conditions (higher powers and more oxidizing chemistries). By tuning the size of the air gaps, a multilevel interconnect can be fabricated with high performance without compromising the mechanical integrity of the construction. In Fig. 3 a STEM (scanning transmission electron microscope) crosssection image of a dual damascene via-chain is shown, where self-aligned air gaps were formed in a ‘dense’ SiOC at metal-1 level. Unfortunately, during the integration of these selfaligned air gaps, process-related issues were also observed. One of the issues encountered was the attack of HF on the SiC(N) dielectric bottom layer, resulting in an undercut and eventually in delamination of the copper lines. The vulnerability of SiC(N) to HF is the direct result of exposure to ‘hard’ etch- and strip plasmas, since they can also cause carbon-depletion in the bottom-liners during the patterning process, which facilitates HF-attack. Therefore, a trade-off needs to be made between the extent of the plasma damage in the SiOC low-k and the preservation of the SiC(N) liner material. The latter could be achieved by using a metal hard mask approach [8,9], which enables the shift of the resist strip process to an earlier phase in the patterning process and consequently prevents severe damage to the bottom liners. Finally, HF in the presence of oxygen is also found to attack copper [10], resulting in increasing resistances (up to 5%). Therefore, a stringent process control is necessary in order to prevent the above-mentioned issues. 3.2. Performance improvement
(1) M1-stack (SiOC)
(3) Dielectric capping
(2) HF wet etch
(4) Integrated airgaps
Fig. 1. Schematic representation of selective air gap-formation in a single damascene SiOC stack.
System level performance can be significantly improved by integrating air gaps in several metal levels due to lower intra- and inter-level capacitances. Experimentally, it has been found that the effect of the self-aligned air gaps on the capacitance-reduction is larger for the narrower spaces (see Fig. 4), since for this case a larger fraction of interline material will be removed. In this experiment the extent of air gaps was also varied by increasing the HF-exposure time, evidenced by larger capacitance reductions. For the
2152
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Fig. 2. Cross-section SEM pictures of self-aligned gaps formed in a porous SiOC (left) and a dense SiOC dielectric (right).
Fig. 3. STEM image of a dual damascene via-chain embedded in a SiOC material. At metal-1 self-aligned air gaps have been created.
spaces and/or in combination with a more porous SiOC material could result in even larger capacitance reductions. However, the appearance of the previously discussed process integration issues and high-porosity related reliability challenges might put limits to this further downscaling.
Relative capacitance decrease (%)
20
1' HF 2' HF 4' HF 15
3.3. Reliability 10
5
0
0
50
100
150
200
250
300
350
Spacing (nm)
Fig. 4. Relative capacitance decrease as function of different dielectric spacings at M1. Different sized air gaps have been created in a porous SiOC material by wet-etching in a 1% HF solution for different times.
50 nm spaces, the latter resulted in a capacitance decrease of 7% for 1 min exposure, while 12% and 20% decreases were achieved by extending the exposure to HF to 2 and 4 min, respectively. Further downscaling of the dielectric
At single damascene level, the reliability has been investigated by screening both the electromigration (EM) and the time-dependent dielectric breakdown (TDDB) behaviour. Earlier work showed typical abrupt EM failures, resulting in tight monomodal distributions [6]. In this work it has been found that the failures could mainly be attributed to extrusions extending from the bottom corners of the SiC(N) liner towards the top interface (see SEM-picture on the left in Fig. 5). The right illustration in Fig. 5 shows finite element analysis (FEA) results of Von-Mises (VM) stresses in the region neighbouring the air gap. This result shows high stress spots in the barriers at the bottom corner, which could explain the extrusion behaviour. TDDB lifetimes were measured for different spacings of a porous SiOC material in which self-aligned air gaps were created optionally. As can be seen in Fig. 6, the 150 nm structures with air gaps incorporated (30 years at user conditions) are outperforming the structures which contain only porous SiOC material (2 years at user conditions).
R.J.O.M. Hoofman et al. / Microelectronic Engineering 83 (2006) 2150–2154
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Fig. 5. (left) FIB cross-section of a typical electromigration failure showing copper extrusions; (right) finite element analysis showing Von Mises stresses in the region close to the self aligned air gaps containing self-aligned airgaps. On the entire right a detail is presented of the Von Mises stresses in the metallic barrier bordering the air gap. 1E+04
99.99
small bubble size indicates large shape factor
99.9
Air gaps (s=150nm)
1E+02
99 95 90
1E+01
1E+00
1E-01
1E-02 0.0
SiOC low-k (s=150nm) 1.0
Percent
Expected lifetime a[s]
1E+03
Air gaps (s=50nm)
80 70 50 30 20 10 5
2.0
3.0
4.0
5.0
Breakdown field [MV/cm]
Fig. 6. t63% Failure time versus electric field extracted from TDDB measurements on 50 and 150 nm dielectric spacings of a porous SiOC material containing self-aligned airgaps. The bubble size represents 1/b (shape parameter extracted from Weibull distributions).
The latter can be explained knowing that the damaged material degrades the dielectric reliability significantly [11,12]. Unfortunately, downscaling of the dielectric spacings (containing self-aligned air gaps) results in significant reliability degradation (as can be seen from comparing the TDDB data in Fig. 6 for the 150 nm with the 50 nm spacings). Finally, dual damascene reliability issues associated with unlanded via have been investigated by varying the enclosure of the via landing on metal-1 from 100 to +100 nm (in either one direction or in both the x- and y-directions). The electrical results obtained on these structures are presented in Fig. 7. As can be seen from this figure, the resistance increases for the more negatively enclosed vias due to a smaller contact area, while the +50 and +100 nm enclosed via chains show identical resistance distributions. A yield loss is recorded for the most negatively enclosed
-50nm
-100nm
+50nm/ +100nm
1 .1
zero
.01 1
10 via resistance
100
Fig. 7. Cumulative distribution of via-resistance of a via-chain with 150 nm-sized vias, in which the enclosure has been systematically varied from 100 to +100 nm. The metal-1 dielectric contains self-aligned airgaps. Thermal cycling experiments with dense Cu/low-k structures without air gaps show comparable trends.
vias. Thermal cycling of the dual damascene structures between room temperature and 400 °C was carried out to simulate multilayer deposition. As can be seen in Fig. 8, the resistance increase per cycle depends on the via enclosure. The negatively aligned vias exhibit the largest via increase. Thermal cycling experiments with dense Cu/lowk structures without air gaps incorporated show a comparable trend. These findings suggest that the incorporation of air gaps into a dense low-k material does not have a detrimental effect on the via reliability. Similar trends were observed for SIV stressing. For the misaligned via, failure
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+100nm
+50nm
zero
1st cycle
2nd cycle
3rd cycle
-50nm
0
10
20
30
40
50
Via resistance increase (%)
Fig. 8. Via-resistance increase upon thermal cycling for different enclosure via-chains. The metal-1 dielectric contains self-aligned airgaps.
at the trench sidewall of SiOC low-k materials using diluted HF. The extent of the gaps was shown to be tuneable by either varying the plasma damage in SiOC low-k materials or by exposure to different HF etch conditions. The incorporation of air gaps into porous SiOC materials yielded significant capacitance reduction without a loss of dielectric reliability performance. Thermal stressing of viachains containing negatively-enclosed vias landing on metal-1 air gaps was found to have a comparable effect on via-yield and -resistance as for vias landing on dense low-k. However, failure analysis showed weak spots at the bottom of the barrier, which could be detrimental for dual damascene reliability. In addition, process-related issues were also observed, such as bottom liner undercut and copper corrosion. While this simple self-aligned air gap process flow appears to offer significant capacitance reduction with no obvious reliability issues for dual damascene structures, much better process control and more reliability studies would be required to successfully implement this flow. References
Fig. 9. Post-stress STEM analysis of a zero-overlap via-chain embedded in a ‘dense’ SiOC dielectric containing air gaps at metal-1.
analysis of the stressed via-structures showed discontinuous barriers at the via-bottoms accompanied with copper extrusions (see Fig. 9). This could point to a serious reliability issue, which could show up especially during electromigration stressing of such structures. 4. Conclusion Self-aligned multilevel air gap integration has been demonstrated by selective removal of the plasma-damage
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