- Email: [email protected]
Serial communication
Serial communication Connection between computers and terminals is often by datalinks. John Wakerly gives the basic principles of serial communication
Computer
Serial data/inks are most commonly used by computers to communicate with both local and remote terminals. In this artic.le, the simple serial datalinks that are most often used are described. Serial communication means that information transmitted from source to destination is carried over a single pathway. Within the immediate physical confines of a computer system, the use of serial links is most often motivated by cost considerations - serial links can reduce packaging and cabling cost and reduce the number and complexity of components for sending and receiving data. Outside the computer system, use of a serial communication link is often forced by the very nature of the available data transmission media - telephone lines and radio waves can only send one analogue signal at a time.
CRT Terminal
/
cP°l .I ,"~'~'>']~;:1 •echo
I
OutpUtport
]
Serial Link
'
~'~,,._ _ I ~
InpUtport
Serial Link
Figure 1. Full~luplex operation. Transmission is independent and simultaneous in both directions Computer
CRT Terminal
Serial Link
TYPES OF SERIAL DATALINKS A simplex serial datalink transmits data in only one direction. (A connection from a computer to a remote printer could be a simplex serial datalink.) In most applications, there are two serial datalinks between a computer and a terminal, one for transmission in each direction. This is called full-duplex operation and is illustrated in Figure 1. Transmission in the two directions in independent and simultaneous. A typical terminal consists of a keyboard and a screen or hardcopy printer. Even though they may be packaged together, the keyboard and screen are logically independent devices. When a character is typed at the keyboard, it is not automatically printed. In most full-duplex systems, the computer must receive each character and echo it back to the terminal. A few full-duplex systems have terminals hard-wired to locally print all typed characters, saving the computer the overhead of echoing them. This mode of operation is sometimes calledecho-plex. (The 'half-duplex' option on most modern terminals is really echo-plex.) Bidirectional communication can also be achieved with a single link as shown in Figure 2, but only in one direction at a time. A special control sequence is needed to 'turn the line around' whenever the direction of transmission is changed. This is called half-duplex operation.
Computer Systems Laboratory, Stanford University, Stanford CA 94305, USA This article is adapted from Appendices A and C of Wakerly, J F Microcomputer architecture and programming John Wiley (1981 )
vo15 no 6july/august 1981
Figure 2. Half-duplex operation. Transmission is bidirectional, but only in one direction at a time Local printing of typed characters is essential with halfduplex links because of the high overhead that would be incurred if the computer had to turn the line around to echo each character. Because of decreased costs and increased capabilities, most serial links in use today are full-duplex. The rate of transmission of a data stream in bit/s is called the bit rate. This rate is sometimes mistakenly called the 'baud rate'. The bit rate and the baud rate are often equal, but not always; the exact definition of baud rate must wait until we discuss modems. Serial transmission rates for typical computer terminals range from 75 to 19 200 bit/s. The reciprocal of the bit rate is called the bit time-the time that it takes to transmit one bit. By far the most common character encoding in minicomputer and microcomputer systems is ASCI I, which represents each character by 7 bits (see Appendix). A character is transmitted over the link one bit at a time, with two to four control bits added to each character. Thus nine to 11 bits are required to transmit one character and the typical bit transmission rates mentioned above yield about eight to 2000 character/s. A typical 24 x 80 CRT screen contains 1920 characters, so it can be completely filled in one second by a 19.2 kbit/s datalink.
0141-9331/81/060247-07 $02.00 © 1981 IPC Business Press
247
Standard bit rates are 75, 1 I0, 134.5,150, 300,600, 1200, 2400, 4800, 9600 and 19 200 bit/s. The standard bit rates form a geometric progression, except for 110 bit/s, used by old fashioned ASR-33 teleprinters and similar equipment, and 134.5 bit/s, used by some IBM printing terminals. Modern CRT terminals have switch-selectable bit rates up to a maximum of 9.6 or 19.2 kbit/s. Most often the same bit rate is used for both directions in a full-duplex serial communication link. This is especially true in communications between a computer and a local terminal, since data is carried over relatively inexpensive short high-bandwidth copper wires. On the other hand, there is nothing to prevent different bit rates from being used in a 'split bit rate' arrangement. This is advantageous for connections to remote equipment by telephone lines or other expensive links with limited bandwidth. A human can type only so fast, even with a repeat key, and so a bit rate supporting more than 15 characters per second from a keyboard to the computer is wasteful. On the other hand, a computer can easily send data to a CRT continuously at rates of 100 characters per second or higher. Therefore, one popular split bit rate arrangement uses a 150 bit/s link from terminal to computer, but 1200 bit/s from computer to terminal. A simple serial communication link uses the signals mark and space to encode the binary digits 1 and 0, respectively. The names mark and space, taken from telegraphy, remind us that the physical values used to represent Is and Os depend on the type of physical link. In fact, each bit has several representations during its journey from source to destination, as shown by the example in Figure 3. Within a computer, I s and Os of a character are represented by a sequence of standard voltage levels for a particular logic family, say transistor-transistor logic (TTL). An interface in the computer converts TTL levels to another standard set of voltage levels prescribed by EIA (Electronic Industries Association) standard RS-232 and connects to a device called a modem. A standard telephone link cannot transmit and receive absolute voltage levels, only sounds whose frequency components are between approximately 300 and 3000 Hz. Therefore the modem converts RS-232 voltage levels into tones that can be transmitted over a telephone line. For example, the modem could transmit a 1270 Hz tone whenever an RS-232 mark level is present, and 1070 Hz for an RS-232 space level. This modulation scheme is
Computer (1.o)
(2,,. o., v,;
(-3 v. +3 v)- I
Telephone LinHz)[ e (1270 HZ,1070 [Teleprinter[( (~orrm~:L°: p) ~
(E_I;vRS'23~)~~
Figure 3. Each bit has several representations during its journey from source to destination
248
1
called frequency-shift keying (FSK). Another modem at the receiving end can detect FSK tones and convert them back into RS-232 levels. In Figure 3, the RS-232 levels at the receiving end are converted to a current-loop interface - a pair of wires in which a 20 mA current represents a mark and 0 mA represents a space. The resulting sequence of on/off currents controls the motion of a teleprinter's mechanical wheels and cams that finally print a character. Alternatively, the RS-232 levels could be connected to a typical CRT terminal which is designed to accept RS-232 levels directly. Most serial communication links are full-duplex, so that Figure 3 should really show another serial link in the reverse direction. However, another telephone line and pair of modems usually is not required for the reverse link. Most modems can provide a full-duplex link using a single telephone line. They do this by using a different pair of frequencies for communicating in the reverse direction, for example, 2225 Hz for a mark and 2025 Hz for a space. The choice of transmitting and receiving frequencies for the computer and terminal is predetermined by convention in any given system. The modem handles the links in both directions simultaneously (the name modem stands for modulator/demodulator). The bit rate that can be reliably transmitted and received by a particular modem is limited. For example, suppose we tried to send data at 9600 bit/s using the FSK modulation scheme described above. Then one bit time would correspond to only about one-eighth of a sine wave period at a transmitting frequency of 1270 Hz. Such a tiny slice of a sine wave cannot be reliably detected at the receiving end after passing through the distortions of the telephone network. Modulation and demodulation schemes more sophisticated than FSK are used in high bit-rate modems. It may seem paradoxical that it is indeed possible to send 9600 bit/s over a telephone link that has a bandwidth of only about 3000 Hz. Such high bit rates are achieved by modulation techniques in which each transmitted signal element has more than two values. For example, some 1200 bit/s modems use a modulation scheme that transmits only 600 signal element/s, where each signal element can have one of four values, representing the four possible combinations of two bits. The number of signal elements per second is called the baud rate. In low-speed modems the bit rate and baud rate are usually equal; in high-speed modems they usually are not. Inexpensive low-speed modems transmit and receive data at 3 0 0 - I 200 bit/s. When a terminal is connected directly to a computer without using a telephone link and modems, it is usually practical to use a much higher bit rate such as 9.6 or 29.2 kbit/s.
ASYCHRONOUS SER IAL COMMUNICATION FORMAT The majority of serial communication links now in use are asynchronous links. Asynchronous means that the transmitter and receiver do not share a common clock, and no clock signal is sent with the data. So how does the receiver
microprocessors and microsystems
Mark
start bit
idle
data bit 0
data bit 1
data parity stop bit n*l bit bit 1
I I I I
Space
i
...
stop bit 2
start bit
I
i
I
t
frame
q 1,~
(e) start bit
idle
1
0
1
0
1
1
0
odd parity stop bit bit 1
stop bit 2
idle
Mark
Space
I
I
I
I
I
I
T
(b)
start bit
idle
I
0
I
0
I
1
0
I
1
I
0
I
1
odd parity stop bit bit
I
idle
I
(c)
Figure 4a. Standard asynchronous serial bit format, 4b. bit format for operation o f an aM fashioned teleprinter at 110 bit/s, 4c. bit format for operation at a more usual rate o f 300 bit/s know.when the databits begin and end? We shall describe a simple algorithm that can be used if the transmitter and receiver agree on a standard bit rate and format. The standard asynchronous serial bit format used by computers and terminals is shown in Figure 4a. When the transmitter is idle (i.e. no data being sent), the line is maintained in a continuous mark state. The transmitter may initiate a character at any time by sending a start bit, that is, by putting the line in the space state for exactly one bit time. It then transmits the databits, least significant first, optionally followed by an even or odd parity bit. (An even parity bit is chosen so that the total number of Is among the databits and parity bit is even.) Finally, the transmitter maintains the mark state for I, 1.5 or 2 bit times - so-called stop bits. The period of time from the beginning of the start bit to the end of the stop bits is called a frame. After the stop bits, the transmitter may immediately send a new start bit if it has another character to send. Otherwise, it may maintain the mark state as long as it is idle. A new start bit may be sent at any time, not necessarily an integral number of bit times since the last stop bit. An old fashioned teleprinter operating at 110 bit/s transmits a start bit, seven ASCII data bits, an odd parity bit and two stop bits, as shown in Figure 4b for the character 0110101 (ASCII '5'). Since 11 bits are required to send each character, at 1 I0 bit/s there are I0 character/s. Terminals operating at 300 bit/s and higher usually transmit a start bit, seven ASCII data bits, a parity bit and one stop bit, as shown in Figure 4c for the character 1010100 (ASCII 'T'). Since only I 0 bits are needed for each character, at 300 bit/s there are 30 character/s. The usage of the parity bit varies widely among different systems. There are three possibilities: even, odd or no parity. These possibilities are compounded by the fact that most terminals and computers can send and receive an optional eighth databit before the optional parity bit. There are four possibilities for the eighth bit: not transmitted, constant I, constant 0 or useful data. The last case creates an additional 128 non-ASCII characters that may be
vol 5 no 6july~august 1981
transmitted between the terminal and computer for extended character sets or special functions. In a serial communication link, the transmitter and receiver must agree upon all of the parameters of the bit format in Figure 4a, including a nominal bit time (or equivalently, bit rate). Since transmitter and receiver have different clocks, they will have slightly different bit times. The decoding procedure described below tolerates a difference of up to a few per cent in the bit times. For optimum kilmunity to signal distortion, noise and clock inaccuracies, the receiver should sample each incoming bit in the middle of its bit time. This can be accomplished by the following procedure which samples the input signal at a frequency that is m times the bit rate (typical values of m are 8, 16, 32 and 64): I
Start bit detection Sample the input for a space. After the first detection of a space, be sure that the input remains in the space state for (m/2)-1 more sample times. If successful, we are now approximately at the middle of the start bit. Otherwise, we have detected a noise pulse and we should start again. 2 Data bit sampling After m more sample times after start bit detection, read the first databit from the input. Repeat a total o f n times for n databits and repeat if necessary for the parity bit. Each bit will be sampled approximately in the middle of its bit time. Place the assembled character in a buffer for the processor or terminal to read. 3 Stop bit detection After m more sample times, sample the input for the mark state (stop bit). Repeat if there are two stop bits. If the input is in the space state, set a framing error status flag along with the received character. Set a character received flag for the processor and return to step 1. The leading edge of the start bit signals the beginning of a character and the time of its occurrence provides a timing reference for sampling the databits. The stop bits provide time for clean-up required between characters on older terminals and also provide a degree of error detection. If the line is not in the mark state when a stop bit is expected, a framing error is said to occur. Framing errors occur most often when the receiver erroneously synchronizes on a space bit that is not the real start bit. Proper resynchronization can always be accomplished if the transmitter is idle (sending mark) for one frame or longer. Unfortunately, if synchronization is lost when the transmitter is sending at full speed, in general it will not be regained until an idle frame occurs. When the line is continuously held in the space state for one frame or longer, a break is said to occur. The BREAK key on most keyboards actually holds the line in the space state for as long as the key is depressed. The serial interfaces on most computers have the capability of detecting break as a special condition. Many software systems then treat break as an extra special-function character. However, break must be used cautiously in remote communication links, because most modems automatically disconnect from the telephone line if a break is held too long.
249
SERIAL I/O INTERFACE CIRCUITS
6850 ACIA
I/O Bus
A computer must have a special I/O interface to transmit and receive data on a serial communication link. Many manufacturers of ICs offer a complete asynchronous serial interface packaged as a single LSI circuit, called a universal asynchronous receiver/transmitter (UART), or some similar name.
] /
Internal Bus
CTS
Serial I= Data Out
~
XMT CLK RCV CLK
.~
Serial Data In DCD
lMo m
Motorola 6850 ACIA An example of an LSI serial I/O interface circuit is the Motorola 6850, which Motorola calls an asynchronous communications interface adapter (ACIA). A block diagram of the ACIA is shown in Figure 5. On one side, the ACIA can transmit data and receive data on an asynchronous full-duplex serial link at speeds up to 19.2 kbit/s or more. On the other side, the ACIA communicates with a CPU by means of two 8-bit input ports and two 8-bit output ports. The I/O programming model of the ACIA is shown in Figure 6. In a typical system configuration the STATUS input port and the CONTROL output port have the same address or port number (e.g. OFCF4H for the console ACIA in the Motorola EXORcisor II development system for the 6809). Likewise, the RCV DATA input port and the XMT DATA output port have the same port number, usually one greater than the STATUS/CONTROL port number (e.g. OFCFSH). Although other configurations are possible, the 6850's I/O bus signals are arranged so that the above configuration is the most convenient. (A sample I/O program for a Motorola 6809 system that uses the 6850 ACIA will given later. The program will use ACIA features that are described in the following subsections.)
Figure 5. Block diagram of the A CIA 654321
I
I
0
I
I c°NTR°'lw I
250
+1 +16 +64 Master Reset
t000 001 010 011 100 101 110 111
7 7 7 7 8 8 8 8
data data data data data data data data
bits, bits, bits, bits, bits, bits, bits, bits,
2 2 1 1 2 1 1 1
stop stop stop stop stop stop stop stop
bits, even parity bits, odd parity bit, even parity bit, odd parity bits, no parity bit, no parity bit, even parity bit, odd parity
001 RTS active, XMT interrupt disabled RTS active, XMT interrupt enabled 0 RTS inactive, XMT interrupt disabled 1 RTS active, XMT interrupt disabled, sending BREAK
LI
10 RCV interrupt disabled RCV interrupt enabled 76543210
IIIIIIII
Ill'
I sr,'rusc~l Receiver Ready Transmitter Ready DCD Inactive CTS Inactive Framing Error Overrun Error Parity Error Interrupt Request
Control Port In order to use the ACIA to send and receive serial data, a program must first set up the operating mode of the ACIA. Sending a byte of 03H to the ACIA CONTROL port resets the ACIA, clearing out-any previous operating mode and disabling the ACIA from sending or receiving data until a new mode is established. The new mode is established by sending an appropriate bit pattern to CONTROL, as detailed in Figure 6 and explained below. The transmitting and receiving bit rates of the ACIA are established by a combination of external clock inputs (XMT CLK and RCV CLK in Figure 5) and a programmable divider ratio. The ACIA transmits serial data at a bit rate equal to the incoming XMT CLK frequency divided by one, 16 or 64, according to the bit pattern loaded into bits 1 - 0 of CONTROL. On receiving, the ACIA uses the bit-sampling procedure described in the previous section. Here the sampling rate is equal to the RCV CLK frequency and the number of samples per bit equals 1,16 or 64 as determined by bits 1 - 0 of CONTROL. The same divider ratio is used for transmitting and receiving. In most systems, only divider ratios of 16 and 64 are useful for receiving. Usually the XMT CLK and RCV CLK inputs are both connected to the same clock source. For example, suppose they are both connected to a 153.6 kHz clock. Then a
~00 01 10 11
7 [
0 ]XMT DATA (W)
7 [
0 ]RCV DATA (R)
Figure 6. I/0 programming model of the A CIA. In this system, STATUS input ports and CONTROL output ports have the same address numbers programmed divider ratio of 16 would allow the ACIA to transmit and receive at 9600 bit/s, while a ratio of 64 would allow it to operate at 2400 bit/s. To operate the ACIA at a different bit rate, the user would have to modify the hardware to connect the XMT CLK and RCV CLK inputs to a different frequency, for example, 19.2 kHz for 1200 or 300 bit/s (this can be done in many systems by a mechanical switch). The ACIA may be configured to transmit and receive seven or eight databits, an even, odd or no parity bit, and one or two stop bits according to a 3-bit pattern loaded into bits 4 - 2 of CONTROL. The same format is used for both transmitting and receiving. CONTROL port bits 6 - 5 control the ACIA's ability to request an interrupt after
microprocessors and microsystems
transmitting a character; they also turn the ACIA's RTS (request to send) output signal on or off. The ACIA will place an interrupt request on its 1RQ output if the transmitter interrupt is enabled and the transmitter is ready to accept another character for transmission. The RTS signal is discussed later. Setting bit 7 of CONTROL allows the ACIA to place an interrupt request on its I RQ output when the receiver has received a character and is ready for a program to read it from RCV DATA. The IRQ output of the ACIA may be connected to an interrupt input of the CPU, typically to the IRQ input in 6809 systems. If both transmitter and receiver interrupts are enabled, then it is up to the interrupt service routine to figure out which section of the ACIA caused the interrupt request to be made. Once the ACIA operating mode is established, it remains the same as long as the ACIA is not reset by sending CONTROL a pattern of 03H. Thus, the operating mode needs to be set up only at the beginning of a sequence of I/O operations; there is no need to reestablish the mode before each operation. The CONTROL port is write only; attempts to read from it do not return the last value written into it. Instead, they return the current value of the STATUS port, described later.
Transmitter data port Once the ACIA operating mode has been established, the CPU may transmit characters to the serial datalink through the ACIA's XMT DATA output port. A new output operation is begun each time the CPU writes a character into XMT DATA. As shown in Figure 5, the transmitted data is double-buffered. Initially, after the ACIA is reset, both XMT DATA and XMT SR are empty. When the CPU writes the first transmitted character into XMT DATA, the ACIA immediately transfers the contents of XMT DATA into XMT SR, a shift register from which the character is shifted into the serial output line with the prescribed format and speed. Since XMT DATA is now empty, the CPU may immediately place a second character into XMT DATA. However, the ACIA will not transfer this second character into XMT SR until the first character has been fully transmitted, a format and speed dependent wait. In general, the CPU can determine when XMT DATA is empty only by checking the Transmitter Ready bit in the STATUS port.
Receiver data port Once the ACIA operating mode has been established in CONTROL, the ACIA immediately starts receiving input characters in the prescribed format. Like transmitted data, received data is double-buffered. Incoming serial data is assembled and its format is checked in the RCV SR shift register. Once a complete character has been assembled, it is transferred into RCV DATA, where the processor may read it at its leisure. In the meantime, RCV SR is available to assemble another incoming character. An 'overrun' error occurs only if the processor fails to read the character presently in RCV DATA before a second character is completely assembled in RCV SR.
vol 5 no 6july/august 1981
In general, the CPU can determine that a new character is present in RCV DATA by checking the Receiver Ready bit in STATUS. The ACIA sets Receiver Ready each time a new character appears in RCV DATA, and clears it each time the CPU reads RCV DATA.
Status port Input/output programs can test the bits in the ACIA's STATUS port to determine if operations have been completed and if any errors have occurred. Bit 1 of STATUS is the Transmitter Ready bit. The ACIA sets this bit on reset and whenever XMT DATA is empty, indicating that the CPU may write XMT DATA with a character for the ACIA to transmit. The ACIA clears this bit when the CPU writes a new character into XMT DATA. (The bit is also forced to 0 if the CTS is inactive. The CTS and DCD modem control inputs and status bits are discussed later.) Likewise, bit 0 indicates Receiver Ready when set; RCV DATA now contains a new character that a program may read. This bit is cleared on reset and whenever the CPU reads RCV DATA. (The bit is also forced to 0 if the DCD input is inactive.) Three possible receiving errors are indicated by bits 4 - 6 of STATUS. The Framing Error bit is set if a received character does not have the proper number of stop bits (i.e. if a space is detected in the serial input during the stop-bit time). Parity Error is set if the received serial input does not have the proper parity. Both of these bits are updated each time the ACIA puts a new received character into RCV DATA. An Overrun Error is set if one or more additional characters are received before the CPU reads the character presently in RCV DATA. This bit is cleared each time the CPU reads RCV DATA. Bit 7 of STATUS is 1 if either the transmitter section or the receiver section of the ACIA has placed an interrupt request on the IRQ output. An interrupt request is made if the transmitter or receiver interrupt has been enabled and the corresponding Ready bit in STATUS is 1. (An interrupt request is also made if an active-to-inactive transition is detected on DCD.)
Modem control lines In addition to the serial data input and output lines, the ACIA has three modem control lines that may be used to indicate or detect certain conditions when the ACIA is connected to a modem. The RTS (request to send) output from the ACIA to the modem is intended to indicate that the ACIA would like to send characters to the modem. If the modem has established a connection to another modem and it is in a state in which it can transmit characters, it responds to RTS by activating the CTS (clear to send) ACIA input signal. The ACIA will not set the Transmitter Ready bit in STATUS while the CTS input signal is inactive. Thus, RTS and CTS form a handshake by which a modem or other device can prevent the ACIA from sending characters until it is ready for them. For example, the modem can prevent data transmission until a valid telephone connection has been established. The CTS bit in STATUS equals 1 whenever the CTS input signal is inactive.
251
The DCD (data carrier detect) ACIA input signal is intended to be connected to a modem output signal that indicates that the modem has detected the presence of another modem capable of transmitting to it from the far end. The DCD bit in STATUS is set to 1 whenever the DCD input signal changes from active to inactive. This event causes an interrupt request to be placed on the ACIA's IRQ output. The DCD status bit is not cleared until the CPU reads STATUS and RCV DATA or resets the ACIA. This convention is useful in telephone links in which a program would like to detect a loss of the received signal, for example, if the far-end party hangs up. When the ACIA conned directly to a terminal without going through a modem, the dispositions of the modem control leads are system dependent. Quite often the CTS and DCD ACIA inputs are connected to be always active and the RTS output is unused. Many inexpensive printers and other devices may accept data at speeds as high as 19.2 kbit/s (approximately 2000 character/s), even though they can only physically process much lower data rates, say 100 characters pre second. Such a printer accepts data at the higher speed and places it in an internal buffer until the buffer becomes full. Then it uses an output signal to indicate that its input buffer is full. By connecting this signal to CTS, the user can automatically prevent the ACIA from transmitting additional characters until some of the previous characters have been physically printed and there is once again room in the buffer.
•
Define addresses SFCF4 BOU SFCF4 EOU SFCF5 EQU spur5 E0U $11
of ACIA I/O ports (system dependent).
CONTROL EOU STATUS XNTDATA RCgDATA ACIAMOD •
$11
(hex) =
Control output port (wrlte-only). Status input port (read-only). Transmitter data output (write-only). Receiver data input (read-only). ACIA operating mode (for CONTHOL). O O O 1000
" receiver interrupt • *
off ....
• •
ACIA initialization at system start*up,
(binary)
)
'
~
I
divide by 16 clock 8 data bits, 2 stop bits, no parity
transmitter interrupt off, . . . . . . . RTS a c t i v e
I
I
routine. This subroutine must be called before calling CURIN or CHBOUT.
CH~INIT LDA ~$03 Reset the ACIA. STA CONTROL LDA #ACIANOD Set up ACIA operating mode. STA CONTROL ~TS All set, return. @ @ Character input routine. After this subroutine is called, @ it returns with an input character in the A register. The @ Z bit in t h e CPU's condition code register (CC) w i l l be 0 @ If any errors occurred, otherwise Z will be I. @ C~PRIN
LDA ANDA DEO LDA ANDA PSHS LDA PUI~ RTS
STATUS #$01
CHRIR STATUS ~70
CC RCVDATA CC
Get current status. Clear all bits except receiver ready. Busy-wait until receiver ready = I. Got a character, get status again. Clear Z if bit 4, 5, or 6 is t, else set Z. Save CC register (including Z) on stack. Get input character, put in A. Pop CC from stack (restores Z). Done, character in A, status in Z.
Character output routine. This subroutine is called with a character in the A register. After waiting for any previous transmission to be completed, it prints the character in A. m CHROUT CWROTI
P~US LUA ANDA BEO PULS STA
RTS
A STATUS #SO2 ~'~OT1 A XMTDATA
Save character to be printed on stack. Get current status. Clear a l l bits except transmitter ready. Busy-watt until transmitter ready R e s t o r e character from stack. Print It. Done, return.
Figure 7. Character input and output subroutines
252
= 1.
SAMPLE PROGRAM The simplest applications of the ACIA do not use interrupts and do not use the ACIA's modem control lines. Such an application, a set of subroutines for performing input and output of characters, is shown in Figure 7. The CHRINIT subroutine must be called before any other, since it resets the ACIA and sets the proper operating mode. The programmer may modify the ACIA's operating mode by changing the definition of the ACIAMOD constant. In the present example a divide-by-16 clock is selected, and so the ACIA will transmit and receive at a bit rate one-sixteenth of the external transmit and receive clock frequencies. For example, if both external clock frequencies are 19.2 kHz, then the ACIA will transmit and receive at 1200 bit/s. The ACIA could also be initialized with a divide-by-64 clock ratio (ACIAMOD EQU $12) in order to transmit and receive at 300 bit/s. A divide-by-1 clock ratio (ACIAMOD EQU $10) could be used to transmit at 19.2 kbit/s, but receiver synchronization with a divide-by-1 clock is not possible. The CHRIN subroutine waits until a Character is received by the ACIA, and returns it in the A register to the calling program. If a framing or overrun error is detected, the subroutine clears the 6809% Z condition bit; the calling program may then check this bit to determine whether an error occurred. Note that a parity error is impossible since the ACIA was set up to ignore parity. The CHROUT subroutine prints a character that is passed to it in the A register. If a previous output operation has not yet completed, it waits before printing the character. This is an example of overlapped I/O. Control is returned to the calling program as soon as CHROUT hands over the character to the ACIA, even though the serial transmission is far from completion. In this way, the serial transmission is overlapped with the calling program's generation of the next character, and busy-waiting in CHROUT occurs only if the main program generates characters faster than they can be serially transmitted. APPENDIX: THE ASCII CHARACTER ASCII
CODE
encoding
The most commonly used character encoding in computers is ASCII (pronounced ass-key), shown in Table 1. The code contains the uppercase and lowercase alphabet, numerals, punctuation and various nonprinting control characters that are sometimes used in serial communications links. ASCIi is a 7-bit code, so its characters are stored one per byte in most computers. The MSB of an ASCII byte is usually unused and set to zero. However, ASCii bytes received from a serial communication link may use the MSB as a parity bit or may have the MSB set to some arbitrary value. Therefore it is wise for a program to clear the MSB of a received ASCII byte before comparing it with other ASCII bytes. Notice that the numeric and alphabetic codes are ordered, so that character sequences may be sorted lexicographically using numeric comparisons of the corresponding character codes. Also, there is a simple relationship between upper and lowercase, so that lower may be converted to upper by subtracting 0100000.
microprocessors and microsystems
Table 1 American standard code for information interchange (ASCII), Standard No. X3.4-1968 of the American National Standards Institute a
b3b2blbo 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
row (hex)
b6bsb4 (column)
0 I 2 3 4 5 6 7 8 9 A B C D E
000 0 NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO
001 1 DLE DCI DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS
010 2 SP '
011 3 0 I
100 4 @ A
101 5 P Q
a
"
2
B
R
b
r
# $ % & ' ( ) * + ,
3 4 5 6 7 8 9 : ; < = >
C D E F G H I
S T U V W X Y
c d e f g h i
s t u v w x y
J
Z
j
z
K L M N
[
k I m n
{
F
Sl
US
/
~
0
o
DEL
b Control codes NUL Null SOH Start of heading STX Start of text ETX End of text EOT End of transmission ENQ Enquiry ACK Acknowledge BEL Bell BS Backspace HT Horizontal tab LF Line feed VT Vertical tab FF Form feed CR Carriage return SO Shift out SI Shift in SP Space
DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US DEL
Data link escape Device control 1 Device control 2 Device control 3 Device control 4 Negative acknowledge Synchronize End transmitted block Cancel End of medium Substitute Escape File separator Group separator Record separator Unit separator Delete or rubout
A S C I I and terminals A few words should be said about the relationship between the ASCII characters and the keyboards and screens of typical terminals. Typically each key transmits one of three or four possible ASCII codes, depending on whether or not the SHIFT and CTRL keys on the keyboard are depressed at the same time as the key. Thus, typing L by itself transmits a lowercase L, binary code 1101100. Holding down SHIFT and typing L transmits an uppercase L, binary code 1001100. Holding down CTRL and typing L transmits binary code 0001 I00, regardless of the position of the SHIFT key on most keyboards. In general, a control code in column 0 or I of Figure 7 is obtained by holding down the CTRL key and typing the character from the same relative position in column 4 or 5. Thus, holding down CTRL and typing C (i.e. typing C T R L - C ) transmits the binary code 0000011,
vol 5 no 6july/august 1981
] -
110 6
111 7 p q
}
the ASCII control code named ETX. Many computer systems use these control codes as special system commands, for example, C T R L - C to return control to an executive, C T R L - 0 to suspend the current output, C T R L - U to cancel the current input line and so on. Note that the ESC key found on most terminals sends a particular ASCII code (0011011), while the CTRL key performs a mapping on other key codes as described above. The BREAK key places an abnormal condition on the serial data link, as described in the accompanying article. In some systems this abnormal condition is detected and used as another system command, but it is not an ASCII character. A typical CRT screen ignores most control codes that it receives, but there are five control codes to which all screens respond: • SP • BS
prints a blank space moves the cursor (current printing position) one space left • CR moves the cursor to the beginning of the current line (some terminals are configured to also move the cursor to the next line when CR is received) • LF moves the cursor down one line (some terminals are configured to also move the cursor to the beginning of the line when LF is received) • BEL produces an audible sound (usually a beep) at the terminal Some smart CRT screens respond to special escape sequences, typically consisting of an ESC character followed by one or more additional characters. For example, a terminal might respond to ESC H by homing the cursor (moving it to the upper left-hand corner of the screen), and to ESC J by clearing all of the text from the current cursor position to the end of the screen. Different escape sequences are defined for different smart terminals.
253
Computer
Serial data/inks are most commonly used by computers to communicate with both local and remote terminals. In this artic.le, the simple serial datalinks that are most often used are described. Serial communication means that information transmitted from source to destination is carried over a single pathway. Within the immediate physical confines of a computer system, the use of serial links is most often motivated by cost considerations - serial links can reduce packaging and cabling cost and reduce the number and complexity of components for sending and receiving data. Outside the computer system, use of a serial communication link is often forced by the very nature of the available data transmission media - telephone lines and radio waves can only send one analogue signal at a time.
CRT Terminal
/
cP°l .I ,"~'~'>']~;:1 •echo
I
OutpUtport
]
Serial Link
'
~'~,,._ _ I ~
InpUtport
Serial Link
Figure 1. Full~luplex operation. Transmission is independent and simultaneous in both directions Computer
CRT Terminal
Serial Link
TYPES OF SERIAL DATALINKS A simplex serial datalink transmits data in only one direction. (A connection from a computer to a remote printer could be a simplex serial datalink.) In most applications, there are two serial datalinks between a computer and a terminal, one for transmission in each direction. This is called full-duplex operation and is illustrated in Figure 1. Transmission in the two directions in independent and simultaneous. A typical terminal consists of a keyboard and a screen or hardcopy printer. Even though they may be packaged together, the keyboard and screen are logically independent devices. When a character is typed at the keyboard, it is not automatically printed. In most full-duplex systems, the computer must receive each character and echo it back to the terminal. A few full-duplex systems have terminals hard-wired to locally print all typed characters, saving the computer the overhead of echoing them. This mode of operation is sometimes calledecho-plex. (The 'half-duplex' option on most modern terminals is really echo-plex.) Bidirectional communication can also be achieved with a single link as shown in Figure 2, but only in one direction at a time. A special control sequence is needed to 'turn the line around' whenever the direction of transmission is changed. This is called half-duplex operation.
Computer Systems Laboratory, Stanford University, Stanford CA 94305, USA This article is adapted from Appendices A and C of Wakerly, J F Microcomputer architecture and programming John Wiley (1981 )
vo15 no 6july/august 1981
Figure 2. Half-duplex operation. Transmission is bidirectional, but only in one direction at a time Local printing of typed characters is essential with halfduplex links because of the high overhead that would be incurred if the computer had to turn the line around to echo each character. Because of decreased costs and increased capabilities, most serial links in use today are full-duplex. The rate of transmission of a data stream in bit/s is called the bit rate. This rate is sometimes mistakenly called the 'baud rate'. The bit rate and the baud rate are often equal, but not always; the exact definition of baud rate must wait until we discuss modems. Serial transmission rates for typical computer terminals range from 75 to 19 200 bit/s. The reciprocal of the bit rate is called the bit time-the time that it takes to transmit one bit. By far the most common character encoding in minicomputer and microcomputer systems is ASCI I, which represents each character by 7 bits (see Appendix). A character is transmitted over the link one bit at a time, with two to four control bits added to each character. Thus nine to 11 bits are required to transmit one character and the typical bit transmission rates mentioned above yield about eight to 2000 character/s. A typical 24 x 80 CRT screen contains 1920 characters, so it can be completely filled in one second by a 19.2 kbit/s datalink.
0141-9331/81/060247-07 $02.00 © 1981 IPC Business Press
247
Standard bit rates are 75, 1 I0, 134.5,150, 300,600, 1200, 2400, 4800, 9600 and 19 200 bit/s. The standard bit rates form a geometric progression, except for 110 bit/s, used by old fashioned ASR-33 teleprinters and similar equipment, and 134.5 bit/s, used by some IBM printing terminals. Modern CRT terminals have switch-selectable bit rates up to a maximum of 9.6 or 19.2 kbit/s. Most often the same bit rate is used for both directions in a full-duplex serial communication link. This is especially true in communications between a computer and a local terminal, since data is carried over relatively inexpensive short high-bandwidth copper wires. On the other hand, there is nothing to prevent different bit rates from being used in a 'split bit rate' arrangement. This is advantageous for connections to remote equipment by telephone lines or other expensive links with limited bandwidth. A human can type only so fast, even with a repeat key, and so a bit rate supporting more than 15 characters per second from a keyboard to the computer is wasteful. On the other hand, a computer can easily send data to a CRT continuously at rates of 100 characters per second or higher. Therefore, one popular split bit rate arrangement uses a 150 bit/s link from terminal to computer, but 1200 bit/s from computer to terminal. A simple serial communication link uses the signals mark and space to encode the binary digits 1 and 0, respectively. The names mark and space, taken from telegraphy, remind us that the physical values used to represent Is and Os depend on the type of physical link. In fact, each bit has several representations during its journey from source to destination, as shown by the example in Figure 3. Within a computer, I s and Os of a character are represented by a sequence of standard voltage levels for a particular logic family, say transistor-transistor logic (TTL). An interface in the computer converts TTL levels to another standard set of voltage levels prescribed by EIA (Electronic Industries Association) standard RS-232 and connects to a device called a modem. A standard telephone link cannot transmit and receive absolute voltage levels, only sounds whose frequency components are between approximately 300 and 3000 Hz. Therefore the modem converts RS-232 voltage levels into tones that can be transmitted over a telephone line. For example, the modem could transmit a 1270 Hz tone whenever an RS-232 mark level is present, and 1070 Hz for an RS-232 space level. This modulation scheme is
Computer (1.o)
(2,,. o., v,;
(-3 v. +3 v)- I
Telephone LinHz)[ e (1270 HZ,1070 [Teleprinter[( (~orrm~:L°: p) ~
(E_I;vRS'23~)~~
Figure 3. Each bit has several representations during its journey from source to destination
248
1
called frequency-shift keying (FSK). Another modem at the receiving end can detect FSK tones and convert them back into RS-232 levels. In Figure 3, the RS-232 levels at the receiving end are converted to a current-loop interface - a pair of wires in which a 20 mA current represents a mark and 0 mA represents a space. The resulting sequence of on/off currents controls the motion of a teleprinter's mechanical wheels and cams that finally print a character. Alternatively, the RS-232 levels could be connected to a typical CRT terminal which is designed to accept RS-232 levels directly. Most serial communication links are full-duplex, so that Figure 3 should really show another serial link in the reverse direction. However, another telephone line and pair of modems usually is not required for the reverse link. Most modems can provide a full-duplex link using a single telephone line. They do this by using a different pair of frequencies for communicating in the reverse direction, for example, 2225 Hz for a mark and 2025 Hz for a space. The choice of transmitting and receiving frequencies for the computer and terminal is predetermined by convention in any given system. The modem handles the links in both directions simultaneously (the name modem stands for modulator/demodulator). The bit rate that can be reliably transmitted and received by a particular modem is limited. For example, suppose we tried to send data at 9600 bit/s using the FSK modulation scheme described above. Then one bit time would correspond to only about one-eighth of a sine wave period at a transmitting frequency of 1270 Hz. Such a tiny slice of a sine wave cannot be reliably detected at the receiving end after passing through the distortions of the telephone network. Modulation and demodulation schemes more sophisticated than FSK are used in high bit-rate modems. It may seem paradoxical that it is indeed possible to send 9600 bit/s over a telephone link that has a bandwidth of only about 3000 Hz. Such high bit rates are achieved by modulation techniques in which each transmitted signal element has more than two values. For example, some 1200 bit/s modems use a modulation scheme that transmits only 600 signal element/s, where each signal element can have one of four values, representing the four possible combinations of two bits. The number of signal elements per second is called the baud rate. In low-speed modems the bit rate and baud rate are usually equal; in high-speed modems they usually are not. Inexpensive low-speed modems transmit and receive data at 3 0 0 - I 200 bit/s. When a terminal is connected directly to a computer without using a telephone link and modems, it is usually practical to use a much higher bit rate such as 9.6 or 29.2 kbit/s.
ASYCHRONOUS SER IAL COMMUNICATION FORMAT The majority of serial communication links now in use are asynchronous links. Asynchronous means that the transmitter and receiver do not share a common clock, and no clock signal is sent with the data. So how does the receiver
microprocessors and microsystems
Mark
start bit
idle
data bit 0
data bit 1
data parity stop bit n*l bit bit 1
I I I I
Space
i
...
stop bit 2
start bit
I
i
I
t
frame
q 1,~
(e) start bit
idle
1
0
1
0
1
1
0
odd parity stop bit bit 1
stop bit 2
idle
Mark
Space
I
I
I
I
I
I
T
(b)
start bit
idle
I
0
I
0
I
1
0
I
1
I
0
I
1
odd parity stop bit bit
I
idle
I
(c)
Figure 4a. Standard asynchronous serial bit format, 4b. bit format for operation o f an aM fashioned teleprinter at 110 bit/s, 4c. bit format for operation at a more usual rate o f 300 bit/s know.when the databits begin and end? We shall describe a simple algorithm that can be used if the transmitter and receiver agree on a standard bit rate and format. The standard asynchronous serial bit format used by computers and terminals is shown in Figure 4a. When the transmitter is idle (i.e. no data being sent), the line is maintained in a continuous mark state. The transmitter may initiate a character at any time by sending a start bit, that is, by putting the line in the space state for exactly one bit time. It then transmits the databits, least significant first, optionally followed by an even or odd parity bit. (An even parity bit is chosen so that the total number of Is among the databits and parity bit is even.) Finally, the transmitter maintains the mark state for I, 1.5 or 2 bit times - so-called stop bits. The period of time from the beginning of the start bit to the end of the stop bits is called a frame. After the stop bits, the transmitter may immediately send a new start bit if it has another character to send. Otherwise, it may maintain the mark state as long as it is idle. A new start bit may be sent at any time, not necessarily an integral number of bit times since the last stop bit. An old fashioned teleprinter operating at 110 bit/s transmits a start bit, seven ASCII data bits, an odd parity bit and two stop bits, as shown in Figure 4b for the character 0110101 (ASCII '5'). Since 11 bits are required to send each character, at 1 I0 bit/s there are I0 character/s. Terminals operating at 300 bit/s and higher usually transmit a start bit, seven ASCII data bits, a parity bit and one stop bit, as shown in Figure 4c for the character 1010100 (ASCII 'T'). Since only I 0 bits are needed for each character, at 300 bit/s there are 30 character/s. The usage of the parity bit varies widely among different systems. There are three possibilities: even, odd or no parity. These possibilities are compounded by the fact that most terminals and computers can send and receive an optional eighth databit before the optional parity bit. There are four possibilities for the eighth bit: not transmitted, constant I, constant 0 or useful data. The last case creates an additional 128 non-ASCII characters that may be
vol 5 no 6july~august 1981
transmitted between the terminal and computer for extended character sets or special functions. In a serial communication link, the transmitter and receiver must agree upon all of the parameters of the bit format in Figure 4a, including a nominal bit time (or equivalently, bit rate). Since transmitter and receiver have different clocks, they will have slightly different bit times. The decoding procedure described below tolerates a difference of up to a few per cent in the bit times. For optimum kilmunity to signal distortion, noise and clock inaccuracies, the receiver should sample each incoming bit in the middle of its bit time. This can be accomplished by the following procedure which samples the input signal at a frequency that is m times the bit rate (typical values of m are 8, 16, 32 and 64): I
Start bit detection Sample the input for a space. After the first detection of a space, be sure that the input remains in the space state for (m/2)-1 more sample times. If successful, we are now approximately at the middle of the start bit. Otherwise, we have detected a noise pulse and we should start again. 2 Data bit sampling After m more sample times after start bit detection, read the first databit from the input. Repeat a total o f n times for n databits and repeat if necessary for the parity bit. Each bit will be sampled approximately in the middle of its bit time. Place the assembled character in a buffer for the processor or terminal to read. 3 Stop bit detection After m more sample times, sample the input for the mark state (stop bit). Repeat if there are two stop bits. If the input is in the space state, set a framing error status flag along with the received character. Set a character received flag for the processor and return to step 1. The leading edge of the start bit signals the beginning of a character and the time of its occurrence provides a timing reference for sampling the databits. The stop bits provide time for clean-up required between characters on older terminals and also provide a degree of error detection. If the line is not in the mark state when a stop bit is expected, a framing error is said to occur. Framing errors occur most often when the receiver erroneously synchronizes on a space bit that is not the real start bit. Proper resynchronization can always be accomplished if the transmitter is idle (sending mark) for one frame or longer. Unfortunately, if synchronization is lost when the transmitter is sending at full speed, in general it will not be regained until an idle frame occurs. When the line is continuously held in the space state for one frame or longer, a break is said to occur. The BREAK key on most keyboards actually holds the line in the space state for as long as the key is depressed. The serial interfaces on most computers have the capability of detecting break as a special condition. Many software systems then treat break as an extra special-function character. However, break must be used cautiously in remote communication links, because most modems automatically disconnect from the telephone line if a break is held too long.
249
SERIAL I/O INTERFACE CIRCUITS
6850 ACIA
I/O Bus
A computer must have a special I/O interface to transmit and receive data on a serial communication link. Many manufacturers of ICs offer a complete asynchronous serial interface packaged as a single LSI circuit, called a universal asynchronous receiver/transmitter (UART), or some similar name.
] /
Internal Bus
CTS
Serial I= Data Out
~
XMT CLK RCV CLK
.~
Serial Data In DCD
lMo m
Motorola 6850 ACIA An example of an LSI serial I/O interface circuit is the Motorola 6850, which Motorola calls an asynchronous communications interface adapter (ACIA). A block diagram of the ACIA is shown in Figure 5. On one side, the ACIA can transmit data and receive data on an asynchronous full-duplex serial link at speeds up to 19.2 kbit/s or more. On the other side, the ACIA communicates with a CPU by means of two 8-bit input ports and two 8-bit output ports. The I/O programming model of the ACIA is shown in Figure 6. In a typical system configuration the STATUS input port and the CONTROL output port have the same address or port number (e.g. OFCF4H for the console ACIA in the Motorola EXORcisor II development system for the 6809). Likewise, the RCV DATA input port and the XMT DATA output port have the same port number, usually one greater than the STATUS/CONTROL port number (e.g. OFCFSH). Although other configurations are possible, the 6850's I/O bus signals are arranged so that the above configuration is the most convenient. (A sample I/O program for a Motorola 6809 system that uses the 6850 ACIA will given later. The program will use ACIA features that are described in the following subsections.)
Figure 5. Block diagram of the A CIA 654321
I
I
0
I
I c°NTR°'lw I
250
+1 +16 +64 Master Reset
t000 001 010 011 100 101 110 111
7 7 7 7 8 8 8 8
data data data data data data data data
bits, bits, bits, bits, bits, bits, bits, bits,
2 2 1 1 2 1 1 1
stop stop stop stop stop stop stop stop
bits, even parity bits, odd parity bit, even parity bit, odd parity bits, no parity bit, no parity bit, even parity bit, odd parity
001 RTS active, XMT interrupt disabled RTS active, XMT interrupt enabled 0 RTS inactive, XMT interrupt disabled 1 RTS active, XMT interrupt disabled, sending BREAK
LI
10 RCV interrupt disabled RCV interrupt enabled 76543210
IIIIIIII
Ill'
I sr,'rusc~l Receiver Ready Transmitter Ready DCD Inactive CTS Inactive Framing Error Overrun Error Parity Error Interrupt Request
Control Port In order to use the ACIA to send and receive serial data, a program must first set up the operating mode of the ACIA. Sending a byte of 03H to the ACIA CONTROL port resets the ACIA, clearing out-any previous operating mode and disabling the ACIA from sending or receiving data until a new mode is established. The new mode is established by sending an appropriate bit pattern to CONTROL, as detailed in Figure 6 and explained below. The transmitting and receiving bit rates of the ACIA are established by a combination of external clock inputs (XMT CLK and RCV CLK in Figure 5) and a programmable divider ratio. The ACIA transmits serial data at a bit rate equal to the incoming XMT CLK frequency divided by one, 16 or 64, according to the bit pattern loaded into bits 1 - 0 of CONTROL. On receiving, the ACIA uses the bit-sampling procedure described in the previous section. Here the sampling rate is equal to the RCV CLK frequency and the number of samples per bit equals 1,16 or 64 as determined by bits 1 - 0 of CONTROL. The same divider ratio is used for transmitting and receiving. In most systems, only divider ratios of 16 and 64 are useful for receiving. Usually the XMT CLK and RCV CLK inputs are both connected to the same clock source. For example, suppose they are both connected to a 153.6 kHz clock. Then a
~00 01 10 11
7 [
0 ]XMT DATA (W)
7 [
0 ]RCV DATA (R)
Figure 6. I/0 programming model of the A CIA. In this system, STATUS input ports and CONTROL output ports have the same address numbers programmed divider ratio of 16 would allow the ACIA to transmit and receive at 9600 bit/s, while a ratio of 64 would allow it to operate at 2400 bit/s. To operate the ACIA at a different bit rate, the user would have to modify the hardware to connect the XMT CLK and RCV CLK inputs to a different frequency, for example, 19.2 kHz for 1200 or 300 bit/s (this can be done in many systems by a mechanical switch). The ACIA may be configured to transmit and receive seven or eight databits, an even, odd or no parity bit, and one or two stop bits according to a 3-bit pattern loaded into bits 4 - 2 of CONTROL. The same format is used for both transmitting and receiving. CONTROL port bits 6 - 5 control the ACIA's ability to request an interrupt after
microprocessors and microsystems
transmitting a character; they also turn the ACIA's RTS (request to send) output signal on or off. The ACIA will place an interrupt request on its 1RQ output if the transmitter interrupt is enabled and the transmitter is ready to accept another character for transmission. The RTS signal is discussed later. Setting bit 7 of CONTROL allows the ACIA to place an interrupt request on its I RQ output when the receiver has received a character and is ready for a program to read it from RCV DATA. The IRQ output of the ACIA may be connected to an interrupt input of the CPU, typically to the IRQ input in 6809 systems. If both transmitter and receiver interrupts are enabled, then it is up to the interrupt service routine to figure out which section of the ACIA caused the interrupt request to be made. Once the ACIA operating mode is established, it remains the same as long as the ACIA is not reset by sending CONTROL a pattern of 03H. Thus, the operating mode needs to be set up only at the beginning of a sequence of I/O operations; there is no need to reestablish the mode before each operation. The CONTROL port is write only; attempts to read from it do not return the last value written into it. Instead, they return the current value of the STATUS port, described later.
Transmitter data port Once the ACIA operating mode has been established, the CPU may transmit characters to the serial datalink through the ACIA's XMT DATA output port. A new output operation is begun each time the CPU writes a character into XMT DATA. As shown in Figure 5, the transmitted data is double-buffered. Initially, after the ACIA is reset, both XMT DATA and XMT SR are empty. When the CPU writes the first transmitted character into XMT DATA, the ACIA immediately transfers the contents of XMT DATA into XMT SR, a shift register from which the character is shifted into the serial output line with the prescribed format and speed. Since XMT DATA is now empty, the CPU may immediately place a second character into XMT DATA. However, the ACIA will not transfer this second character into XMT SR until the first character has been fully transmitted, a format and speed dependent wait. In general, the CPU can determine when XMT DATA is empty only by checking the Transmitter Ready bit in the STATUS port.
Receiver data port Once the ACIA operating mode has been established in CONTROL, the ACIA immediately starts receiving input characters in the prescribed format. Like transmitted data, received data is double-buffered. Incoming serial data is assembled and its format is checked in the RCV SR shift register. Once a complete character has been assembled, it is transferred into RCV DATA, where the processor may read it at its leisure. In the meantime, RCV SR is available to assemble another incoming character. An 'overrun' error occurs only if the processor fails to read the character presently in RCV DATA before a second character is completely assembled in RCV SR.
vol 5 no 6july/august 1981
In general, the CPU can determine that a new character is present in RCV DATA by checking the Receiver Ready bit in STATUS. The ACIA sets Receiver Ready each time a new character appears in RCV DATA, and clears it each time the CPU reads RCV DATA.
Status port Input/output programs can test the bits in the ACIA's STATUS port to determine if operations have been completed and if any errors have occurred. Bit 1 of STATUS is the Transmitter Ready bit. The ACIA sets this bit on reset and whenever XMT DATA is empty, indicating that the CPU may write XMT DATA with a character for the ACIA to transmit. The ACIA clears this bit when the CPU writes a new character into XMT DATA. (The bit is also forced to 0 if the CTS is inactive. The CTS and DCD modem control inputs and status bits are discussed later.) Likewise, bit 0 indicates Receiver Ready when set; RCV DATA now contains a new character that a program may read. This bit is cleared on reset and whenever the CPU reads RCV DATA. (The bit is also forced to 0 if the DCD input is inactive.) Three possible receiving errors are indicated by bits 4 - 6 of STATUS. The Framing Error bit is set if a received character does not have the proper number of stop bits (i.e. if a space is detected in the serial input during the stop-bit time). Parity Error is set if the received serial input does not have the proper parity. Both of these bits are updated each time the ACIA puts a new received character into RCV DATA. An Overrun Error is set if one or more additional characters are received before the CPU reads the character presently in RCV DATA. This bit is cleared each time the CPU reads RCV DATA. Bit 7 of STATUS is 1 if either the transmitter section or the receiver section of the ACIA has placed an interrupt request on the IRQ output. An interrupt request is made if the transmitter or receiver interrupt has been enabled and the corresponding Ready bit in STATUS is 1. (An interrupt request is also made if an active-to-inactive transition is detected on DCD.)
Modem control lines In addition to the serial data input and output lines, the ACIA has three modem control lines that may be used to indicate or detect certain conditions when the ACIA is connected to a modem. The RTS (request to send) output from the ACIA to the modem is intended to indicate that the ACIA would like to send characters to the modem. If the modem has established a connection to another modem and it is in a state in which it can transmit characters, it responds to RTS by activating the CTS (clear to send) ACIA input signal. The ACIA will not set the Transmitter Ready bit in STATUS while the CTS input signal is inactive. Thus, RTS and CTS form a handshake by which a modem or other device can prevent the ACIA from sending characters until it is ready for them. For example, the modem can prevent data transmission until a valid telephone connection has been established. The CTS bit in STATUS equals 1 whenever the CTS input signal is inactive.
251
The DCD (data carrier detect) ACIA input signal is intended to be connected to a modem output signal that indicates that the modem has detected the presence of another modem capable of transmitting to it from the far end. The DCD bit in STATUS is set to 1 whenever the DCD input signal changes from active to inactive. This event causes an interrupt request to be placed on the ACIA's IRQ output. The DCD status bit is not cleared until the CPU reads STATUS and RCV DATA or resets the ACIA. This convention is useful in telephone links in which a program would like to detect a loss of the received signal, for example, if the far-end party hangs up. When the ACIA conned directly to a terminal without going through a modem, the dispositions of the modem control leads are system dependent. Quite often the CTS and DCD ACIA inputs are connected to be always active and the RTS output is unused. Many inexpensive printers and other devices may accept data at speeds as high as 19.2 kbit/s (approximately 2000 character/s), even though they can only physically process much lower data rates, say 100 characters pre second. Such a printer accepts data at the higher speed and places it in an internal buffer until the buffer becomes full. Then it uses an output signal to indicate that its input buffer is full. By connecting this signal to CTS, the user can automatically prevent the ACIA from transmitting additional characters until some of the previous characters have been physically printed and there is once again room in the buffer.
•
Define addresses SFCF4 BOU SFCF4 EOU SFCF5 EQU spur5 E0U $11
of ACIA I/O ports (system dependent).
CONTROL EOU STATUS XNTDATA RCgDATA ACIAMOD •
$11
(hex) =
Control output port (wrlte-only). Status input port (read-only). Transmitter data output (write-only). Receiver data input (read-only). ACIA operating mode (for CONTHOL). O O O 1000
" receiver interrupt • *
off ....
• •
ACIA initialization at system start*up,
(binary)
)
'
~
I
divide by 16 clock 8 data bits, 2 stop bits, no parity
transmitter interrupt off, . . . . . . . RTS a c t i v e
I
I
routine. This subroutine must be called before calling CURIN or CHBOUT.
CH~INIT LDA ~$03 Reset the ACIA. STA CONTROL LDA #ACIANOD Set up ACIA operating mode. STA CONTROL ~TS All set, return. @ @ Character input routine. After this subroutine is called, @ it returns with an input character in the A register. The @ Z bit in t h e CPU's condition code register (CC) w i l l be 0 @ If any errors occurred, otherwise Z will be I. @ C~PRIN
LDA ANDA DEO LDA ANDA PSHS LDA PUI~ RTS
STATUS #$01
CHRIR STATUS ~70
CC RCVDATA CC
Get current status. Clear all bits except receiver ready. Busy-wait until receiver ready = I. Got a character, get status again. Clear Z if bit 4, 5, or 6 is t, else set Z. Save CC register (including Z) on stack. Get input character, put in A. Pop CC from stack (restores Z). Done, character in A, status in Z.
Character output routine. This subroutine is called with a character in the A register. After waiting for any previous transmission to be completed, it prints the character in A. m CHROUT CWROTI
P~US LUA ANDA BEO PULS STA
RTS
A STATUS #SO2 ~'~OT1 A XMTDATA
Save character to be printed on stack. Get current status. Clear a l l bits except transmitter ready. Busy-watt until transmitter ready R e s t o r e character from stack. Print It. Done, return.
Figure 7. Character input and output subroutines
252
= 1.
SAMPLE PROGRAM The simplest applications of the ACIA do not use interrupts and do not use the ACIA's modem control lines. Such an application, a set of subroutines for performing input and output of characters, is shown in Figure 7. The CHRINIT subroutine must be called before any other, since it resets the ACIA and sets the proper operating mode. The programmer may modify the ACIA's operating mode by changing the definition of the ACIAMOD constant. In the present example a divide-by-16 clock is selected, and so the ACIA will transmit and receive at a bit rate one-sixteenth of the external transmit and receive clock frequencies. For example, if both external clock frequencies are 19.2 kHz, then the ACIA will transmit and receive at 1200 bit/s. The ACIA could also be initialized with a divide-by-64 clock ratio (ACIAMOD EQU $12) in order to transmit and receive at 300 bit/s. A divide-by-1 clock ratio (ACIAMOD EQU $10) could be used to transmit at 19.2 kbit/s, but receiver synchronization with a divide-by-1 clock is not possible. The CHRIN subroutine waits until a Character is received by the ACIA, and returns it in the A register to the calling program. If a framing or overrun error is detected, the subroutine clears the 6809% Z condition bit; the calling program may then check this bit to determine whether an error occurred. Note that a parity error is impossible since the ACIA was set up to ignore parity. The CHROUT subroutine prints a character that is passed to it in the A register. If a previous output operation has not yet completed, it waits before printing the character. This is an example of overlapped I/O. Control is returned to the calling program as soon as CHROUT hands over the character to the ACIA, even though the serial transmission is far from completion. In this way, the serial transmission is overlapped with the calling program's generation of the next character, and busy-waiting in CHROUT occurs only if the main program generates characters faster than they can be serially transmitted. APPENDIX: THE ASCII CHARACTER ASCII
CODE
encoding
The most commonly used character encoding in computers is ASCII (pronounced ass-key), shown in Table 1. The code contains the uppercase and lowercase alphabet, numerals, punctuation and various nonprinting control characters that are sometimes used in serial communications links. ASCIi is a 7-bit code, so its characters are stored one per byte in most computers. The MSB of an ASCII byte is usually unused and set to zero. However, ASCii bytes received from a serial communication link may use the MSB as a parity bit or may have the MSB set to some arbitrary value. Therefore it is wise for a program to clear the MSB of a received ASCII byte before comparing it with other ASCII bytes. Notice that the numeric and alphabetic codes are ordered, so that character sequences may be sorted lexicographically using numeric comparisons of the corresponding character codes. Also, there is a simple relationship between upper and lowercase, so that lower may be converted to upper by subtracting 0100000.
microprocessors and microsystems
Table 1 American standard code for information interchange (ASCII), Standard No. X3.4-1968 of the American National Standards Institute a
b3b2blbo 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
row (hex)
b6bsb4 (column)
0 I 2 3 4 5 6 7 8 9 A B C D E
000 0 NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO
001 1 DLE DCI DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS
010 2 SP '
011 3 0 I
100 4 @ A
101 5 P Q
a
"
2
B
R
b
r
# $ % & ' ( ) * + ,
3 4 5 6 7 8 9 : ; < = >
C D E F G H I
S T U V W X Y
c d e f g h i
s t u v w x y
J
Z
j
z
K L M N
[
k I m n
{
F
Sl
US
/
~
0
o
DEL
b Control codes NUL Null SOH Start of heading STX Start of text ETX End of text EOT End of transmission ENQ Enquiry ACK Acknowledge BEL Bell BS Backspace HT Horizontal tab LF Line feed VT Vertical tab FF Form feed CR Carriage return SO Shift out SI Shift in SP Space
DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US DEL
Data link escape Device control 1 Device control 2 Device control 3 Device control 4 Negative acknowledge Synchronize End transmitted block Cancel End of medium Substitute Escape File separator Group separator Record separator Unit separator Delete or rubout
A S C I I and terminals A few words should be said about the relationship between the ASCII characters and the keyboards and screens of typical terminals. Typically each key transmits one of three or four possible ASCII codes, depending on whether or not the SHIFT and CTRL keys on the keyboard are depressed at the same time as the key. Thus, typing L by itself transmits a lowercase L, binary code 1101100. Holding down SHIFT and typing L transmits an uppercase L, binary code 1001100. Holding down CTRL and typing L transmits binary code 0001 I00, regardless of the position of the SHIFT key on most keyboards. In general, a control code in column 0 or I of Figure 7 is obtained by holding down the CTRL key and typing the character from the same relative position in column 4 or 5. Thus, holding down CTRL and typing C (i.e. typing C T R L - C ) transmits the binary code 0000011,
vol 5 no 6july/august 1981
] -
110 6
111 7 p q
}
the ASCII control code named ETX. Many computer systems use these control codes as special system commands, for example, C T R L - C to return control to an executive, C T R L - 0 to suspend the current output, C T R L - U to cancel the current input line and so on. Note that the ESC key found on most terminals sends a particular ASCII code (0011011), while the CTRL key performs a mapping on other key codes as described above. The BREAK key places an abnormal condition on the serial data link, as described in the accompanying article. In some systems this abnormal condition is detected and used as another system command, but it is not an ASCII character. A typical CRT screen ignores most control codes that it receives, but there are five control codes to which all screens respond: • SP • BS
prints a blank space moves the cursor (current printing position) one space left • CR moves the cursor to the beginning of the current line (some terminals are configured to also move the cursor to the next line when CR is received) • LF moves the cursor down one line (some terminals are configured to also move the cursor to the beginning of the line when LF is received) • BEL produces an audible sound (usually a beep) at the terminal Some smart CRT screens respond to special escape sequences, typically consisting of an ESC character followed by one or more additional characters. For example, a terminal might respond to ESC H by homing the cursor (moving it to the upper left-hand corner of the screen), and to ESC J by clearing all of the text from the current cursor position to the end of the screen. Different escape sequences are defined for different smart terminals.
253