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Session F2: System design II
North-Holland
Microprocessingand Microprogramming30 (1990)535-536
Session F2:
535
System Design II Chairman: K. Klockner Gesellschaft fur Mathematik und Datenverarbeitung St. Augustin Germany
Things have changed a lot in formal specification... Ten years ago, circuits that were designed were usually simple enough to allow for a verbal specification. Verification was done by testing. Powerful tools like Higher Order Logic, VHDL, ADL and RT languages support the system design process in a way that hardware costs and processing time can be reduced drastically. In this session we have four papers covering this topic. The first paper "On the formal specification and verification of digital circuits" of P.J. de Graaff from Eindhoven University, The Netherlands, shows that formal verification of digital circuits can be done in a very elegant way, that it does not have to lead to extensive testing. Higher Order Logic is used in this paper to describe various implementations and how they can be verified against a given specification. The second paper "An interactive environment for hardware/software systems design at the specification level" by Dr. Stefano Antoniazzi and Dr. Mirella Mastretti from ITALTEL, Central Research Laboratories, Italy, describes a specification framework. This is a dedicated software environment to support specification acquisition and handling. The approach was initially implemented using Smalltalk, lateron it was done in C++. Natural language and visual programming techniques are provided to complement the VHDL textual input.
The third paper "A rational methodology for the design of new computer structures" by Edwige Pissaloux, University Paris, France, describes a universal methodology for the design of new computer structures. The chosen approach is a generalisation of the von Neumann methodology. It permits the design of new hardware structures in accord with the completeness theorem. It optimises the hardware cost of computers and decreases the processing time of programs. In the fourth paper "Behavioral Circuit Description on System Level" Uwe Wienkop from Siemens AG, Germany, presents several description mechanisms for a system level language. By the example of a packet switching node the paper demonstrates the expressiveness of ADL as a high level description mechanism.
Microprocessingand Microprogramming30 (1990)535-536
Session F2:
535
System Design II Chairman: K. Klockner Gesellschaft fur Mathematik und Datenverarbeitung St. Augustin Germany
Things have changed a lot in formal specification... Ten years ago, circuits that were designed were usually simple enough to allow for a verbal specification. Verification was done by testing. Powerful tools like Higher Order Logic, VHDL, ADL and RT languages support the system design process in a way that hardware costs and processing time can be reduced drastically. In this session we have four papers covering this topic. The first paper "On the formal specification and verification of digital circuits" of P.J. de Graaff from Eindhoven University, The Netherlands, shows that formal verification of digital circuits can be done in a very elegant way, that it does not have to lead to extensive testing. Higher Order Logic is used in this paper to describe various implementations and how they can be verified against a given specification. The second paper "An interactive environment for hardware/software systems design at the specification level" by Dr. Stefano Antoniazzi and Dr. Mirella Mastretti from ITALTEL, Central Research Laboratories, Italy, describes a specification framework. This is a dedicated software environment to support specification acquisition and handling. The approach was initially implemented using Smalltalk, lateron it was done in C++. Natural language and visual programming techniques are provided to complement the VHDL textual input.
The third paper "A rational methodology for the design of new computer structures" by Edwige Pissaloux, University Paris, France, describes a universal methodology for the design of new computer structures. The chosen approach is a generalisation of the von Neumann methodology. It permits the design of new hardware structures in accord with the completeness theorem. It optimises the hardware cost of computers and decreases the processing time of programs. In the fourth paper "Behavioral Circuit Description on System Level" Uwe Wienkop from Siemens AG, Germany, presents several description mechanisms for a system level language. By the example of a packet switching node the paper demonstrates the expressiveness of ADL as a high level description mechanism.