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Silicon carbide as a new MEMS technology
Sensors and Actuators 82 Ž2000. 210–218 www.elsevier.nlrlocatersna
Silicon carbide as a new MEMS technology Pasqualina M. Sarro
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DIMES, Delft UniÕersity of Technology, Delft UniÕersity of Technology, DIMES, Laboratory of Electronic Materials, DeÕices and Components, P.O. Box 5053, 2600 GB Delft, Netherlands Received 11 October 1999; accepted 12 October 1999
Abstract Silicon carbide ŽSiC. is a material with very attractive properties for microsystems applications. Its mechanical strength, high thermal conductivity, ability to operate at high temperatures and extreme chemical inertness in several liquid electrolytes, make SiC an attractive candidate for MEMS applications, both as structural material and as coating layer. The recently reported progress in material growth and processing techniques has strengthened the potential of this material for MEMS, especially for applications requiring operation at high temperature or in severe environments. Examples of SiC microsensors and microstructures are given and interesting development in both material characteristics and micromachining processes are discussed. q 2000 Elsevier Science S.A. All rights reserved. Keywords: MEMS; Silicon carbide; Micromachining; Mechanical stress
1. Introduction An increasing demand for sensors that can operate at temperatures well above 3008C and often in severe environments Žautomotive and aerospace applications: combustion processes or gas turbine control; oil industry. has stimulated the search for alternatives to silicon. In order to benefit from the enormous know how on silicon integrated circuit ŽIC. technology attention is first directed to silicon derivatives. Silicon carbide ŽSiC. is a material that has attracted much attention for a long time, particularly due to its wide bandgap, its ability to operate at high temperatures, its mechanical strength and its inertness to exposure in corrosive environments. However, the difficulty in growing crystalline material and the limited knowledge in the areas of oxidation, doping, etching and metallization have limited its use to very specific applications area, such as light emitting devices and specific high-temperature, high-power or high-frequency applications that are not suitable for Si- or GaAs-based devices. For other applications and particularly for SiC-MEMS devices, large area substrates are essential. In the past decade great progress has been made with respect to the growth of single crystal wafers now commercially available and what is much
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Corresponding author. Tel.: q31-15-278-77-08; fax: q31-152787369. E-mail: [email protected]
more relevant to the MEMS community, in epitaxial growth of single and poly-crystalline SiC layers on silicon w1x. These developments have stimulated research on deposition, characterization and further processing of SiC for MEMS. In this paper we review some of the most interesting results both in terms of material characteristics and micromachining processes and give a few examples of MEMS devices which indicate the great progress made in SiC MEMS technology and underline the potential of this material for MEMS.
2. Growth and deposition technologies 2.1. Single crystal SiC Several techniques are used to grow single crystal SiC. Next to seed-sublimation techniques used for growing SiC bulk material, significant progresses have been made in the growth of mono Žand poly. crystalline layers on a silicon substrate by using Metalorganic Chemical Vapor Deposition ŽMOCVD., gas-source Molecular Beam Epitaxy ŽMBE., electron cyclotron resonance ŽECR. plasma and liquid phase epitaxy w1,2x. Breakthroughs in crystal growth reported in the past decade resulted in the availability of single crystal SiC wafers w3–7x n- and p-type doped. This, together with the progress made in ion implantation, oxida-
0924-4247r00r$ - see front matter q 2000 Elsevier Science S.A. All rights reserved. PII: S 0 9 2 4 - 4 2 4 7 Ž 9 9 . 0 0 3 3 5 - 0
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tion and ohmic contact formation has increased the use of this material for sensors which need to operate at high temperatures, such as piezoresistive sensors w8x, gas sensors w9x and flame detectors w10x. However, single crystal wafers of SiC are not suitable for MEMS, as conventional micromachining of these wafers is not Žyet. possible. Recent developments in epitaxial and CVD growth of SiC single crystal layers Žmostly in the cubic phase, 3C-SiC. on silicon substrates w2,3,11–16x are of more interest for MEMS. In this way, the specific properties of crystalline SiC can be combined with the rather developed and widely used silicon micromachining techniques. A number of manufacturers of SiC wafers andror epitaxy are reported in Table 1. SiC wafers are available up to 2 in. in diameter. Although growth of 3-in. diameter SiC wafers have been achieved w4,17x they are not yet commercially available. SiC layers up to 50 mm in thickness grown on various sizes of silicon substrates are offered. Furthermore, very interesting developments with respect to dedicated epitaxial reactors w18–20x have contributed to a wider accessibility and better quality of epitaxial layers of single crystal SiC on both Si and SiC substrates. 2.2. Poly-SiC Despite the remarkable progress obtained in singlecrystal layer growth, still elevated temperature and rather complex processes are required. The possibility of using lower processing temperatures and substrates other than single crystal silicon, which is crucial for surface micromachining applications, justify the interest in poly-crystalline and amorphous SiC layers. Some of the processes developed to epitaxially grow single crystal layers of SiC on silicon substrates can also be used to grow polycrystalline layers. For example, Fleischman et al. w21x reported the growth of 3C-SiC poly-crystalline films. These layers are deposited in APCVD system at 10008C, using a polysilicon layer as seed layer. Undoped films are mostly used, although doping can be added either during the growth or by ion implantation. Hot wall LPCVD at temperatures between 900–10508C for poly-SiC films on 3 and 4-in. silicon wafers with controllable mechanical stress has been used by Yamaguchi et al. w22x. A reactive sputtering Table 1 Major manufacturers of single crystal SiC wafers Žbulk or epitaxy.
Cree Research Westinghouse Nippon Steel Sterling Semiconductors SiCrystal Nasa Glenn IMCrKHT Technologies and Devices Intl. Hoya
Single crystal SiC
Reference
Bulk and Epi Bulk Bulk Bulk Bulk Epi Bulk and Epi Epi Epi
w3x w4x w5x w6x w7x w13x w14x w15x w16x
211
process that requires lower temperatures Ž650–7508C. than epitaxial growth has been developed by Onuma et al. w23x. Oxidized silicon wafers are used as substrate. These films appear to contain the b-phase and are suitable for high temperature thermistors and pressure sensors. Flow and temp sensors w24x have been fabricated using poly-SiC deposited by plasma-assisted chemical vapor deposition at 7508C. Poly-SiC can be patterned by dry etching, using similar processes to the ones used for single crystal SiC. Mostly fluorine-based chemistry is used and some data are available w25x. Selectivity to silicon or oxide is still a problem and often aluminum is used as masking layer. This last possibility, although improving etch selectivity, cannot be always used as it can lead to contamination problems when further processing of the wafers is required. 2.3. Amorphous SiC All the above mentioned techniques still use rather high processing temperatures Ž) 6008C.. Lower deposition temperatures and the use of commercially available systems is quite interesting for IC compatible MEMS processing. In fact, the thermal and mechanical properties or the chemical inertness of SiC can significantly improve device performance or simplify fabrication processing even when high temperature operation is not required. Recently, it has been demonstrated that SiC can also be deposited as amorphous material using lower deposition techniques. Next to plasma enhanced techniques w26–29x, laser ablation deposition ŽLAD. in which a high purity SiC target is ablated using KrF pulsed excimer laser w30x or triode sputtering deposition, in which a SiC target is rf-sputtered under argon gas pressure w31x have been reported. Despite of the lower deposition temperature, many of the attractive properties of this material are still preserved. Furthermore, tuning of the process is possible, as relationships between deposition parameters and film properties are investigated. Depending on the specific application and the maximum thermal budget allowed, a particular deposition or treatment can be selected. Tong et al. w26x reported PECVD deposition of silicon carbide for surface micromachining applications. The quality of these films can be improved by post-deposition annealing in N2 up to 8008C. Klump et al. w27x used a liquid source instead of gas in their PECVD SiC deposition system. Particular attention has been paid to the mechanical stress, an important parameter in MEMS. Post-deposition anneals at temperatures between 450 and 6008C were often required to reduce stress. The etch-resistance of SiC in HF allows the use of porous silicon as sacrificial layer and its thermal properties make it an interesting membrane material for thermal devices. Recent work related to the use of PECVD SiC for MEMS was reported by Flannery et al. w28x. Their work concentrated on the chemical inertness and the mechanical characteristics of the layers mostly employed as protective coating
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in various MEMS applications. An interesting finding is the relation between the film composition and the etch rate in commonly used anisotropic etchants for silicon as KOH. As MEMS research activities at DIMES focus on ICcompatible processing, we are interested in exploring the potentials of SiC layers deposited using low temperature techniques. Thin films of amorphous SiC are deposited in a conventional PECVD reactor, a Novellus Concept One System. This is a multi-station, sequential deposition reactor, which allows process optimization while maintaining a high throughput. This system allows the growth of both doped and undoped SiC films and makes it possible to control the stress by altering some deposition parameters, particularly the low frequency ŽLF. component of the RF power w29x. So far we have used only undoped SiC films, deposited on Si wafers coated by oxide, nitride, polysilicon andror aluminum. The SiC films are patterned in conventional dry etching equipment, using fluorine-based chemistry and photoresist as masking layer. Generally as-deposited films are in compressive stress, which shifts into the tensile region after a post-deposition anneal between 4008C and 6008C. However, films with a low tensile stress without requiring any heat treatments are often required in freestanding microstructures. Recently, the effect of pressure and gas flow ratio on the stress has been further investigated. By selecting the proper combination of deposition parameters is possible to obtain as-deposited layers with a slightly tensile stress as shown in Fig. 1, where the average stress values and deposition rate are plotted vs. pressure. Apparently the use of a larger SiH 4 flow and somewhat lower pressure have the desired effect on the stress without a negative effect on deposition rate and uniformity. Similar values have been obtained for films deposited on wafers coated by an oxide Žthermal and PECVD., nitride ŽLPCVD and PECVD., polysilicon or aluminum layer in the same deposition conditions. The effect of the substrate although present, does not change the sign of the stress, which remains tensile in all cases. The step coverage is rather good as shown in Fig. 2 for a 500 nm-thick SiC layer deposited on patterned layers of oxide, aluminum and polysilicon.
Fig. 2. SEM micrographs illustrating the step coverage of PECVD SiC deposited on patterned Ža. oxide, Žb. aluminum and Žc. polysilicon Žmagnification 20,000=..
Next to evaluate mechanical and structural properties, the thermal conductivity of these films w32x and their chemical inertness have been evaluated w29x. The measured thermal conductivity values, although lower than the ones reported for single crystal bulk material, are more than five times higher than the values measured for polysilicon thin films. The chemical inertness in most of the commonly used etchants in MEMS processing is largely preserved despite the amorphous nature of these films. Table 2 summarizes some of the characteristics of these films. These low stress PECVD SiC films have been used in various MEMS applications, in both bulk and surface micromachined structures, as passivation to protect metallization in harsh environments and as coating in silicon– glassrglass–glass bonded microstructures for bio-analytic applications. 2.4. Micromachining processes
Fig. 1. Mechanical stress ŽB. and deposition rate Žl. of PECVD SiC thin films deposited at 4008C, using an increase SiH 4 flow, as a function of reactor pressure.
In order to realize SiC microstructures, micromachining technologies have to be developed. As SiC can now be deposited on silicon substrates, the bulk and surface micro-
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Table 2 Properties of PECVD amorphous-SiC thin films
˚ 400–1000 Armin 900 MPa Žcompressive. ™ 200 MPa Žtensile. 200 MPa Žcompressive. ™1000 MPa Žtensile.
Deposition rate Mechanical stress Žas-deposited. Mechanical stress Žafter 6008C anneal.
˚ - 20 Arh
Etch rate in KOH 33 wt.% @858C Etch rate in TMAH 25 wt.% @808C
˚ - 20 Arh
Etch rate in 40%HF
˚ -10 Arh
Etch rate in HFrHNO3 Ž2:5. Etch rate in CF4 rSF6 rO 2 plasma Thermal conductivity
˚ 900–1200 Arh 70–450 nmrmin 130–160 Wrm K Fig. 3. Schematic view of the process flow for SiC bulk micromachining: Ža. back side and Žb. front-side etching.
machining processes developed for silicon can be used as starting point to realize SiC microstructures. The applicability of conventional micromachining processes and the possibility of using it as coating in relation to the type of SiC used Žsingle-crystal, polycrystalline or amorphous. are indicated in Table 3 and discussed in the following sections. 2.5. Bulk micromachining Conventional silicon bulk micromachining can be used for single-crystal, poly and amorphous SiC. In the case of single-crystal generally epi-SiC on Si is used, although a BMM SiC pressure sensors using SiC epi on SiC bulk substrate has been reported w33x. Electrochemical etching from the backside has been used to realize 25 mm-thick membranes containing piezoresistors. In the case of epi-SiC on Si, both front and backside bulk micromachining are feasible as shown in Fig. 3 where a schematic view of the process flow is depicted. Due to the high etch resistance in most commonly used anisotropic etchants to remove the bulk silicon ŽKOH, TMAH or EDP solutions., this process is a truly post-processing one. In the case of a backside BMM ŽFig. 3a., the process is very similar to the one applied to SOI wafers, with the difference that SiC is much more resistant to any etchant than oxide, so that the etch stop on the SiC membrane is excellent. Freestanding structures can be realized in one etch step using front side micromachining ŽFig. 3b.. In this case the SiC microstruc-
Table 3 Applicability of conventional silicon MEMS technologies to SiC SiC Monocrystalline Polycrystalline Amorphous
BMM a
6 6 6
SMM
Coating
x 6 6
x xb 6
6s possible. x s Not possible or very difficult. a Epitaxial layer of crystalline SiC on Si. b Depending on substrate and thermal budget allowed.
tures are patterned first and the etching of the bulk silicon is done as a final post-processing step. Single crystal and poly SiC layers between a few microns and several tens have been used for BMM structures. Their mechanical properties can be adjusted during or after growth, so to obtained low stress structures. Amorphous SiC films are generally thinner as stress is more difficult to control. Therefore, they are often used in sandwich configurations together with silicon oxide, nitride or polysilicon. 2.6. Surface micromachining As explained in the previous section, single-crystal SiC films must be grown directly on single-crystal silicon. Therefore, no conventional surface micromachining is possible with crystalline layers on silicon. Poly-crystalline and amorphous SiC layers, on the other hand, can be grown and deposited on various substrates and are suitable for surface micromachining. Poly-SiC is generally grown on a poly-Si layer or deposited on oxide layers. The SiC is the mechanical or structural layer while the poly-Si or the oxide is used as sacrificial layer, as schematically illustrated in Fig. 4. When poly-Si is used as sacrificial layer, KOH or TMAH can be used to release the SiC microstructures, so that the oxide can be used to protect the underlying silicon during the final sacrificial etch. If the oxide is used as sacrificial layer, HF based solutions are used, just as in conventional silicon surface micromachining. No protection of the mechanical layer is required since SiC is HF resistant. Multi-layer structures are also possible. If under the poly-Si layer an oxide layer is grown, the oxide is used as sacrificial layer and both poly-Si and poly-SiC can be used as mechanical layer. For example, this configuration was selected to realize a micromotor with a rotor made of polySi and a stator made of the much better wear resistant poly SiC w34x with nitride and oxide as substrate protection and sacrificial layer, respectively.
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Fig. 4. Schematic view of the process flow for SiC surface micromachining for poly-SiC and amorphous SiC as mechanical layer.
Conventional surface micromachining can also be applied to amorphous SiC films. Moreover, as these films can be deposited also on metal, due to the lower deposition temperatures ŽF 4008C., surface micromachining using metal as sacrificial layer is possible as well. Although no report in the literature has been found so far, it is possible to envision further expansion of Si MEMS technology to SiC MEMS. In fact, new silicon MEMS technologies such as Deep Reactive Ion Etching ŽDRIE. or epi-micromachining w35x could also be employed for SiC MEMS. As SiC is grown on Si wafers and as plasma etching of both Si and SiC is possible in the same fluorine based chemistry, it should be possible to apply DRIE to the SiCrSi system as well. A modified epi-micromachining process, as schematically illustrated in Fig. 5, could also be used as alternative to surface micromachining when single crystal SiC is required as structural layer. In fact the SiC layer can be patterned by a dry etching process and a pre-defined region of the silicon can be made porous and removed Žsee Fig. 5a. or the underlying silicon can be directly etched in KOH or TMAH solutions to the desired depth ŽFig. 5b..
Fig. 5. Schematic view of the process flow for SiC epi-micromachining with Ža. a sacrificial layer is etched to release the microstructures; Žb. the silicon substrate is locally etched to release the microstructures.
2.7. Wafer-to-wafer bonding As for Si MEMS the possibility to use wafer bonding for SiC to either seal micromachined structures or split the process on two distinct wafers is quite attractive. Therefore, the possibility to bond SiC Žor SiC-on-Si. wafers to silicon or glass wafers has been investigated. The bonding to silicon wafers is mostly done through an oxide-to-oxide bonding w36x. Bonding to glass wafers is possible as well using conventional anodic bonding. At DIMES we have successfully bonded silicon wafers coated by amorphous layers of PECVD SiC to glass, using conventional anodic bonding. More recently, a glass-to-glass bonding process using various intermediate layers, among which PECVD SiC, has been demonstrated w37x. As an example, a device using this technology is shown in the coming section. The developments on wafer bonding have had also a positive impact on SiC on insulator ŽSiCOI.. In fact although Si on insulator ŽSOI. can be used up to 4508C, it is not suitable when harsh environment is present. In this case a SiCOI is preferred to SiC on Si. Various techniques have been reported. Eickhoff et al. w38x use an SOI wafer as starting material. After growing and patterning an oxide layer, SiC is epitaxially grown in the open windows producing selectively grown SiC regions Žsee Fig. 6a.. A different approach is used by Serre et al. w39x and it is schematically depicted in Fig. 6b. The top wafer is a silicon wafer in which a buried SiC layer is formed by high temperature multiple implantation of C followed by an annealing step. Then the top silicon layer is fully oxidized and bonded to an oxidized silicon handle wafer by a long high-temperature anneal step Ž11008C for 5 h.. A third approach Žsee Fig. 6c. is reported by Tong et al. w40x. This is quite similar to the method used to fabricate SOI wafers Žoxidation, bonding and etch back.. Unfortunately only 30% of the SiC area remains bonded after etch back of the silicon handle wafer. Better results Žup to 80% of bonded area. using an additional polysilicon layer on top of the oxide have been reported by Vinod et al. w41x. Polishing to a mirror finish of the polysilicon surface and a
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Fig. 6. Schematic view of SiC on insulator processes: Ža. selective epitaxial growth on SOI; Žb. buried SiC layer formed by ion implantation and followed by wafer bonding and etch back; Žc. epitaxial growth of SiC layer followed by wafer bonding and etch back.
high temperature anneal Ž11008C for 5 h. are essential for a successful bonding.
3. Devices and microstructures The progress made so far is quite encouraging and the number of projects and groups working on SiC MEMS is steadily increasing. In order to illustrate the state of the art of SiC devices and microstructures, a few examples are given. b-SiC films grown on silicon have been used to realize bulk micromachined membranes for pressure sensors or for gas sensing w42x. Epitaxial layers of single crystal 3C-SiC have been used to realize pressure sensors designed for operations at 4008C w43x. High temperature pressure sensors based on APCVD 3C-SiC grown on
silicon and anisotropically etched to realize membranes have been realized and tested in the 0–1 bar-pressure range w44x. Interesting developments on MEMS-based micro-gas turbine engines have been presented recently w45x. This specific application area largely benefits from materials with high specific strength and creep resistance at elevated temperature. The thermal and mechanical properties of SiC together with the possibility to micromachine it, make it an ideal candidate for such an application. High aspect ratio SiC microstructures have been realized using rather thick Ž10–200 mm. CVD SiC layers deposited on deep etched silicon molds. Poly-SiC surface micromachining has resulted in several devices, such as lateral resonant structures with resonance operation up to 9008C w21x and micromotors operating up to 5008C w34x.
Fig. 7. Bulk micromachined SiCrSiN membrane with a poly-Si-heating resistor and poly-SirAl thermocouples on it for thermal conductivity measurements.
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stress testing, chemical testing and mechanical stress, have been performed. Initial results w46x indicate that PECVD SiC thin films are more resilient to stress and generally show fewer failure than other conventionally used passivation layers. Finally the low temperature deposition of the SiC layers has made it possible to use it also on glass. The remarkable etch resistance to HF based solution used to etch deep channels into glass, make it a suitable masking layer for this purpose. Furthermore, due to its chemical inertness SiC is very attractive as insulating material in biochemical analysis systems, as it prevents sticking of organic molecules in the channel and eventually clogging of the device. This characteristic together with the recently demonstrated possibility of bonding a glass wafer coated by PECVD SiC to another glass wafer resulted in an all-glass sealed channel with integrated liquid conductivity detector w47x. A photograph of one such device is shown in Fig. 8 together with a close up of the cross section of the channel coated by a 1 mm-thick PECVD SiC layer.
4. Conclusions
Fig. 8. All glass sealed channel with integrated liquid conductivity detector: Ža. optical micrograph of the device; Žb. SEM micrograph of the cross section of the channel after etching and coating with 1 mm-thick SiC layer.
Quite a few microstructures have been realized using amorphous SiC either as a structural layer or as coating. Among the first reported devices are freestanding 200 nm-thick SiC membranes for thin film bolometers w27x. More recently, PECVD SiC films have been successfully employed as protective coating in several MEMS applications w28x, such as microelectrode probes that can be employed in HF solutions, as passivation for front-side bulk micromachined pressure sensors and as coating in microfluidic channels. The PECVD SiC thin films deposited in our laboratory have been used in various MEMS applications. Next to use it as protection layer in conventional bulk and surface micromachining, SiC and SiCrSiN membranes with polyrSi–Al thermocouples on it w32x have been realized. In Fig. 7 an example of such micromachined membrane structure used to measure thermal properties of the SiC films is shown. These PECVD SiC films are also quite suitable as passivation layers on top of sensors that need to operate in harsh environments. Several tests, including high temperature operating test, temperature cycling, highly accelerated
Silicon carbide appears to be a good candidate for MEMS applications, particularly when high operation temperatures or harsh environments are involved. The recent developments on SiC deposition techniques, the improved control on its properties and the progress on SiC micromachining are quite promising and have resulted in a number of SiC MEMS devices and structures. Although quite some work still needs to be done, SiC MEMS technology has definitely demonstrated its potentials and entered new and challenging areas. Furthermore, the research on material and process technology for SiC MEMS will also advance the state of the art in SiC electronics.
Acknowledgements The author would like to thank all DIMES colleagues and graduate students who have contributed to the material presented in this paper. Particularly the contributions of C.R. de Boer, who is responsible for the SiC PECVD depositions, Axel Berthold for his work on wafer bonding and Andrea Irace for the thermal conductivity measurements, are greatly appreciated.
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w30x S. Boily, M. Chaker, H. Pepin, T. Kerdja, J. Voyer, A. Jean, J.C. Kieffer, P. Leung, F. Cerrina, G. Wells, SiC membranes for X-ray masks produced by laser ablation deposition, J. Vac. Sci. Technol. B 9 Ž6. Ž1991. 3254–3257. w31x A.M. Haghiri-Gosnet, F. Rousseaux, B. Kebabi, F.R. Ladan, C. Mayeux, A. Madouri, D. Decanini, J. Bourneix, F. Carcenac, H. Launois, B. Wisniewski, E. Gat, J. Durand, A 100-nm patterned X-ray mask technology based on amorphous SiC membranes, J. Vac. Sci. Technol. B 8 Ž6. Ž1990. 1565–1569. w32x A. Irace, P.M. Sarro, Thermal Conductivity Measurement on a SiC Thin Film, Proc. Eurosensors ’99 Conf., The Hague, The Netherlands, Sept. 12–15, 1999, pp. 809–812. w33x R.S. Okojie, A.A. Ned, A.D. Kurtz, W.N. Carr, a Ž6H.-SiC Pressure Sensors for high temperature applications, Proc. IEEE-MEMS, San Diego, CA, Feb. 11–15, 1996, pp. 146–149. w34x A.A. Yasseen, H. Wu, C.A. Zorman, M. Mehregany, Fabrication and testing of surface micromachined silicon carbide micromotors, Proc. IEEE-MEMS 99, Orlando, FL, USA, 17–21 Jan. 1999, pp. 644–649. w35x P.M. Sarro, P.J. French, P.J.T. Gennissen, New developments in the integration of micromachined sensors, Žinvited paper. Proc. SPIE Micromachining and Microfabrication ’96 Symposium, Austin, TX, USA, 14–15 October, 1996, SPIE Vol. 2882, pp. 26–36. w36x Q.-Y. Tong, U. Gosele, Semiconductor Wafer Bonding: Science and ¨ Technology, Wiley, USA, 1999. w37x A. Berthold, P.M. Sarro, M.J. Vellekoop, L. Nicola, A novel technological process for glass-to-glass anodic bonding, Proc. Transducers 99, Sendai, Japan, June 7–10, 1999, pp. 1324–1327. w38x M. Eickhoff, H. Moller, G. Kroetz, J.V. Berg, R. Ziermann, A high ¨ temperature pressure sensor prepared by selective deposition of cubic silicon carbide on SOI substrates, Sensors and Actuators A 74 Ž1999. 56–59. w39x C. Serre, A. Romano-Rodriguez, A. Perez-Rodriguez, J.R. Morante, L. Fonseca, M.C. Acero, R. Kogler, W. Skorupa, b-SiC on SiO 2 ¨ formed by ion implantation and bonding for micromechanics applications, Sensors and Actuators A 74 Ž1999. 169–173. w40x Q. Tong, U. Gosele, C. Yuan, A.J. Steckl, M. Reiche, SiC wafer bonding, J. Electrochem. Soc. 142 Ž1995. 232–236. w41x K. Vinod, C.A. Zorman, M. Mehregany, A novel SiC on insulator technology using wafer bonding, Proc. Transd. ’97, Chicago, USA, June 16–19, 1997, pp. 653–656. w42x G. Krotz, G. ¨ Ch. Wagner, W. Legner, H. Sonntag, H. Moller, ¨ Muller, Micromachining applications of heteroepitaxially grown b¨ SiC layers on silicon, Proc. Int Conf on SiC and Related Materials, Kyoto, Japan, 1995, pp. 829–832. w43 x M. Mehregany, http:rrmems.eeap.cwru.edurSiCrPagesr devices.html. w44x C. Gourbeyre, P. Aboughe-nze, C. Malhaire, M. LeBerre, Y. Monteil, D. Barbier, SiC thin film characterization and stress measurements for high temperature sensors applications, MRS ’98 Fall Meeting, Boston, MA, USA, Nov. 30–Dec. 4, 1998, Book of Abstracts, AA4.3, full paper to be published in MRS Proceedings Series, Vol. 546, pp. 500. w45x K.A. Lohner, K.S. Chen, A.A. Ayon, S.M. Spearing, Microfabricated silicon carbide microengine structures, MRS ’98 Fall Meeting, Boston, MA, USA, Nov. 30–Dec. 4, 1998, Book of Abstracts, AA5.2, full paper to be published in MRS Proceedings Series, Vol. 546, pp. 502. w46x P. Trimp, J.R. Mollinger, A. Bossche, F.R. Riedijk, P.J. French, A study of the reliability of passivation layers for sensors applications, Proc. Eurosensors XIII Conf., The Hague, Netherlands, 12–15 Sept. 1999, pp. 823–826. w47x A. Berthold, L. Nicola, P.M. Sarro, M.J. Vellekoop, G. Pignatel, All-glass microstructures for biochemical analysis systems, Proc. Eurosensors XIII Conf., The Hague, Netherlands, 12–15 Sept. 1999, pp. 975–978.
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Biography Pasqualina M. Sarro received the Laurea degree in solid-states physics from the University of Naples, Italy, in 1980. From 1981 to 1983, she was a post-doctoral fellow in the Photovoltaic Research Group of the Division of Engineering, Brown University, Rhode Island, U.S.A., where she worked on thin-film photovoltaic cell fabrication by chemical spray pyrolysis. In 1987, she received the Ph.D. degree in Electrical Engineering at the Delft University of Technology, the Netherlands, her thesis dealing with infrared sensors based on integrated silicon thermopiles. Since then, she has been with the Delft Institute of Microelectronics and Submicron Technology ŽDIMES., at the Delft University, where she is responsible for research on integrated silicon sensors and microsystems technology. Since April 1996 she is also Associate Professor in the Electronic Components, Materials and Technology Laboratory of the Delft University. She has been an IEEE member since 1984 and a Senior Member since 1997. She acts as reviewer for numerous technical journals and has served as technical program committee member of the ESSDERC Conferences Žsince ’95., the SPIE 5th Annual Symposium on SMART STRUCTURES and MATERIALS ’98 and EUROSENSORS ’99.
Silicon carbide as a new MEMS technology Pasqualina M. Sarro
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DIMES, Delft UniÕersity of Technology, Delft UniÕersity of Technology, DIMES, Laboratory of Electronic Materials, DeÕices and Components, P.O. Box 5053, 2600 GB Delft, Netherlands Received 11 October 1999; accepted 12 October 1999
Abstract Silicon carbide ŽSiC. is a material with very attractive properties for microsystems applications. Its mechanical strength, high thermal conductivity, ability to operate at high temperatures and extreme chemical inertness in several liquid electrolytes, make SiC an attractive candidate for MEMS applications, both as structural material and as coating layer. The recently reported progress in material growth and processing techniques has strengthened the potential of this material for MEMS, especially for applications requiring operation at high temperature or in severe environments. Examples of SiC microsensors and microstructures are given and interesting development in both material characteristics and micromachining processes are discussed. q 2000 Elsevier Science S.A. All rights reserved. Keywords: MEMS; Silicon carbide; Micromachining; Mechanical stress
1. Introduction An increasing demand for sensors that can operate at temperatures well above 3008C and often in severe environments Žautomotive and aerospace applications: combustion processes or gas turbine control; oil industry. has stimulated the search for alternatives to silicon. In order to benefit from the enormous know how on silicon integrated circuit ŽIC. technology attention is first directed to silicon derivatives. Silicon carbide ŽSiC. is a material that has attracted much attention for a long time, particularly due to its wide bandgap, its ability to operate at high temperatures, its mechanical strength and its inertness to exposure in corrosive environments. However, the difficulty in growing crystalline material and the limited knowledge in the areas of oxidation, doping, etching and metallization have limited its use to very specific applications area, such as light emitting devices and specific high-temperature, high-power or high-frequency applications that are not suitable for Si- or GaAs-based devices. For other applications and particularly for SiC-MEMS devices, large area substrates are essential. In the past decade great progress has been made with respect to the growth of single crystal wafers now commercially available and what is much
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Corresponding author. Tel.: q31-15-278-77-08; fax: q31-152787369. E-mail: [email protected]
more relevant to the MEMS community, in epitaxial growth of single and poly-crystalline SiC layers on silicon w1x. These developments have stimulated research on deposition, characterization and further processing of SiC for MEMS. In this paper we review some of the most interesting results both in terms of material characteristics and micromachining processes and give a few examples of MEMS devices which indicate the great progress made in SiC MEMS technology and underline the potential of this material for MEMS.
2. Growth and deposition technologies 2.1. Single crystal SiC Several techniques are used to grow single crystal SiC. Next to seed-sublimation techniques used for growing SiC bulk material, significant progresses have been made in the growth of mono Žand poly. crystalline layers on a silicon substrate by using Metalorganic Chemical Vapor Deposition ŽMOCVD., gas-source Molecular Beam Epitaxy ŽMBE., electron cyclotron resonance ŽECR. plasma and liquid phase epitaxy w1,2x. Breakthroughs in crystal growth reported in the past decade resulted in the availability of single crystal SiC wafers w3–7x n- and p-type doped. This, together with the progress made in ion implantation, oxida-
0924-4247r00r$ - see front matter q 2000 Elsevier Science S.A. All rights reserved. PII: S 0 9 2 4 - 4 2 4 7 Ž 9 9 . 0 0 3 3 5 - 0
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tion and ohmic contact formation has increased the use of this material for sensors which need to operate at high temperatures, such as piezoresistive sensors w8x, gas sensors w9x and flame detectors w10x. However, single crystal wafers of SiC are not suitable for MEMS, as conventional micromachining of these wafers is not Žyet. possible. Recent developments in epitaxial and CVD growth of SiC single crystal layers Žmostly in the cubic phase, 3C-SiC. on silicon substrates w2,3,11–16x are of more interest for MEMS. In this way, the specific properties of crystalline SiC can be combined with the rather developed and widely used silicon micromachining techniques. A number of manufacturers of SiC wafers andror epitaxy are reported in Table 1. SiC wafers are available up to 2 in. in diameter. Although growth of 3-in. diameter SiC wafers have been achieved w4,17x they are not yet commercially available. SiC layers up to 50 mm in thickness grown on various sizes of silicon substrates are offered. Furthermore, very interesting developments with respect to dedicated epitaxial reactors w18–20x have contributed to a wider accessibility and better quality of epitaxial layers of single crystal SiC on both Si and SiC substrates. 2.2. Poly-SiC Despite the remarkable progress obtained in singlecrystal layer growth, still elevated temperature and rather complex processes are required. The possibility of using lower processing temperatures and substrates other than single crystal silicon, which is crucial for surface micromachining applications, justify the interest in poly-crystalline and amorphous SiC layers. Some of the processes developed to epitaxially grow single crystal layers of SiC on silicon substrates can also be used to grow polycrystalline layers. For example, Fleischman et al. w21x reported the growth of 3C-SiC poly-crystalline films. These layers are deposited in APCVD system at 10008C, using a polysilicon layer as seed layer. Undoped films are mostly used, although doping can be added either during the growth or by ion implantation. Hot wall LPCVD at temperatures between 900–10508C for poly-SiC films on 3 and 4-in. silicon wafers with controllable mechanical stress has been used by Yamaguchi et al. w22x. A reactive sputtering Table 1 Major manufacturers of single crystal SiC wafers Žbulk or epitaxy.
Cree Research Westinghouse Nippon Steel Sterling Semiconductors SiCrystal Nasa Glenn IMCrKHT Technologies and Devices Intl. Hoya
Single crystal SiC
Reference
Bulk and Epi Bulk Bulk Bulk Bulk Epi Bulk and Epi Epi Epi
w3x w4x w5x w6x w7x w13x w14x w15x w16x
211
process that requires lower temperatures Ž650–7508C. than epitaxial growth has been developed by Onuma et al. w23x. Oxidized silicon wafers are used as substrate. These films appear to contain the b-phase and are suitable for high temperature thermistors and pressure sensors. Flow and temp sensors w24x have been fabricated using poly-SiC deposited by plasma-assisted chemical vapor deposition at 7508C. Poly-SiC can be patterned by dry etching, using similar processes to the ones used for single crystal SiC. Mostly fluorine-based chemistry is used and some data are available w25x. Selectivity to silicon or oxide is still a problem and often aluminum is used as masking layer. This last possibility, although improving etch selectivity, cannot be always used as it can lead to contamination problems when further processing of the wafers is required. 2.3. Amorphous SiC All the above mentioned techniques still use rather high processing temperatures Ž) 6008C.. Lower deposition temperatures and the use of commercially available systems is quite interesting for IC compatible MEMS processing. In fact, the thermal and mechanical properties or the chemical inertness of SiC can significantly improve device performance or simplify fabrication processing even when high temperature operation is not required. Recently, it has been demonstrated that SiC can also be deposited as amorphous material using lower deposition techniques. Next to plasma enhanced techniques w26–29x, laser ablation deposition ŽLAD. in which a high purity SiC target is ablated using KrF pulsed excimer laser w30x or triode sputtering deposition, in which a SiC target is rf-sputtered under argon gas pressure w31x have been reported. Despite of the lower deposition temperature, many of the attractive properties of this material are still preserved. Furthermore, tuning of the process is possible, as relationships between deposition parameters and film properties are investigated. Depending on the specific application and the maximum thermal budget allowed, a particular deposition or treatment can be selected. Tong et al. w26x reported PECVD deposition of silicon carbide for surface micromachining applications. The quality of these films can be improved by post-deposition annealing in N2 up to 8008C. Klump et al. w27x used a liquid source instead of gas in their PECVD SiC deposition system. Particular attention has been paid to the mechanical stress, an important parameter in MEMS. Post-deposition anneals at temperatures between 450 and 6008C were often required to reduce stress. The etch-resistance of SiC in HF allows the use of porous silicon as sacrificial layer and its thermal properties make it an interesting membrane material for thermal devices. Recent work related to the use of PECVD SiC for MEMS was reported by Flannery et al. w28x. Their work concentrated on the chemical inertness and the mechanical characteristics of the layers mostly employed as protective coating
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in various MEMS applications. An interesting finding is the relation between the film composition and the etch rate in commonly used anisotropic etchants for silicon as KOH. As MEMS research activities at DIMES focus on ICcompatible processing, we are interested in exploring the potentials of SiC layers deposited using low temperature techniques. Thin films of amorphous SiC are deposited in a conventional PECVD reactor, a Novellus Concept One System. This is a multi-station, sequential deposition reactor, which allows process optimization while maintaining a high throughput. This system allows the growth of both doped and undoped SiC films and makes it possible to control the stress by altering some deposition parameters, particularly the low frequency ŽLF. component of the RF power w29x. So far we have used only undoped SiC films, deposited on Si wafers coated by oxide, nitride, polysilicon andror aluminum. The SiC films are patterned in conventional dry etching equipment, using fluorine-based chemistry and photoresist as masking layer. Generally as-deposited films are in compressive stress, which shifts into the tensile region after a post-deposition anneal between 4008C and 6008C. However, films with a low tensile stress without requiring any heat treatments are often required in freestanding microstructures. Recently, the effect of pressure and gas flow ratio on the stress has been further investigated. By selecting the proper combination of deposition parameters is possible to obtain as-deposited layers with a slightly tensile stress as shown in Fig. 1, where the average stress values and deposition rate are plotted vs. pressure. Apparently the use of a larger SiH 4 flow and somewhat lower pressure have the desired effect on the stress without a negative effect on deposition rate and uniformity. Similar values have been obtained for films deposited on wafers coated by an oxide Žthermal and PECVD., nitride ŽLPCVD and PECVD., polysilicon or aluminum layer in the same deposition conditions. The effect of the substrate although present, does not change the sign of the stress, which remains tensile in all cases. The step coverage is rather good as shown in Fig. 2 for a 500 nm-thick SiC layer deposited on patterned layers of oxide, aluminum and polysilicon.
Fig. 2. SEM micrographs illustrating the step coverage of PECVD SiC deposited on patterned Ža. oxide, Žb. aluminum and Žc. polysilicon Žmagnification 20,000=..
Next to evaluate mechanical and structural properties, the thermal conductivity of these films w32x and their chemical inertness have been evaluated w29x. The measured thermal conductivity values, although lower than the ones reported for single crystal bulk material, are more than five times higher than the values measured for polysilicon thin films. The chemical inertness in most of the commonly used etchants in MEMS processing is largely preserved despite the amorphous nature of these films. Table 2 summarizes some of the characteristics of these films. These low stress PECVD SiC films have been used in various MEMS applications, in both bulk and surface micromachined structures, as passivation to protect metallization in harsh environments and as coating in silicon– glassrglass–glass bonded microstructures for bio-analytic applications. 2.4. Micromachining processes
Fig. 1. Mechanical stress ŽB. and deposition rate Žl. of PECVD SiC thin films deposited at 4008C, using an increase SiH 4 flow, as a function of reactor pressure.
In order to realize SiC microstructures, micromachining technologies have to be developed. As SiC can now be deposited on silicon substrates, the bulk and surface micro-
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Table 2 Properties of PECVD amorphous-SiC thin films
˚ 400–1000 Armin 900 MPa Žcompressive. ™ 200 MPa Žtensile. 200 MPa Žcompressive. ™1000 MPa Žtensile.
Deposition rate Mechanical stress Žas-deposited. Mechanical stress Žafter 6008C anneal.
˚ - 20 Arh
Etch rate in KOH 33 wt.% @858C Etch rate in TMAH 25 wt.% @808C
˚ - 20 Arh
Etch rate in 40%HF
˚ -10 Arh
Etch rate in HFrHNO3 Ž2:5. Etch rate in CF4 rSF6 rO 2 plasma Thermal conductivity
˚ 900–1200 Arh 70–450 nmrmin 130–160 Wrm K Fig. 3. Schematic view of the process flow for SiC bulk micromachining: Ža. back side and Žb. front-side etching.
machining processes developed for silicon can be used as starting point to realize SiC microstructures. The applicability of conventional micromachining processes and the possibility of using it as coating in relation to the type of SiC used Žsingle-crystal, polycrystalline or amorphous. are indicated in Table 3 and discussed in the following sections. 2.5. Bulk micromachining Conventional silicon bulk micromachining can be used for single-crystal, poly and amorphous SiC. In the case of single-crystal generally epi-SiC on Si is used, although a BMM SiC pressure sensors using SiC epi on SiC bulk substrate has been reported w33x. Electrochemical etching from the backside has been used to realize 25 mm-thick membranes containing piezoresistors. In the case of epi-SiC on Si, both front and backside bulk micromachining are feasible as shown in Fig. 3 where a schematic view of the process flow is depicted. Due to the high etch resistance in most commonly used anisotropic etchants to remove the bulk silicon ŽKOH, TMAH or EDP solutions., this process is a truly post-processing one. In the case of a backside BMM ŽFig. 3a., the process is very similar to the one applied to SOI wafers, with the difference that SiC is much more resistant to any etchant than oxide, so that the etch stop on the SiC membrane is excellent. Freestanding structures can be realized in one etch step using front side micromachining ŽFig. 3b.. In this case the SiC microstruc-
Table 3 Applicability of conventional silicon MEMS technologies to SiC SiC Monocrystalline Polycrystalline Amorphous
BMM a
6 6 6
SMM
Coating
x 6 6
x xb 6
6s possible. x s Not possible or very difficult. a Epitaxial layer of crystalline SiC on Si. b Depending on substrate and thermal budget allowed.
tures are patterned first and the etching of the bulk silicon is done as a final post-processing step. Single crystal and poly SiC layers between a few microns and several tens have been used for BMM structures. Their mechanical properties can be adjusted during or after growth, so to obtained low stress structures. Amorphous SiC films are generally thinner as stress is more difficult to control. Therefore, they are often used in sandwich configurations together with silicon oxide, nitride or polysilicon. 2.6. Surface micromachining As explained in the previous section, single-crystal SiC films must be grown directly on single-crystal silicon. Therefore, no conventional surface micromachining is possible with crystalline layers on silicon. Poly-crystalline and amorphous SiC layers, on the other hand, can be grown and deposited on various substrates and are suitable for surface micromachining. Poly-SiC is generally grown on a poly-Si layer or deposited on oxide layers. The SiC is the mechanical or structural layer while the poly-Si or the oxide is used as sacrificial layer, as schematically illustrated in Fig. 4. When poly-Si is used as sacrificial layer, KOH or TMAH can be used to release the SiC microstructures, so that the oxide can be used to protect the underlying silicon during the final sacrificial etch. If the oxide is used as sacrificial layer, HF based solutions are used, just as in conventional silicon surface micromachining. No protection of the mechanical layer is required since SiC is HF resistant. Multi-layer structures are also possible. If under the poly-Si layer an oxide layer is grown, the oxide is used as sacrificial layer and both poly-Si and poly-SiC can be used as mechanical layer. For example, this configuration was selected to realize a micromotor with a rotor made of polySi and a stator made of the much better wear resistant poly SiC w34x with nitride and oxide as substrate protection and sacrificial layer, respectively.
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Fig. 4. Schematic view of the process flow for SiC surface micromachining for poly-SiC and amorphous SiC as mechanical layer.
Conventional surface micromachining can also be applied to amorphous SiC films. Moreover, as these films can be deposited also on metal, due to the lower deposition temperatures ŽF 4008C., surface micromachining using metal as sacrificial layer is possible as well. Although no report in the literature has been found so far, it is possible to envision further expansion of Si MEMS technology to SiC MEMS. In fact, new silicon MEMS technologies such as Deep Reactive Ion Etching ŽDRIE. or epi-micromachining w35x could also be employed for SiC MEMS. As SiC is grown on Si wafers and as plasma etching of both Si and SiC is possible in the same fluorine based chemistry, it should be possible to apply DRIE to the SiCrSi system as well. A modified epi-micromachining process, as schematically illustrated in Fig. 5, could also be used as alternative to surface micromachining when single crystal SiC is required as structural layer. In fact the SiC layer can be patterned by a dry etching process and a pre-defined region of the silicon can be made porous and removed Žsee Fig. 5a. or the underlying silicon can be directly etched in KOH or TMAH solutions to the desired depth ŽFig. 5b..
Fig. 5. Schematic view of the process flow for SiC epi-micromachining with Ža. a sacrificial layer is etched to release the microstructures; Žb. the silicon substrate is locally etched to release the microstructures.
2.7. Wafer-to-wafer bonding As for Si MEMS the possibility to use wafer bonding for SiC to either seal micromachined structures or split the process on two distinct wafers is quite attractive. Therefore, the possibility to bond SiC Žor SiC-on-Si. wafers to silicon or glass wafers has been investigated. The bonding to silicon wafers is mostly done through an oxide-to-oxide bonding w36x. Bonding to glass wafers is possible as well using conventional anodic bonding. At DIMES we have successfully bonded silicon wafers coated by amorphous layers of PECVD SiC to glass, using conventional anodic bonding. More recently, a glass-to-glass bonding process using various intermediate layers, among which PECVD SiC, has been demonstrated w37x. As an example, a device using this technology is shown in the coming section. The developments on wafer bonding have had also a positive impact on SiC on insulator ŽSiCOI.. In fact although Si on insulator ŽSOI. can be used up to 4508C, it is not suitable when harsh environment is present. In this case a SiCOI is preferred to SiC on Si. Various techniques have been reported. Eickhoff et al. w38x use an SOI wafer as starting material. After growing and patterning an oxide layer, SiC is epitaxially grown in the open windows producing selectively grown SiC regions Žsee Fig. 6a.. A different approach is used by Serre et al. w39x and it is schematically depicted in Fig. 6b. The top wafer is a silicon wafer in which a buried SiC layer is formed by high temperature multiple implantation of C followed by an annealing step. Then the top silicon layer is fully oxidized and bonded to an oxidized silicon handle wafer by a long high-temperature anneal step Ž11008C for 5 h.. A third approach Žsee Fig. 6c. is reported by Tong et al. w40x. This is quite similar to the method used to fabricate SOI wafers Žoxidation, bonding and etch back.. Unfortunately only 30% of the SiC area remains bonded after etch back of the silicon handle wafer. Better results Žup to 80% of bonded area. using an additional polysilicon layer on top of the oxide have been reported by Vinod et al. w41x. Polishing to a mirror finish of the polysilicon surface and a
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Fig. 6. Schematic view of SiC on insulator processes: Ža. selective epitaxial growth on SOI; Žb. buried SiC layer formed by ion implantation and followed by wafer bonding and etch back; Žc. epitaxial growth of SiC layer followed by wafer bonding and etch back.
high temperature anneal Ž11008C for 5 h. are essential for a successful bonding.
3. Devices and microstructures The progress made so far is quite encouraging and the number of projects and groups working on SiC MEMS is steadily increasing. In order to illustrate the state of the art of SiC devices and microstructures, a few examples are given. b-SiC films grown on silicon have been used to realize bulk micromachined membranes for pressure sensors or for gas sensing w42x. Epitaxial layers of single crystal 3C-SiC have been used to realize pressure sensors designed for operations at 4008C w43x. High temperature pressure sensors based on APCVD 3C-SiC grown on
silicon and anisotropically etched to realize membranes have been realized and tested in the 0–1 bar-pressure range w44x. Interesting developments on MEMS-based micro-gas turbine engines have been presented recently w45x. This specific application area largely benefits from materials with high specific strength and creep resistance at elevated temperature. The thermal and mechanical properties of SiC together with the possibility to micromachine it, make it an ideal candidate for such an application. High aspect ratio SiC microstructures have been realized using rather thick Ž10–200 mm. CVD SiC layers deposited on deep etched silicon molds. Poly-SiC surface micromachining has resulted in several devices, such as lateral resonant structures with resonance operation up to 9008C w21x and micromotors operating up to 5008C w34x.
Fig. 7. Bulk micromachined SiCrSiN membrane with a poly-Si-heating resistor and poly-SirAl thermocouples on it for thermal conductivity measurements.
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stress testing, chemical testing and mechanical stress, have been performed. Initial results w46x indicate that PECVD SiC thin films are more resilient to stress and generally show fewer failure than other conventionally used passivation layers. Finally the low temperature deposition of the SiC layers has made it possible to use it also on glass. The remarkable etch resistance to HF based solution used to etch deep channels into glass, make it a suitable masking layer for this purpose. Furthermore, due to its chemical inertness SiC is very attractive as insulating material in biochemical analysis systems, as it prevents sticking of organic molecules in the channel and eventually clogging of the device. This characteristic together with the recently demonstrated possibility of bonding a glass wafer coated by PECVD SiC to another glass wafer resulted in an all-glass sealed channel with integrated liquid conductivity detector w47x. A photograph of one such device is shown in Fig. 8 together with a close up of the cross section of the channel coated by a 1 mm-thick PECVD SiC layer.
4. Conclusions
Fig. 8. All glass sealed channel with integrated liquid conductivity detector: Ža. optical micrograph of the device; Žb. SEM micrograph of the cross section of the channel after etching and coating with 1 mm-thick SiC layer.
Quite a few microstructures have been realized using amorphous SiC either as a structural layer or as coating. Among the first reported devices are freestanding 200 nm-thick SiC membranes for thin film bolometers w27x. More recently, PECVD SiC films have been successfully employed as protective coating in several MEMS applications w28x, such as microelectrode probes that can be employed in HF solutions, as passivation for front-side bulk micromachined pressure sensors and as coating in microfluidic channels. The PECVD SiC thin films deposited in our laboratory have been used in various MEMS applications. Next to use it as protection layer in conventional bulk and surface micromachining, SiC and SiCrSiN membranes with polyrSi–Al thermocouples on it w32x have been realized. In Fig. 7 an example of such micromachined membrane structure used to measure thermal properties of the SiC films is shown. These PECVD SiC films are also quite suitable as passivation layers on top of sensors that need to operate in harsh environments. Several tests, including high temperature operating test, temperature cycling, highly accelerated
Silicon carbide appears to be a good candidate for MEMS applications, particularly when high operation temperatures or harsh environments are involved. The recent developments on SiC deposition techniques, the improved control on its properties and the progress on SiC micromachining are quite promising and have resulted in a number of SiC MEMS devices and structures. Although quite some work still needs to be done, SiC MEMS technology has definitely demonstrated its potentials and entered new and challenging areas. Furthermore, the research on material and process technology for SiC MEMS will also advance the state of the art in SiC electronics.
Acknowledgements The author would like to thank all DIMES colleagues and graduate students who have contributed to the material presented in this paper. Particularly the contributions of C.R. de Boer, who is responsible for the SiC PECVD depositions, Axel Berthold for his work on wafer bonding and Andrea Irace for the thermal conductivity measurements, are greatly appreciated.
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Biography Pasqualina M. Sarro received the Laurea degree in solid-states physics from the University of Naples, Italy, in 1980. From 1981 to 1983, she was a post-doctoral fellow in the Photovoltaic Research Group of the Division of Engineering, Brown University, Rhode Island, U.S.A., where she worked on thin-film photovoltaic cell fabrication by chemical spray pyrolysis. In 1987, she received the Ph.D. degree in Electrical Engineering at the Delft University of Technology, the Netherlands, her thesis dealing with infrared sensors based on integrated silicon thermopiles. Since then, she has been with the Delft Institute of Microelectronics and Submicron Technology ŽDIMES., at the Delft University, where she is responsible for research on integrated silicon sensors and microsystems technology. Since April 1996 she is also Associate Professor in the Electronic Components, Materials and Technology Laboratory of the Delft University. She has been an IEEE member since 1984 and a Senior Member since 1997. She acts as reviewer for numerous technical journals and has served as technical program committee member of the ESSDERC Conferences Žsince ’95., the SPIE 5th Annual Symposium on SMART STRUCTURES and MATERIALS ’98 and EUROSENSORS ’99.