Silicon oxide defects in aging of MOS electronic devices

] O f f R N A L OF

ELSEVIER

Journal of Non-Crystalline Solids 216 (1997) 209-212

Silicon oxide defects in aging of MOS electronic devices Marc de la Bardonnie a,*, Alain Maouad b, Pierre Mialhe a

a

Centre d'Etudes Fondamentales, Universit~ de Perpignan, 52, avenue de ViUeneuve, 66860 Perpignan cedex, France b Laboratoire de Physique des Semiconducteurs et Energdtique, Universit~ Libanaise, B.P. 90 656, Jdeidet, Lebanon

Abstract

Electrical ageing with applied drain and gate bias on n type metal-oxide-semiconductor (MOS) transistors has been shown to produce defects in the insulating oxide (SiO 2) layer. The characterization method is based on numerical analysis performed on the substrate-drain junction experimental current-voltage curves to extract electrical parameters. The observed recombination carrier increase is related to hot carriers electron induced damage in the gate-to-drain overlap region. © 1997 Elsevier Science B.V.

1. Introduction

Degradation of the electrical properties of micrometric metal-oxide-semiconductor devices under normal supply voltages has been discussed previously in terms of the creation of interface-semiconductor-oxide states and of oxide trapping sites [1]. The origin of these defects is related to the presence of very high fields which increase carrier injection into the thermally grown silicon dioxide layer (SiO 2) used as gate insulator [2]. The injection process is enhanced near the drain edge where the channel field attains its greatest magnitude [3]. The large electric field causes the generation of states at the siliconoxide interface and of trapping sites in the oxide layer [4]. Various mechanisms have been proposed to describe the physical processes which lead to damage localization in the MOS structure, but no consensus

* Corresponding author. Tel. + 3 3 - 4 68 66 20 70; fax: + 3 3 - 4 68 66 22 34; e-mail: [email protected].

has been reached [5]. Earlier studies have been based on process simulations to predict the distribution of injected hot carriers into the gate oxide, the mechanisms for defect generation, the resulting amount of carder trapping and interface damage, and the degradation of the device characteristics [6]. They have shown the important effects, on the observed degradation effects, of the damage localization along the oxide-semiconductor interface and in the oxide towards the drain terminal. The distribution of the defects have been determined by a number of techniques [6]. In this work the influence of the oxide insulating layer on the ageing of micrometric transistors (channel length within 1 Ixm) is considered. The method focuses on the drain region and is based on the extraction of device parameters from the substratedrain junction experimental current-voltage data. Evolution of the parameters is followed during electrical ageing of the device in order to observe changes in carrier transport processes and in substrate-drain junction properties.

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2. Method

Experiments have been performed with n-channel metal-oxide semiconductor transistors (MOSFETs) from SCMOS technology [7] obtained from MATRA MHS company (France) Fig. 1 displays the MOS structure, the gate dimensions were 0.8 Ixm length and 1.4 I~m width, and the gate oxide thickness was 19.5nm. Four classes of defects in S i / S i O 2 systems have been recognized [8,9] as influencing electronic MOS devices. These are: fixed oxide charge, mobile ionic charge, interface-trapped charge and oxidetrapped charge. Near interfacial oxide traps or border traps are to be taken into account [10,11] to provide a complete description of MOS electrical response. Oxide traps and fixed oxide charge lie in the oxide and act on Si via modification of its surface potential [9]. Interface traps are associated with trivalent Si defects and exchange charge with silicon (capture and emission of channel carriers) [10]. Border traps located in the oxide close to the Si/SiO 2 interface can interact with the silicon [10]. The sources of defects are varied and depend on the technological steps for device fabrication and the annealing process is known to increase the density of oxygen vacancies in S i t 2 [11]. In our experiments, the device has been stressed with an applied high drain voltage (VDs) of 6 V and a gate voltage (Vcs) of 5 V. These conditions of stressing have been applied for this study since for these stressing conditions it has been recognized [1] that (i) the oxide trapped charge is mostly responsible for the damage whereas the degradation at Vcs ---Vos/2 arises from the interface state creation, and that (ii) the injected carriers are mainly composed of electrons. Pre- and post-stress measurements of the drain current versus gate to source voltage dependence have been performed with a 0.1 V drain

Gate Source ~ rnetai i ....... ? ! S i O 2 oxide n+j . " ,I

i '

Drain ~(

~," - . n+ Substrate p

Fig. 1. Schematic structure of a planar MOS device.

voltage which was also applied for measurements of the current, I, as a function of voltage (V), I(V), of the substrate-drain junction. The hot carrier stressing effect was observed and the evolution of the I(V) properties due to gradual degradation with time of the structure has been recorded. In the experiment, one hundred current-voltage data points of the I(V) dependence of the substrate-drain junction were obtained with a computer-driven acquisition system and stored for modeling analysis. The I(V) dependence of silicon p - n junctions is described by mathematical models introducing physical and electrical parameters. This experimental procedure has been given elsewhere [12]. The junction single exponential model (SEM) given by Eq. (1) introduces four parameters, i.e., the series and shunt resistances R S, and Rsh, the diode ideality factor, n, the reverse generation-recombination current, /Or, which are to be determined so that the graph of I(V) gives a description of the I(V) dependence [13]:

V - RsI l=--+Ior[e

(q/°'kr~×v R ~ , , _ I ] .

(1)

Rsh

The diode ideality factor is related to physical transport phenomena occurring in the device. Ideality factor, n = l, is related to a next to ideal junction and an increase of n implies carrier recombination via traps in the space-charge region, n = 2 is an indication of surface recombination near the junction [14-16]. Parameters are extracted from the experimental characteristics by a specifically developed software PARADI [17].

3. Results

Fig. 2 shows the evolution of the transistor transconductance ( g m ) for increasing stress durations. Degradation is observed during the first minutes of ageing and a saturation of the effect occurred after 4 h. No change, greater than errors of measurement, of the threshold voltage was observed during the experiment. The threshold voltage shift was obtained from the intercept of the extrapolated value of the I J g~m data with the voltage axis, leading to a shift less than 10 inV. During the stress, performed

M. de la Bardonnie et al. / Journal of Non-Crystalline Solids 216 (1997) 209-212

16 14 (p,vJ)12 lo 8 6 4 2 oo

211

Rs (ohms)

I~efore stres~

Duralion of

gm

slress (mn) ~J

....... ~ . . . . . .

7

mo [ ] 15

1

2

3

4

120

5

1136o

V (V) GS

VGs Fig. 2. Evolution of the transconductance of the n MOS during stress at VGS = 5 V, Vos = 6 V.

with a gate voltage value close to the drain voltage value, the injected hot carriers are composed mainly of electrons which is consistent with the observed effect on the gm data. The maximum of the transconductance, Gm, is approximately at the same gate voltage and, for large V~s, the transconductance data is independent of the stress time. This evolution has already been obtained with larger transistors having a graded gate structure [18] and with transistors stressed with larger drain current levels [19]. This effect is explained by electron induced damage created near the drain-channel region or further into the gate-to-drain overlap region, thus in regions out of gate control, and is confirmed by the observed absence of variation of the threshold voltage. Further investigations of the degradation process have been performed and Fig. 3 displays I(V) dependence of the substrate-drain junction. The evolution of the curves can be observed during degradation obtained with an electrical stress. A change in

Fig. 4. Extracted series resistance as a function of the gate to source voltage during stress.

,2.6 .2.4

2.2 2 1.8 -0.5 0.5 1.b VGS(V) Fig. 5. Quality factor vs. gate to source voltage after different stress time.

the direction of the evolution occurs after 15 rain of stress. Parameters, R~, n, and /Or, have been extracted from the I(V) dependence obtained during ageing and for various gate voltages (Figs. 4-6). The values of all these parameters show a gradual evolution during the stress experiment and the change in the

Ior (A) 20

Before ~ s

tD(mA)10155

00.0

J

I

o.15 _'4//

0h454h2h~~'~/~f

0.5

1.0

1.5

VSDfV) Fig. 3. Evolution of the 1 - V characteristic of the substrate-drain junction during stress at V~s = 5 V, VDs = 6 V.

~.5

0.5

1.5

2,5

V

3.b

4.b

N) GS

Fig. 6. Extracted recombination current lot vs. gate to source voltage during stress.

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M. de la Bardonnie et al. / Journal of Non-Crystalline Solids 216 (1997) 209-212

direction of the evolution is noticeable for the series resistance.

4. Discussion

The decrease of R s and the increase of the quality factor, n, for an increasing gate voltage up to 2 V was expected since the increase of Vas leads to an increase of the voltage drop through the SiO 2 layer. Hence, before the creation of the inversion layer, the increasing electron concentration decreases Rs and enlarges the induced depleted region. The effect on the parameters, due to change in carrier transport processes, is larger than that due to the inversion layer formation below the oxide-semiconductor interface. The junction properties and operating activity are related to the interface electrostatic potential which depends on the applied gate voltage and the surface charge density and on the oxide charge [9]. The oxide charge decreases the electrical field at the injecting interface and thereby increases the barrier height. It follows that the oxide layer properties are of great importance on MOS devices. The increase of the ideality factor during the stress, to values larger than two is due to an increase of carrier recombination at the oxide-semiconductor interface and in the space charge region of the junction due to the larger density of traps. This result is confirmed by the increase of the generation-recombination current, /Or, with stress time. The initial evolution of the series resistance is considered to be a consequence of energetic electrons trapped within the drain region leading to a decrease of R~. With the condition of stress corresponding to an injection of electrons, negative charges are trapped deeper in the oxide explaining the following slower increase of R~. A fraction of these injected electrons recombines in the insulation oxide and neutral defects move.

5. Conclusion

We have demonstrated that the study of substrate-drain junction of MOS devices provides in-

sight into the affects of the properties of the gate insulating SiO 2 layer on the degradation of micrometric transistors under normal operating conditions. A two step process has been deduced based on the observation that degradation appears in the region of the gate-controlled junction. It is of interest to improve the intrinsic hardness of commercial MOS gate oxides specially in sub-micrometric devices where the influence of border traps is greater than in larger devices.

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