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silicon nitride dual-layer films: a stacked gate dielectric for the 21st century
Journal of Non-Crystalline Solids 254 (1999) 26±37
www.elsevier.com/locate/jnoncrysol
Silicon oxide/silicon nitride dual-layer ®lms: a stacked gate dielectric for the 21st century Gerald Lucovsky * Departments of Physics, Electrical and Computer Engineering, and Materials Science and Engineering, North Carolina State University, Raleigh, NC 27695-8202, USA
Abstract Incorporation of nitrogen atoms into ultra thin (<0.3 nm) gate dielectrics (i) reduces defect generation at the Si±SiO2 interface, (ii) allows use of physically thicker dielectrics when incorporated into oxide±nitride stacked gate dielectrics, and (iii) prevents boron atom transport out of heavily doped p polycrystalline silicon gate electrodes when nitrided layers are incorporated at the polycrystalline Si-dielectric interface. I demonstrate that nitrogen atoms can be selectively and independently incorporated into dierent parts of the gate dielectric structure by low-temperature (300°C) remote plasma assisted processing followed by low-thermal budget rapid thermal annealing (RTA) yielding state of the art ®eld eect transistors with oxide equivalent thicknesses less than 2 nm. Ó 1999 Elsevier Science B.V. All rights reserved.
1. Introduction As lateral device dimensions are scaled into the submicron regime <100 nm to achieve greater levels of speed and integration, there must be corresponding decreases in the oxide-equivalent thickness of dielectrics, tox-eq , to <2 nm to maintain current levels needed for circuit operation [1]. Direct tunneling currents increase exponentially with decreasing oxide layer thickness establishing a limitation of the use of SiO2 as a gate dielectric. As an example, an oxide thickness of 3 nm and less de®nes the regime of ultra thin oxides in which direct tunneling is the dominant mechanism for current transport through the oxide ®lm, and a practical limitation for oxides is tox-eq 1.6 nm, the thickness at which the direct tunneling current
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reaches a level of 1 A cmÿ2 for an oxide bias of 1 V. The technology challenge is to increase the physical thickness of gate dielectrics to reduce tunneling current while maintaining a tox-eq that corresponds to a signi®cantly thinner SiO2 ®lm by using alternative insulators with dielectric constants larger than SiO2 . These alternative dielectrics include silicon nitride, Si3 N4 , as well as other metal binary and ternary oxides such as Ta2 O5 and ZrSiO4 , respectively. These alternative dielectrics can be incorporated into stacked structures, such as the oxide±nitride, ON, composites, as well as including other alternative larger-K materials such as TiO2 or Ta2 O5 in combination with either Si±SiO2 or nirtided Si±SiO2 interfaces. This paper considers on the nitrided oxides, in particular stacked ON structures with nitrided Si± SiO2 interfaces, and does not address the alternative larger-K materials. Spatially selective incorporation of nitorgen (N) atoms into advanced gate dielectrics (i) reduces
0022-3093/99/$ ± see front matter Ó 1999 Elsevier Science B.V. All rights reserved. PII: S 0 0 2 2 - 3 0 9 3 ( 9 9 ) 0 0 4 3 2 - 9
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defect generation at the Si±SiO2 interface when N-atoms incorporated at monolayer concentrations [2±6], (ii) allows the use of physically thicker stacked dielectrics when silicon nitride layers are incorporated into the body of gate dielectric as in ON stacks, [7±10], and (iii) reduces boron (B) atom penetration out of doped p polycrystalline silicon gate electrodes through the dielectric ®lms to the Si±SiO2 interface when the nitride layers are at the polycrystalline Si-dielectric interface [11±13]. This paper presents research results from a program at North Carolina State University that have demonstrated separate and independent control of Natom incorporation in these dierent parts of oxide gate dielectrics through combined use of plasma-assisted processing at 300°C, and lowthermal-budget rapid thermal annealing (RTA), e.g., 30 s at 900°C [2,6±11,13±15]. This review is restricted to devices prepared by remote plasma processing, and will not describe formation of nitrided gate dielectrics by thermal processing, direct plasma processing, jet vapor deposition, or other physical vapor deposition techniques such as reactive sputtering or evaporation. 2. Experimental procedures 2.1. Remote plasma processing Fig. 1 is a schematic of a prototypical remote plasma processing chamber that has been used for Si±SiO2 interface formation, SiO2 and silicon nitride, Si3 N4 ®lm deposition, and Si±SiO2 interface and SiO2 top-surface nitridation [16]. Plasma assisted activation of reactive species for plasma processing has been achieved by radio frequency, rf, excitation at 13.56 MHz, and typically at power levels from 15 to 60 W. The coupling to the plasma is capacitive with the `coil' being the hot electrode, and the metal plate at the top of the chamber being grounded. The same basic chamber design has been implemented into several dierent multichamber systems (e.g., see Ref. [10]), that include additional chambers for (i) surface chemical analysis by Auger electron spectroscopy, AES, and (ii) RTA. The remote plasma processing chamber provides gas introduction through a plasma
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Fig. 1. Schematic diagram of remote plasma processing chamber.
excitation tube, as well as by downstream injection through showerhead dispersal rings. Remote plasma processing is dierentiated from conventional or direct plasma processing in three ways: (i) it provides selective excitation of source and carrier gases as determined by their point of injection into the system, either through the plasma tube, or through the downstream showerhead injection ring; (ii) the deposition substrate is outside of the plasma glow region; (iii) the source gases injected downstream from the plasma generation region are prevented from back-streaming into the plasma generation region by gas ¯ow and process pressure [16]. In addition, several of these plasma chambers have been ®xtured for in situ process diagnostics, including mass spectrometry, MS, and optical emission spectroscopy, OES. The implementation of remote plasma processing chambers into multi-chamber systems has made it possible (i) to interrupt plasma-assisted oxidation, nitridation and/or deposition processes and then, without removing the sample from a ultra-high-vacuum, UHV, compatible environment, to perform on-line chemical analysis by AES and (ii) to integrate online sequences of plasma processing with RTA. These devices utilize four 300°C remote plasmaassisted processes and RTA states that are outlined in Table 1: (i) plasma-assisted oxidation for
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G. Lucovsky / Journal of Non-Crystalline Solids 254 (1999) 26±37
Table 1 Process steps for forming device-quality stacked gate oxide dielectrics Process step
Process conditions
Processing results
(a) Remote plasmaassisted oxidation
Substrate temperature 300°C; process pressure 300 mTorr; plasma excited mixture He/O2 (200 sccm He, 20 sccm O2 ); time 15±30 s
(b) Remote plasmaenhanced CVD (c) Remote plasmaassisted interface nitridation
Substrate temperature 300°C; process pressure 300 mTorr; plasma excited mixture He/O2 (200 sccm He/ 20 sccm O2 ); down-stream mixture He/SiH4 (20 sccm He/0.4 sccm SiH4 ) Substrate temperature 300°C; process pressure 300 mTorr; plasma excited mixture He/N2 (160 sccm He, 60 sccm N2 ); time 90 s
(d) Remote plasmaassisted top surface nitridation
Substrate temperature 300°C; process pressure 100 mTorr; plasma excited mixture He/N2 (200 sccm He, 20 sccm N2 ); time 10±20 min
In situ substrate cleaning (reduces C and F level); forms Si±SiO2 interface; grows passiviting oxide 0.5 nm; introduces sub-oxide bonding at Si±SiO2 interface Forms body of dielectric ®lm; deposition rate 2.5±5.0 nm/min; stoichiometric SiO2 NO-IR detectable Si±H or Si±OH Low Si±OH (n5 at.% H) Inserts approximately one monolayer of nitrogen atoms at Si±SiO2 interface; nitrogen is localized at interface; nitrogen concentration scales with time Forms 2 molecular layers of silicon nitride at top surface of a plasma or thermally-grown oxide; sucient to suppress boron diusion
(e) Rapid thermal annealing
Temperate: 900°C Time: 30 seconds Low pressure or atmospheric inert gas ambident (e.g., Ar)
Reduces oxidation induced sub-oxide bonding at Si±SiO2 interface; promotes densi®cation of oxide ®lms; reduces bonded-H (mostly in nitrides)
Si±SiO2 interface formation, (ii) plasma-assisted interface nitridation, (iii) plasma-assisted nitridation of oxide top surfaces, (iv) plasma-assisted deposition of `bulk' oxide and nitride ®lms; i.e., remote plasma-enhanced chemical-vapor deposition (RPECVD), and (v) RTA. Additionally, PMOS structures have been fabricated in which nitride ®lms have been deposited directly onto to hydrogen terminated Si surfaces. Two types of structures were fabricated ± devices with (i) nitride layers 4 nm, thick and (ii) nitride layers of 0.4 and 0.8 nm which were over coated with 4 nm of plasma-deposited SiO2 . 2.2. Interface characterization The primary tools for interface measurements have been on-line AES, and o-line secondary ion mass spectrometry, SIMS. Figs. 2 and 3, respectively, display (i) AES results for an interrupted interface nitridation process and (ii) SIMS results for dierent interface nitridation exposure times using CsN detection. The AES spectra of Fig. 2 indicate no NKLL feature after an initial oxidation process that produces 0.5 0.1 nm of oxide as
Fig. 2. Time evolution of dierential counting rate (dn(E)/dE) for Auger electron spectroscopy (AES) spectra as a function of kinetic energy (E), for the O2 remote plasma-assisted oxidation process combined with post-oxidation nitridation from an N2 /He plasma for dierent exposure times.
G. Lucovsky / Journal of Non-Crystalline Solids 254 (1999) 26±37
Fig. 3. Secondary ion mass spectrometry (SIMS) depth pro®les for the N2 /He plasma nitridation process. The plasma processed interface has been over coated with 5 nm of plasma-deposited SiO2 . The intensity of the SIMS intensity is plotted as function of the depth (x) from the surface of the sample.
determined from the ratio of the amplitude of SiLVV oxide feature at 76 eV to that of the SiLVV substrate feature at 91 eV, using a nominal electron escape depth of 0.6 nm [17]. By taking measurements at several points on the wafer, it was determined that the thickness of the plasma-grown oxide was uniform to 0.1 nm. This uniformity is further con®rmed by electrical measurements. As the exposure time to the upstream N2 /He plasma is increased, a NKLL feature emerges and increases in intensity with increasing exposure time. The SIMS data are also for dierent interface nitridation times. The nitrided interfacial oxide of Fig. 3 has been over coated with approximately 5 nm of SiO2 . The nitrogen atom concentration is obtained by integration of the CsN signal. This data reduction analysis shows a linear increase of the integrated peak signal as a function of exposure time, with a time of 90 s yielding approximately one monolayer of N atom coverage (see Fig. 4). There is still some controversy with regard to the correct way to normalize the SIMS results, i.e., using the relative
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Fig. 4. Normalized nitrogen concentration obtained from integration of SIMS pro®les versus nitridation time (t). The value of one (1) corresponds to approximately (10%) one monolayer of interfacial nitrogen atoms.
sensitivity factor for N atoms in SiO2 or crystalline Si. Since these dier by a factor of more than 2, this is the primary source of uncertainty in determining N-atom areal density concentrations. The normalization of this paper has utilized the approach of Ref. [2], which established that monolayer interface nitridation could also be achieved by plasma-assisted nitridation using N2 O as the source gas. Interfacial nitridation, as de®ned above, means that N atoms are bonded directly to the Si substrate and provide a chemical bridge between that substrate and the plasma-grown SiO2 layer. The concentration of nitrogen atoms is equal to the surface concentration of Si atoms on the (1 0 0) face, 7 ´ 1014 cmÿ2 . This monolayer concentration was further con®rmed by nuclear reaction analysis which gave a nitrogen areal density of 8 1 ´ 1014 cmÿ2 [18]. Interfacial nitridation by this approach has also been con®rmed by angle resolved X-ray photoelectron spectroscopy (ARXPS) studies [19]. The plot in Fig. 5 establishes that the N-atoms injected into the oxidized layer by exposure to the N2 /He plasma products are localized at the
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Fig. 5. Comparison of (i) the ratio of the amplitudes of the NKLL and substrate SiLVV feature peaks (N/Si ratio) as a function of nitridation time (t), and (ii) the amplitude of the NKLL feature peak as a function of nitridation time (t).
Si±SiO2 interface. This is con®rmed by noting ®rst that a plot of the intensity of the NKLL AES feature versus time is sublinear, but that a plot of the ratio of the intensities of the NKLL and SiLVV substrate AES features is linear. The lack of linearity for the NKLL versus time plot derives from increases in dielectric layer thickness with increasing nitridation time, and normalization by the substrate SiLVV feature takes this into account. 2.3. Nitride ®lm properties Device grade silicon nitride ®lms have been prepared by RPECVD at 300°C using either N2 or HN3 as the source gas for N, and SiH4 as the source gas for Si. Previous publications have considered the local atomic bonding of Si, N and H in these ®lms as a function of the source gas mixtures, e.g., the ratio of NH3 to SiH4 [6± 9,20,21]. As-deposited ®lms deposited from 10 : 1 NH3 /SiH4 mixtures provided optimized performance as a gate dielectric for thin ®lm transistors [21], whereas annealing these ®lms at 400±450°C and using them as a constituent layer in stacked oxide±nitride±oxide (ONO) gate dielectrics yields marginal performance [6±9]. On the other hand,
annealing the ONO stacks at 900°C for approximately 30 s in an inert ambient, e.g., Ar, results in excellent device performance with reliability generally exceeding oxide dielectrics with the same oxide equivalent thickness [22]. These dierences in performance have been resolved by employing AES and infrared spectroscopy for chemical measurements [21]. The optimized as-deposited ®lms display only Si±N bonding by on-line AES, whereas, as shown in Ref. [21], the ®lms deposited with lower ¯ow rates of NH3 or N2 to SiH4 are sub-nitrides with both Si±Si and Si±N bonds detected by AES. Also, shown in Ref. [21], bonded hydrogen occurs predominantly as Si±H in the sub-nitrides, whereas SiN±H groups dominate in the hydrogenated nitrides. Typical bonded hydrogen concentrations in the as-deposited ®lms are 20 at.% for ®lms grown from N2 , and 28 at.% for ®lms grown from NH3 [20,21] Optimized ®lms display predominantly SiN±H bonding, but there are IR-detectable Si±H groups as well. Upon annealing at temperatures greater than the 300°C deposition temperature, there is a loss of bonded hydrogen with an activation energy of 0.4 eV. For annealing at temperatures greater than 500°C, loss of bonded hydrogen continues, but additional absorption occurs in the Si±N bond stretching regime (see Fig. 6). Films optimized for gate dielectrics in MOS devices typically display bonded hydrogen concentrations, primary in SiN±H groups of 10±15 at.%, but show no detectable IR absorption in Si±H con®gurations. The SiH±H bonds were stable up to annealing temperatures of at least 1200°C [20]. 2.4. Top surface nitridation Top surface nitridation has also been accomplished by a 300°C plasma-assisted process in which the process pressure is reduced to 100 mTorr eectively changing the plasma reactor from a remote to an after-glow mode [11,12]. This process is used to form a nitride layer on the top surface of a previously deposited oxide dielectric. Fig. 7 indicates the intensity of the NKLL AES feature as a function of plasma exposure time for dierent process variations: (i) plasma excitation of an N2 /He mixture, and (ii) plasma excitation of
G. Lucovsky / Journal of Non-Crystalline Solids 254 (1999) 26±37
Fig. 6. Infra red absorption spectrum for plasma deposited hydrogenated silicon nitride ®lm: (i) as deposited at 300°C; (ii) after a post deposition 900°C rapid thermal anneal. The data have been plotted as absorbance as function of wavenumber (cmÿ1 ).
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Fig. 8. Secondary ion mass spectrometry depth pro®les for (i) the top surface N2 /He plasma nitridation process, and (ii) the combined top surface and interface N2 /He plasma nitridation processes. Data are plotted as concentration as function of depth (x) from the top surface.
He and down stream injection of N2 . ARXPS has demonstrated that nitridation is restricted to the top surface of the oxide ®lm [11]; this has been con®rmed by SIMS (see Fig. 8). 3. Results
Fig. 7. Dierential AES spectra (dN(E)/dE) as function of kinetic energy (E) for remote plasma-assisted top oxide surface nitridation.
This section of the paper discusses electrical measurements of MOS capacitors and FETs. It is organized into three parts which highlight respectively: (i) improvements in device performance associated with interface nitridation in MOS capacitors; (ii) quanti®cation of the stopping of boron out-diusion from p polycrystalline Si; and (iii) performance of electron (or `N channel') conducting metal oxide semiconductor (NMOS) and hole (or `P-channel') conducting metal oxide semiconductor (PMOS) ®eld eect transistors (FETs) with stacked ON gate dielectrics and nitrided Si±SiO2 interfaces, eectively MOSFETs with `NON' stacked dielectrics. All
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device structures were subjected to 30 s, 900°C rapid thermal anneals prior to the deposition of either Al or polycrystalline Si gate electrodes. 3.1. Interface nitridation in MOS capacitors Fig. 9(a)±(c) present current±voltage characteristics for NMOS and PMOS structures with and without nitrided interfaces. The plots in Fig. 9(a) indicate that reductions in tunneling current increase as interface nitridation is increased with an apparent saturation of the eect occurring for monolayer coverage. The plots in Fig. 9(b) and (c) are for monolayer interface nitridation. Capacitance as a function of voltage (C(V)) measurements of the devices in Fig. 9 indicate that oxide-equivalent capacitance is essentially the same for each pair of devices in Fig. 9(b) and (c), and the group of devices in Fig. 9(a) so that the pairs of devices in Fig. 9(b) and (c) and the groups of devices in Fig. 9(a), respectively have essentially the same thickness to 0.1 nm. The eect of interface nitridation is to reduce tunneling. There are several aspects of this data that are now highlighted: the fractional reduction of tunneling current (i) saturates at a level of monolayer coverage; (ii) is independent of the injection direction, substrate or gate electrode; (iii) is independent for the gate electrode material; and (iv) is independent of oxide thickness, showing essentially the same property in the Fowler±Nordheim (Fig. 9(a)) and direct tunneling (Fig. 9(b) and (c)) regimes. These data are consistent with a tunneling electron mass of 0.5 mO , and a conduction band oset energy of 3.1 eV. 3.2. Suppression of boron atom transport for PMOS devices The minimum thickness of silicon nitride in contact with a p polycrystalline gate electrode that is needed to stop boron out-diusion during a high-temperature dopant activation anneal (900± 1050°C) has been found to be 0.8 nm, or approximately 2 molecular layers, corresponding to a nitrogen atom areal density of 4.5 ´ 1015 cmÿ2 . The areal density of nitrogen atoms is determined from the physical density of the nitride material (3.1 gm cmÿ1 ) and mass of one molecular unit of
Fig. 9. Current density (Jg ) as a function of applied voltage (Vg ) for capacitors with: (a) tox 4.5 nm, and (b) tox 3 and 2 nm, and (c) tox 2.5 nm. tox is the oxide thickness determined from capacitance measurements (C(V)).
G. Lucovsky / Journal of Non-Crystalline Solids 254 (1999) 26±37
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Si3 N4 (140 g). Fig. 10 indicates C(V) traces for capacitors that have dierent thicknesses of optimized plasma-deposited and annealed nitride layers, and for an oxide layer without a nitride capping layer. The eect of boron transport out of the p polycrystalline Si is to shift the C(V) to more positive capacitances, i.e., to increase both the ¯at band and threshold voltages. The C(V) for top nitride ®lms thicker than 0.8 nm is at the same position as the C(V) for nitride ®lms that are 0.8 nm thick. Note that 0.4 nm of nitride yields a C(V)
intermediate between that of a dielectric with an 0.8 nm nitride layer, and the oxide dielectric indicating that boron transport has occurred. Fig. 11(a) and (b) indicate a series of experiments that provide insight into the boron blocking mechanism of the 0.8 nm nitride ®lms. The traces in Fig. 11(a) are for PMOS devices in which the thickness of the top nitride or oxynitride layer has been ®xed at 0.8 nm; i.e., (i) an 0.8 nm nitride ®lm; (ii) two ®lms with 8 nm thick oxynitride alloy ®lms with compositions of 30% and 70% SiO2 ; (iii) a
Fig. 10. Normalized quasi-static C(V) curves for devices with a 4.7 nm thermal oxide and 0.4 and 0.8 nm top nitrides deposited onto thermal oxides 4.7 and 4.0 nm thermal oxides. Curves are shifted to higher voltages due to boron penetration through thin gate material. The dopant activation annealing is 1000°C for 60 s.
Fig. 11. C(V) traces for dierent top surface nitrided barrier layers. Each set of traces has an oxide dielectric for reference (No. 1) in which the ¯at band voltage has been shifted to positive values by B atom penetration to the Si±SiO2 interface. Each set of traces also includes an 0.8 mn nitride layer (No. 2) which eectively completely suppresses B atom transport. The traces in (a) are for a ®xed barrier layer thickness of 0.8 nm, and the those in (b) are for a ®xed area density of nitrogen atoms, 4.5 ´ 1015 cmÿ2 . The curves are plotted as normalized capacitance (C/Cox ) as a function of applied gate electrode bias (Vg ).
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control oxide. A similar set of traces is included in Fig. 11(b), where instead of top layer thickness being held constant, the top layer nitride atom areal density was at a level corresponding to 0.8 nm of nitride (4.5 ´ 1015 cmÿ2 ). The eects of nitrogen penetration are referenced to the oxide layers. Note that keeping the areal density ®xed, and increasing oxynitride alloy thickness is more eective than keeping top layer thickness constant and increasing the SiO2 alloy fraction. Studies made on n-type substrates, but using Al, rather than p polycrystalline Si gate electrodes indicated that ®xed charge levels were at most in the low 1011 cmÿ2 regime. As such, shifts in ¯at band voltage relative to those calculated from the substrate and polycrystalline Si doping doping, were signi®cantly smaller than the shifts in ¯at band voltage due to boron penetration to the Si±SiO2 interface. Additionally, shifts in ¯at band voltage due to ®xed positive charge are in the opposite direction to shifts to boron penetration to the Si±SiO2 interface, so that these would tend to decrease the quantitative ¯at band voltage shifts in Fig. 11(a) and (b). 3.3. Properties of NMOS and PMOS FETs Plasma-deposited nitride layers have incorporated into NMOS and PMOS FETs and have been discussed at some length in Refs. [14,15], respectively. FETs include nitrided Si±SiO2 interfaces formed either by remote plasma-oxidation in N2 O [23], or by nitrogen atom transport to the Si±SiO2 interface during nitride ®lm deposition [15]. The devices studied therefore had `NON' stacked gate dielectrics. Devices were made with dierent oxide and nitride layer thicknesses, and with tox-eq ranging from about 1.8 to 3.5 nm. In all instances the following results were obtained: (i) transistor drive currents were determined by tox-eq , or equivalently, the capacitance of the dielectric layer, (ii) reliability in was improved with respect to oxide dielectrics with the same tox-eq , and ®nally (iii) direct tunneling leakage was reduced for the stacked NON structures. These three aspects of PMOS FETs are illustrated respectively in Fig. 12(a), (b) and (c).
3.4. Nitrided interfaces PMOS devices with single layer optimized nitride gate dielectrics perform very badly showing threshold shifts of about 1 V and saturated mobility degradations of about 50, whereas NMOS devices show much reduced threshold voltage shifts, and mobility degradations of about 2. The mobility degradations are referenced to devices with Si±SiO2 interfaces, and sucient nitriding of the top surface of the oxide to suppress boron outdiusion during dopant activation. 4. Discussion 4.1. Control of nitrogen pro®les The experimental data presented above have shown that remote plasma-assisted processing combining (i) plasma-assisted oxidation, (ii) plasma-assisted interface and top surface nitridation, and (iii) plasma-assisted ®lm deposition can control nitrogen pro®les in ultra thin gate dielectrics with tox-eq extending to at least 1.8 nm. The nitrogen concentrations have been determined by SIMS and AES. Localization of N atoms at the Si±SiO2 interface has been determined by AES and con®rmed by ARXPS [18] and optical second harmonic generation [23]. 4.2. Si±SiO2 interface nitridation Si±SiO2 interface nitridation is important in the formation of ultra thin stacked oxide±nitride gate dielectrics. The experimental data in Refs. [2,14,15], and displayed in Figs. 9 and 12 indicate that interface nitridation reduces tunneling currents and improves device reliability as well. 4.3. Improvements in NMOS and PMOS devices with NON gate dielectrics Improvements in NMOS and PMOS FETs with ultra-thin stacked NON gate dielectrics have been published in Refs. [14,15]. Devices with stacked NON gate dielectrics will be integrated into commercial CMOS devices within the next 2±3 yr,
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initially for state of the art microprocessors, and eventually in memory devices [1]. 4.4. Limitations on interface nitridation Experiments described in Ref. [24] have established that devices with nitride gate dielectrics do not perform as well as stacked NON devices with interfacial oxide layers as thin as 0.5±0.6 nm. The performance of PMOS devices is signi®cantly poorer than NMOS devices indicating that defects at the Si±Si3 N4 interface derive from states in the lower half of the band gap that are positively charged when the Fermi level resides close to the valence band edge (see Fig. 13(a) and (b)). Although these states have not been identi®ed by spectroscopic techniques, it is likely that they are Si-atom dangling bonds, that cannot be compensated by hydrogen due to sterio-chemical constraints. 5. Conclusions The results presented above have demonstrated that stacked ON gate dielectrics with nitrided interfaces can play an important role in meeting SIA Technology Roadmap goals [1]. For example, stacked ON gate dielectrics possess all of the potential advantages for gate dielectric nitridation; (i) interface nitridation improves performance and reliability, (ii) bulk nitride incorporation allows for increased physical thickness without increases oxide equivalent thickness and decreases in capacitance, and (iii) top surface nitride layers block B-atom transport out of boron doped p polycrystalline silicon gate electrodes. Preliminary studies have shown that ON gate dielectrics are
Fig. 12. Properties of PMOS FETs with ON gate dielectrics. Comparisons are made with an FET with a control oxide: (a) drain current (Id ) as a function of drain voltage (Vd ) for different normalized gate voltages, (Vg ÿVth ), where Vg is the gate voltage and Vth is the threshold voltage, (b) a Weibull statistical plot charge to breakdown (Qbd ), and (c) substrate injection tunneling current plotted as function tunneling current density (Jg ) as function of the voltage across the oxide, Vg ÿVth , where Vg is the gate voltage and Vth is the threshold voltage.
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G. Lucovsky / Journal of Non-Crystalline Solids 254 (1999) 26±37
compatible with elemental and compound metal gate electrodes such as TiNx for PMOS [24]. Based on the research reported to date, stacked ON structures with physical thicknesses of 2 nm, and tox-eq 1.5 nm should meet SIA Technology Roadmap goals projected to the 2006±2009 time frame [24]. It is likely that a remote plasma processing tool that can be used to form these structures will emerge in the not-too-distant future. Acknowledgements Support from ONR, SRC and SEMATECH is acknowledged. In addition, this work is based on collaborations with graduate students and postdoctoral fellows at North Carolina State University, including, David Lee, Chris Parker, Hiro Niimi, and Yider Wu, and draws heavily on earlier publications. Collaborations with Professors John Hauser and Veena Misra are also acknowledged. References
Fig. 13. (a) C(V) measurements showing (i) shifts in ¯at band voltage due to positive charge, and (ii) increased separation between high frequency and quasi-static plots due to interface trapping, both resulting from direct deposition of thin nitride ®lms onto Si prior to deposition of gate oxides. (b) Plots of drain current (Id ) as a function of gate voltage (Vg ) characteristics for PMOSFETs with (i) a 4 nm nitride layer, (ii) a 0.6 nm oxide separating a 2.4 nm nitride from the Si substrate, and (iii) a 1.5 nm oxide separating a 1.0 nm nitride from the Si substrate. The threshold voltage shift between (ii) and (iii) is due in part to substrate doping dierences (0.16 V) and in part to positive charge at the internal oxide±nitride interface (0.04 eV).
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G. Lucovsky / Journal of Non-Crystalline Solids 254 (1999) 26±37 [13] Y. Wu, G. Lucovsky, AIP Conf. Proc. 449 (1998) 293. [14] C.R. Parker, G. Lucovsky, J.R. Hauser, IEEE Electron Device Letters 19 (1998) 106. [15] Y. Wu, G. Lucovsky, IEEE Electron Device Lett. 19 (1998) 367. [16] G. Lucovsky, D.V. Tsu, R.A. Rudder, J. Markunas, in: J.L. Vossen, W. Kern (Eds.), Thin Film Processes II, Academic Press, Boston, 1991, p. 565. [17] T. Yasuda, Y. Ma, S. Habermehl, G. Lucovsky, Appl. Phys. Lett. 60 (1992) 434. [18] B.C. Smith, H.H. Lamb, J. Appl. Phys. 83 (1998) 7635. [19] H. Niimi, G. Lucovsky, AIP Conf. Proc. 449 (1998) 297.
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[20] Z. Lu, M.J. Williams, P.F. Santos-Filho, G. Lucovsky, J. Vac. Sci. Technol. A 13 (1995) 607. [21] G. Lucovsky, P. Santos-Filho, G. Stevens, Z. Jing, A. Banerjee, J. Non-Cryst. Solids 198±200 (1996) 19. [22] Yi Ma, T. Yasuda, G. Lucovsky, Appl. Phys. Lett. 64 (1994) 2226. [23] G. Lucovsky, H. Niimi, K. Koh, D.R. Lee, Z. Jing, in: H.Z. Massoud, E.H. Poindexter, C.R. Helms (Eds.), The Physics and Chemistry of SiO2 and the Si±SiO2 Interface, Electrochemical Soc., Pennington, 1996, p. 441. [24] B. Cla¯in, M. Binger, G. Lucovsky, J. Vac. Sci. Technol. A 16 (1998) 1757.
www.elsevier.com/locate/jnoncrysol
Silicon oxide/silicon nitride dual-layer ®lms: a stacked gate dielectric for the 21st century Gerald Lucovsky * Departments of Physics, Electrical and Computer Engineering, and Materials Science and Engineering, North Carolina State University, Raleigh, NC 27695-8202, USA
Abstract Incorporation of nitrogen atoms into ultra thin (<0.3 nm) gate dielectrics (i) reduces defect generation at the Si±SiO2 interface, (ii) allows use of physically thicker dielectrics when incorporated into oxide±nitride stacked gate dielectrics, and (iii) prevents boron atom transport out of heavily doped p polycrystalline silicon gate electrodes when nitrided layers are incorporated at the polycrystalline Si-dielectric interface. I demonstrate that nitrogen atoms can be selectively and independently incorporated into dierent parts of the gate dielectric structure by low-temperature (300°C) remote plasma assisted processing followed by low-thermal budget rapid thermal annealing (RTA) yielding state of the art ®eld eect transistors with oxide equivalent thicknesses less than 2 nm. Ó 1999 Elsevier Science B.V. All rights reserved.
1. Introduction As lateral device dimensions are scaled into the submicron regime <100 nm to achieve greater levels of speed and integration, there must be corresponding decreases in the oxide-equivalent thickness of dielectrics, tox-eq , to <2 nm to maintain current levels needed for circuit operation [1]. Direct tunneling currents increase exponentially with decreasing oxide layer thickness establishing a limitation of the use of SiO2 as a gate dielectric. As an example, an oxide thickness of 3 nm and less de®nes the regime of ultra thin oxides in which direct tunneling is the dominant mechanism for current transport through the oxide ®lm, and a practical limitation for oxides is tox-eq 1.6 nm, the thickness at which the direct tunneling current
* Tel.: +1-919 515 3301/3468; fax: +1-919 515 7331; e-mail: [email protected]
reaches a level of 1 A cmÿ2 for an oxide bias of 1 V. The technology challenge is to increase the physical thickness of gate dielectrics to reduce tunneling current while maintaining a tox-eq that corresponds to a signi®cantly thinner SiO2 ®lm by using alternative insulators with dielectric constants larger than SiO2 . These alternative dielectrics include silicon nitride, Si3 N4 , as well as other metal binary and ternary oxides such as Ta2 O5 and ZrSiO4 , respectively. These alternative dielectrics can be incorporated into stacked structures, such as the oxide±nitride, ON, composites, as well as including other alternative larger-K materials such as TiO2 or Ta2 O5 in combination with either Si±SiO2 or nirtided Si±SiO2 interfaces. This paper considers on the nitrided oxides, in particular stacked ON structures with nitrided Si± SiO2 interfaces, and does not address the alternative larger-K materials. Spatially selective incorporation of nitorgen (N) atoms into advanced gate dielectrics (i) reduces
0022-3093/99/$ ± see front matter Ó 1999 Elsevier Science B.V. All rights reserved. PII: S 0 0 2 2 - 3 0 9 3 ( 9 9 ) 0 0 4 3 2 - 9
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defect generation at the Si±SiO2 interface when N-atoms incorporated at monolayer concentrations [2±6], (ii) allows the use of physically thicker stacked dielectrics when silicon nitride layers are incorporated into the body of gate dielectric as in ON stacks, [7±10], and (iii) reduces boron (B) atom penetration out of doped p polycrystalline silicon gate electrodes through the dielectric ®lms to the Si±SiO2 interface when the nitride layers are at the polycrystalline Si-dielectric interface [11±13]. This paper presents research results from a program at North Carolina State University that have demonstrated separate and independent control of Natom incorporation in these dierent parts of oxide gate dielectrics through combined use of plasma-assisted processing at 300°C, and lowthermal-budget rapid thermal annealing (RTA), e.g., 30 s at 900°C [2,6±11,13±15]. This review is restricted to devices prepared by remote plasma processing, and will not describe formation of nitrided gate dielectrics by thermal processing, direct plasma processing, jet vapor deposition, or other physical vapor deposition techniques such as reactive sputtering or evaporation. 2. Experimental procedures 2.1. Remote plasma processing Fig. 1 is a schematic of a prototypical remote plasma processing chamber that has been used for Si±SiO2 interface formation, SiO2 and silicon nitride, Si3 N4 ®lm deposition, and Si±SiO2 interface and SiO2 top-surface nitridation [16]. Plasma assisted activation of reactive species for plasma processing has been achieved by radio frequency, rf, excitation at 13.56 MHz, and typically at power levels from 15 to 60 W. The coupling to the plasma is capacitive with the `coil' being the hot electrode, and the metal plate at the top of the chamber being grounded. The same basic chamber design has been implemented into several dierent multichamber systems (e.g., see Ref. [10]), that include additional chambers for (i) surface chemical analysis by Auger electron spectroscopy, AES, and (ii) RTA. The remote plasma processing chamber provides gas introduction through a plasma
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Fig. 1. Schematic diagram of remote plasma processing chamber.
excitation tube, as well as by downstream injection through showerhead dispersal rings. Remote plasma processing is dierentiated from conventional or direct plasma processing in three ways: (i) it provides selective excitation of source and carrier gases as determined by their point of injection into the system, either through the plasma tube, or through the downstream showerhead injection ring; (ii) the deposition substrate is outside of the plasma glow region; (iii) the source gases injected downstream from the plasma generation region are prevented from back-streaming into the plasma generation region by gas ¯ow and process pressure [16]. In addition, several of these plasma chambers have been ®xtured for in situ process diagnostics, including mass spectrometry, MS, and optical emission spectroscopy, OES. The implementation of remote plasma processing chambers into multi-chamber systems has made it possible (i) to interrupt plasma-assisted oxidation, nitridation and/or deposition processes and then, without removing the sample from a ultra-high-vacuum, UHV, compatible environment, to perform on-line chemical analysis by AES and (ii) to integrate online sequences of plasma processing with RTA. These devices utilize four 300°C remote plasmaassisted processes and RTA states that are outlined in Table 1: (i) plasma-assisted oxidation for
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Table 1 Process steps for forming device-quality stacked gate oxide dielectrics Process step
Process conditions
Processing results
(a) Remote plasmaassisted oxidation
Substrate temperature 300°C; process pressure 300 mTorr; plasma excited mixture He/O2 (200 sccm He, 20 sccm O2 ); time 15±30 s
(b) Remote plasmaenhanced CVD (c) Remote plasmaassisted interface nitridation
Substrate temperature 300°C; process pressure 300 mTorr; plasma excited mixture He/O2 (200 sccm He/ 20 sccm O2 ); down-stream mixture He/SiH4 (20 sccm He/0.4 sccm SiH4 ) Substrate temperature 300°C; process pressure 300 mTorr; plasma excited mixture He/N2 (160 sccm He, 60 sccm N2 ); time 90 s
(d) Remote plasmaassisted top surface nitridation
Substrate temperature 300°C; process pressure 100 mTorr; plasma excited mixture He/N2 (200 sccm He, 20 sccm N2 ); time 10±20 min
In situ substrate cleaning (reduces C and F level); forms Si±SiO2 interface; grows passiviting oxide 0.5 nm; introduces sub-oxide bonding at Si±SiO2 interface Forms body of dielectric ®lm; deposition rate 2.5±5.0 nm/min; stoichiometric SiO2 NO-IR detectable Si±H or Si±OH Low Si±OH (n5 at.% H) Inserts approximately one monolayer of nitrogen atoms at Si±SiO2 interface; nitrogen is localized at interface; nitrogen concentration scales with time Forms 2 molecular layers of silicon nitride at top surface of a plasma or thermally-grown oxide; sucient to suppress boron diusion
(e) Rapid thermal annealing
Temperate: 900°C Time: 30 seconds Low pressure or atmospheric inert gas ambident (e.g., Ar)
Reduces oxidation induced sub-oxide bonding at Si±SiO2 interface; promotes densi®cation of oxide ®lms; reduces bonded-H (mostly in nitrides)
Si±SiO2 interface formation, (ii) plasma-assisted interface nitridation, (iii) plasma-assisted nitridation of oxide top surfaces, (iv) plasma-assisted deposition of `bulk' oxide and nitride ®lms; i.e., remote plasma-enhanced chemical-vapor deposition (RPECVD), and (v) RTA. Additionally, PMOS structures have been fabricated in which nitride ®lms have been deposited directly onto to hydrogen terminated Si surfaces. Two types of structures were fabricated ± devices with (i) nitride layers 4 nm, thick and (ii) nitride layers of 0.4 and 0.8 nm which were over coated with 4 nm of plasma-deposited SiO2 . 2.2. Interface characterization The primary tools for interface measurements have been on-line AES, and o-line secondary ion mass spectrometry, SIMS. Figs. 2 and 3, respectively, display (i) AES results for an interrupted interface nitridation process and (ii) SIMS results for dierent interface nitridation exposure times using CsN detection. The AES spectra of Fig. 2 indicate no NKLL feature after an initial oxidation process that produces 0.5 0.1 nm of oxide as
Fig. 2. Time evolution of dierential counting rate (dn(E)/dE) for Auger electron spectroscopy (AES) spectra as a function of kinetic energy (E), for the O2 remote plasma-assisted oxidation process combined with post-oxidation nitridation from an N2 /He plasma for dierent exposure times.
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Fig. 3. Secondary ion mass spectrometry (SIMS) depth pro®les for the N2 /He plasma nitridation process. The plasma processed interface has been over coated with 5 nm of plasma-deposited SiO2 . The intensity of the SIMS intensity is plotted as function of the depth (x) from the surface of the sample.
determined from the ratio of the amplitude of SiLVV oxide feature at 76 eV to that of the SiLVV substrate feature at 91 eV, using a nominal electron escape depth of 0.6 nm [17]. By taking measurements at several points on the wafer, it was determined that the thickness of the plasma-grown oxide was uniform to 0.1 nm. This uniformity is further con®rmed by electrical measurements. As the exposure time to the upstream N2 /He plasma is increased, a NKLL feature emerges and increases in intensity with increasing exposure time. The SIMS data are also for dierent interface nitridation times. The nitrided interfacial oxide of Fig. 3 has been over coated with approximately 5 nm of SiO2 . The nitrogen atom concentration is obtained by integration of the CsN signal. This data reduction analysis shows a linear increase of the integrated peak signal as a function of exposure time, with a time of 90 s yielding approximately one monolayer of N atom coverage (see Fig. 4). There is still some controversy with regard to the correct way to normalize the SIMS results, i.e., using the relative
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Fig. 4. Normalized nitrogen concentration obtained from integration of SIMS pro®les versus nitridation time (t). The value of one (1) corresponds to approximately (10%) one monolayer of interfacial nitrogen atoms.
sensitivity factor for N atoms in SiO2 or crystalline Si. Since these dier by a factor of more than 2, this is the primary source of uncertainty in determining N-atom areal density concentrations. The normalization of this paper has utilized the approach of Ref. [2], which established that monolayer interface nitridation could also be achieved by plasma-assisted nitridation using N2 O as the source gas. Interfacial nitridation, as de®ned above, means that N atoms are bonded directly to the Si substrate and provide a chemical bridge between that substrate and the plasma-grown SiO2 layer. The concentration of nitrogen atoms is equal to the surface concentration of Si atoms on the (1 0 0) face, 7 ´ 1014 cmÿ2 . This monolayer concentration was further con®rmed by nuclear reaction analysis which gave a nitrogen areal density of 8 1 ´ 1014 cmÿ2 [18]. Interfacial nitridation by this approach has also been con®rmed by angle resolved X-ray photoelectron spectroscopy (ARXPS) studies [19]. The plot in Fig. 5 establishes that the N-atoms injected into the oxidized layer by exposure to the N2 /He plasma products are localized at the
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Fig. 5. Comparison of (i) the ratio of the amplitudes of the NKLL and substrate SiLVV feature peaks (N/Si ratio) as a function of nitridation time (t), and (ii) the amplitude of the NKLL feature peak as a function of nitridation time (t).
Si±SiO2 interface. This is con®rmed by noting ®rst that a plot of the intensity of the NKLL AES feature versus time is sublinear, but that a plot of the ratio of the intensities of the NKLL and SiLVV substrate AES features is linear. The lack of linearity for the NKLL versus time plot derives from increases in dielectric layer thickness with increasing nitridation time, and normalization by the substrate SiLVV feature takes this into account. 2.3. Nitride ®lm properties Device grade silicon nitride ®lms have been prepared by RPECVD at 300°C using either N2 or HN3 as the source gas for N, and SiH4 as the source gas for Si. Previous publications have considered the local atomic bonding of Si, N and H in these ®lms as a function of the source gas mixtures, e.g., the ratio of NH3 to SiH4 [6± 9,20,21]. As-deposited ®lms deposited from 10 : 1 NH3 /SiH4 mixtures provided optimized performance as a gate dielectric for thin ®lm transistors [21], whereas annealing these ®lms at 400±450°C and using them as a constituent layer in stacked oxide±nitride±oxide (ONO) gate dielectrics yields marginal performance [6±9]. On the other hand,
annealing the ONO stacks at 900°C for approximately 30 s in an inert ambient, e.g., Ar, results in excellent device performance with reliability generally exceeding oxide dielectrics with the same oxide equivalent thickness [22]. These dierences in performance have been resolved by employing AES and infrared spectroscopy for chemical measurements [21]. The optimized as-deposited ®lms display only Si±N bonding by on-line AES, whereas, as shown in Ref. [21], the ®lms deposited with lower ¯ow rates of NH3 or N2 to SiH4 are sub-nitrides with both Si±Si and Si±N bonds detected by AES. Also, shown in Ref. [21], bonded hydrogen occurs predominantly as Si±H in the sub-nitrides, whereas SiN±H groups dominate in the hydrogenated nitrides. Typical bonded hydrogen concentrations in the as-deposited ®lms are 20 at.% for ®lms grown from N2 , and 28 at.% for ®lms grown from NH3 [20,21] Optimized ®lms display predominantly SiN±H bonding, but there are IR-detectable Si±H groups as well. Upon annealing at temperatures greater than the 300°C deposition temperature, there is a loss of bonded hydrogen with an activation energy of 0.4 eV. For annealing at temperatures greater than 500°C, loss of bonded hydrogen continues, but additional absorption occurs in the Si±N bond stretching regime (see Fig. 6). Films optimized for gate dielectrics in MOS devices typically display bonded hydrogen concentrations, primary in SiN±H groups of 10±15 at.%, but show no detectable IR absorption in Si±H con®gurations. The SiH±H bonds were stable up to annealing temperatures of at least 1200°C [20]. 2.4. Top surface nitridation Top surface nitridation has also been accomplished by a 300°C plasma-assisted process in which the process pressure is reduced to 100 mTorr eectively changing the plasma reactor from a remote to an after-glow mode [11,12]. This process is used to form a nitride layer on the top surface of a previously deposited oxide dielectric. Fig. 7 indicates the intensity of the NKLL AES feature as a function of plasma exposure time for dierent process variations: (i) plasma excitation of an N2 /He mixture, and (ii) plasma excitation of
G. Lucovsky / Journal of Non-Crystalline Solids 254 (1999) 26±37
Fig. 6. Infra red absorption spectrum for plasma deposited hydrogenated silicon nitride ®lm: (i) as deposited at 300°C; (ii) after a post deposition 900°C rapid thermal anneal. The data have been plotted as absorbance as function of wavenumber (cmÿ1 ).
31
Fig. 8. Secondary ion mass spectrometry depth pro®les for (i) the top surface N2 /He plasma nitridation process, and (ii) the combined top surface and interface N2 /He plasma nitridation processes. Data are plotted as concentration as function of depth (x) from the top surface.
He and down stream injection of N2 . ARXPS has demonstrated that nitridation is restricted to the top surface of the oxide ®lm [11]; this has been con®rmed by SIMS (see Fig. 8). 3. Results
Fig. 7. Dierential AES spectra (dN(E)/dE) as function of kinetic energy (E) for remote plasma-assisted top oxide surface nitridation.
This section of the paper discusses electrical measurements of MOS capacitors and FETs. It is organized into three parts which highlight respectively: (i) improvements in device performance associated with interface nitridation in MOS capacitors; (ii) quanti®cation of the stopping of boron out-diusion from p polycrystalline Si; and (iii) performance of electron (or `N channel') conducting metal oxide semiconductor (NMOS) and hole (or `P-channel') conducting metal oxide semiconductor (PMOS) ®eld eect transistors (FETs) with stacked ON gate dielectrics and nitrided Si±SiO2 interfaces, eectively MOSFETs with `NON' stacked dielectrics. All
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device structures were subjected to 30 s, 900°C rapid thermal anneals prior to the deposition of either Al or polycrystalline Si gate electrodes. 3.1. Interface nitridation in MOS capacitors Fig. 9(a)±(c) present current±voltage characteristics for NMOS and PMOS structures with and without nitrided interfaces. The plots in Fig. 9(a) indicate that reductions in tunneling current increase as interface nitridation is increased with an apparent saturation of the eect occurring for monolayer coverage. The plots in Fig. 9(b) and (c) are for monolayer interface nitridation. Capacitance as a function of voltage (C(V)) measurements of the devices in Fig. 9 indicate that oxide-equivalent capacitance is essentially the same for each pair of devices in Fig. 9(b) and (c), and the group of devices in Fig. 9(a) so that the pairs of devices in Fig. 9(b) and (c) and the groups of devices in Fig. 9(a), respectively have essentially the same thickness to 0.1 nm. The eect of interface nitridation is to reduce tunneling. There are several aspects of this data that are now highlighted: the fractional reduction of tunneling current (i) saturates at a level of monolayer coverage; (ii) is independent of the injection direction, substrate or gate electrode; (iii) is independent for the gate electrode material; and (iv) is independent of oxide thickness, showing essentially the same property in the Fowler±Nordheim (Fig. 9(a)) and direct tunneling (Fig. 9(b) and (c)) regimes. These data are consistent with a tunneling electron mass of 0.5 mO , and a conduction band oset energy of 3.1 eV. 3.2. Suppression of boron atom transport for PMOS devices The minimum thickness of silicon nitride in contact with a p polycrystalline gate electrode that is needed to stop boron out-diusion during a high-temperature dopant activation anneal (900± 1050°C) has been found to be 0.8 nm, or approximately 2 molecular layers, corresponding to a nitrogen atom areal density of 4.5 ´ 1015 cmÿ2 . The areal density of nitrogen atoms is determined from the physical density of the nitride material (3.1 gm cmÿ1 ) and mass of one molecular unit of
Fig. 9. Current density (Jg ) as a function of applied voltage (Vg ) for capacitors with: (a) tox 4.5 nm, and (b) tox 3 and 2 nm, and (c) tox 2.5 nm. tox is the oxide thickness determined from capacitance measurements (C(V)).
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Si3 N4 (140 g). Fig. 10 indicates C(V) traces for capacitors that have dierent thicknesses of optimized plasma-deposited and annealed nitride layers, and for an oxide layer without a nitride capping layer. The eect of boron transport out of the p polycrystalline Si is to shift the C(V) to more positive capacitances, i.e., to increase both the ¯at band and threshold voltages. The C(V) for top nitride ®lms thicker than 0.8 nm is at the same position as the C(V) for nitride ®lms that are 0.8 nm thick. Note that 0.4 nm of nitride yields a C(V)
intermediate between that of a dielectric with an 0.8 nm nitride layer, and the oxide dielectric indicating that boron transport has occurred. Fig. 11(a) and (b) indicate a series of experiments that provide insight into the boron blocking mechanism of the 0.8 nm nitride ®lms. The traces in Fig. 11(a) are for PMOS devices in which the thickness of the top nitride or oxynitride layer has been ®xed at 0.8 nm; i.e., (i) an 0.8 nm nitride ®lm; (ii) two ®lms with 8 nm thick oxynitride alloy ®lms with compositions of 30% and 70% SiO2 ; (iii) a
Fig. 10. Normalized quasi-static C(V) curves for devices with a 4.7 nm thermal oxide and 0.4 and 0.8 nm top nitrides deposited onto thermal oxides 4.7 and 4.0 nm thermal oxides. Curves are shifted to higher voltages due to boron penetration through thin gate material. The dopant activation annealing is 1000°C for 60 s.
Fig. 11. C(V) traces for dierent top surface nitrided barrier layers. Each set of traces has an oxide dielectric for reference (No. 1) in which the ¯at band voltage has been shifted to positive values by B atom penetration to the Si±SiO2 interface. Each set of traces also includes an 0.8 mn nitride layer (No. 2) which eectively completely suppresses B atom transport. The traces in (a) are for a ®xed barrier layer thickness of 0.8 nm, and the those in (b) are for a ®xed area density of nitrogen atoms, 4.5 ´ 1015 cmÿ2 . The curves are plotted as normalized capacitance (C/Cox ) as a function of applied gate electrode bias (Vg ).
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control oxide. A similar set of traces is included in Fig. 11(b), where instead of top layer thickness being held constant, the top layer nitride atom areal density was at a level corresponding to 0.8 nm of nitride (4.5 ´ 1015 cmÿ2 ). The eects of nitrogen penetration are referenced to the oxide layers. Note that keeping the areal density ®xed, and increasing oxynitride alloy thickness is more eective than keeping top layer thickness constant and increasing the SiO2 alloy fraction. Studies made on n-type substrates, but using Al, rather than p polycrystalline Si gate electrodes indicated that ®xed charge levels were at most in the low 1011 cmÿ2 regime. As such, shifts in ¯at band voltage relative to those calculated from the substrate and polycrystalline Si doping doping, were signi®cantly smaller than the shifts in ¯at band voltage due to boron penetration to the Si±SiO2 interface. Additionally, shifts in ¯at band voltage due to ®xed positive charge are in the opposite direction to shifts to boron penetration to the Si±SiO2 interface, so that these would tend to decrease the quantitative ¯at band voltage shifts in Fig. 11(a) and (b). 3.3. Properties of NMOS and PMOS FETs Plasma-deposited nitride layers have incorporated into NMOS and PMOS FETs and have been discussed at some length in Refs. [14,15], respectively. FETs include nitrided Si±SiO2 interfaces formed either by remote plasma-oxidation in N2 O [23], or by nitrogen atom transport to the Si±SiO2 interface during nitride ®lm deposition [15]. The devices studied therefore had `NON' stacked gate dielectrics. Devices were made with dierent oxide and nitride layer thicknesses, and with tox-eq ranging from about 1.8 to 3.5 nm. In all instances the following results were obtained: (i) transistor drive currents were determined by tox-eq , or equivalently, the capacitance of the dielectric layer, (ii) reliability in was improved with respect to oxide dielectrics with the same tox-eq , and ®nally (iii) direct tunneling leakage was reduced for the stacked NON structures. These three aspects of PMOS FETs are illustrated respectively in Fig. 12(a), (b) and (c).
3.4. Nitrided interfaces PMOS devices with single layer optimized nitride gate dielectrics perform very badly showing threshold shifts of about 1 V and saturated mobility degradations of about 50, whereas NMOS devices show much reduced threshold voltage shifts, and mobility degradations of about 2. The mobility degradations are referenced to devices with Si±SiO2 interfaces, and sucient nitriding of the top surface of the oxide to suppress boron outdiusion during dopant activation. 4. Discussion 4.1. Control of nitrogen pro®les The experimental data presented above have shown that remote plasma-assisted processing combining (i) plasma-assisted oxidation, (ii) plasma-assisted interface and top surface nitridation, and (iii) plasma-assisted ®lm deposition can control nitrogen pro®les in ultra thin gate dielectrics with tox-eq extending to at least 1.8 nm. The nitrogen concentrations have been determined by SIMS and AES. Localization of N atoms at the Si±SiO2 interface has been determined by AES and con®rmed by ARXPS [18] and optical second harmonic generation [23]. 4.2. Si±SiO2 interface nitridation Si±SiO2 interface nitridation is important in the formation of ultra thin stacked oxide±nitride gate dielectrics. The experimental data in Refs. [2,14,15], and displayed in Figs. 9 and 12 indicate that interface nitridation reduces tunneling currents and improves device reliability as well. 4.3. Improvements in NMOS and PMOS devices with NON gate dielectrics Improvements in NMOS and PMOS FETs with ultra-thin stacked NON gate dielectrics have been published in Refs. [14,15]. Devices with stacked NON gate dielectrics will be integrated into commercial CMOS devices within the next 2±3 yr,
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35
initially for state of the art microprocessors, and eventually in memory devices [1]. 4.4. Limitations on interface nitridation Experiments described in Ref. [24] have established that devices with nitride gate dielectrics do not perform as well as stacked NON devices with interfacial oxide layers as thin as 0.5±0.6 nm. The performance of PMOS devices is signi®cantly poorer than NMOS devices indicating that defects at the Si±Si3 N4 interface derive from states in the lower half of the band gap that are positively charged when the Fermi level resides close to the valence band edge (see Fig. 13(a) and (b)). Although these states have not been identi®ed by spectroscopic techniques, it is likely that they are Si-atom dangling bonds, that cannot be compensated by hydrogen due to sterio-chemical constraints. 5. Conclusions The results presented above have demonstrated that stacked ON gate dielectrics with nitrided interfaces can play an important role in meeting SIA Technology Roadmap goals [1]. For example, stacked ON gate dielectrics possess all of the potential advantages for gate dielectric nitridation; (i) interface nitridation improves performance and reliability, (ii) bulk nitride incorporation allows for increased physical thickness without increases oxide equivalent thickness and decreases in capacitance, and (iii) top surface nitride layers block B-atom transport out of boron doped p polycrystalline silicon gate electrodes. Preliminary studies have shown that ON gate dielectrics are
Fig. 12. Properties of PMOS FETs with ON gate dielectrics. Comparisons are made with an FET with a control oxide: (a) drain current (Id ) as a function of drain voltage (Vd ) for different normalized gate voltages, (Vg ÿVth ), where Vg is the gate voltage and Vth is the threshold voltage, (b) a Weibull statistical plot charge to breakdown (Qbd ), and (c) substrate injection tunneling current plotted as function tunneling current density (Jg ) as function of the voltage across the oxide, Vg ÿVth , where Vg is the gate voltage and Vth is the threshold voltage.
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compatible with elemental and compound metal gate electrodes such as TiNx for PMOS [24]. Based on the research reported to date, stacked ON structures with physical thicknesses of 2 nm, and tox-eq 1.5 nm should meet SIA Technology Roadmap goals projected to the 2006±2009 time frame [24]. It is likely that a remote plasma processing tool that can be used to form these structures will emerge in the not-too-distant future. Acknowledgements Support from ONR, SRC and SEMATECH is acknowledged. In addition, this work is based on collaborations with graduate students and postdoctoral fellows at North Carolina State University, including, David Lee, Chris Parker, Hiro Niimi, and Yider Wu, and draws heavily on earlier publications. Collaborations with Professors John Hauser and Veena Misra are also acknowledged. References
Fig. 13. (a) C(V) measurements showing (i) shifts in ¯at band voltage due to positive charge, and (ii) increased separation between high frequency and quasi-static plots due to interface trapping, both resulting from direct deposition of thin nitride ®lms onto Si prior to deposition of gate oxides. (b) Plots of drain current (Id ) as a function of gate voltage (Vg ) characteristics for PMOSFETs with (i) a 4 nm nitride layer, (ii) a 0.6 nm oxide separating a 2.4 nm nitride from the Si substrate, and (iii) a 1.5 nm oxide separating a 1.0 nm nitride from the Si substrate. The threshold voltage shift between (ii) and (iii) is due in part to substrate doping dierences (0.16 V) and in part to positive charge at the internal oxide±nitride interface (0.04 eV).
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