- Email: [email protected]
Smart-Cut® technology: from 300 mm ultrathin SOI production to advanced engineered substrates
Solid-State Electronics 48 (2004) 1055–1063 www.elsevier.com/locate/sse
Smart-Cut technology: from 300 mm ultrathin SOI production to advanced engineered substrates Christophe Maleville *, Carlos Mazure SOITEC SA, Parc Technologique Des Fontaines, Crolles Cedex 38926, France
The review of this paper was arranged by Prof. S. Cristoloveanu
Abstract The Smart-Cut process, based on hydrogen implantation and wafer bonding, is a generic thin layer process transfer. Unibond SOI wafers are today in volume production, showing that splitting and bonding steps can be controlled, with high yields. Taking advantage of standard equipments flexibility, the process has been successfully scaled up to 300 mm. Most advanced 200 mm processes were successfully transferred to 300 mm, with wafers showing uniformity and defectivity results compatible with industry requirements for fully depleted device applications. The number of wafer solutions offered by the Smart-Cut technology is already much greater than just SOI. Strained silicon on insulator, silicon on quartz (SOQ), single crystal silicon layer on plastic supports, silicon carbide on insulator, germanium on insulator, multilayer SOI structures are just few examples of the potential of Smart Cut to engineer and design new substrates to answer the demands of the industry. A review of the progress achieved is given. 2004 Elsevier Ltd. All rights reserved.
1. Introduction During the last decade, the substrate industry has 00 brought the 8 substrate technology to maturity with the introduction of Cop (crystal-originated particles) free wafers, and two major innovations at the substrate level have occurred: the development of 300 mm silicon has been the response to the 0.18 lm IC technology node with a more aggressive introduction for technologies below 100 nm, and SOI, silicon on insulator, has been the response to the IC requirements [1] of improved performance while reducing the parasitic substrate capacitances and leakage currents. The SOI substrates constitute without doubt a paradigm shift of the silicon IC industry. The early SOI days in the 70s and 80s as a niche substrate technology for military or space applications are long over. SIMOX, wafer bonding and grind back (BESOI), the first SOI wafer manufacturing technologies, have also strongly * Corresponding author. Tel.: +33-476-92-7584; fax: +33476-92-7501. E-mail address: [email protected] (C. Maleville).
improved during the past 10 years but the SOI boom arrived with the breakthrough made by the Smart-Cut technology [2] in the late 90s. Since then, commercial applications of SOI have grown exponentially, and entered the mainstream of UltraLarge Scale Integration (ULSI) ICs. The SOI wafer is a composite substrate with an active top Si layer decoupled from the support wafer. It is the first example of an engineered substrate addressing main-stream MOSFET performance requirements. The impact of SOI on partially and fully depleted devices, performance enhancement, reduction of leakage currents and power consumption, suitability for low voltage device architecture and so forth, have been very extensively studied for the past two decades [3–5]. But as the IC industry moves towards the development of the future 65, 45, 32 and 22 nm technology nodes, more innovations will be required at the substrate level towards the end of this decade, which will be driven mainly by the MOSFET design. The coupling between device architecture and composite substrate engineering will be stronger. The IC industry is experiencing a similar shift to the one seen in the 90s with the development of IC process modules by the equipment manufacturers.
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2003.12.029
1056
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
with consistent quality. Bernin facility, opened in 1998, is now running at full capacity, with 900k wafers starts per year. 200 mm experience is demonstrating production stability and Unibond products in all diameters up 00 to 12 are today qualified in production by IC manufacturers for applications ranging from thin films to thick films (Fig. 2). 2.1. 300 mm SOI wafer manufacturing
Fig. 1. The UNIBOND process is based on hydrogen implantation and wafer bonding to a handle substrate B. Hydrogen implantation induces formation of an in-depth weakened layer located at the mean ion penetration depth which leads to cleavage of a thin film from a donor substrate A.
Substrate engineering will increasingly become a key consideration for the device architecture and CMOS processing. Smart Cut is a bonding and thin layer transfer technique from a donor wafer onto a handle substrate [6–8]. The transferred layer thickness is pre-determined by the cleavage zone created via ion implantation (hydrogen, helium, argon, etc.). After the layer transfer, the cleaved surface of the thin film is treated, polished and annealed to ensure a silicon film and surface quality comparable to silicon prime wafers. The schematic process flow of Smart Cut SOI (UNIBOND ) is shown in Fig. 1. Its technological strength is the manufacturability of the Smart-Cut technology, the wide flexibility in top silicon and buried oxide thicknesses, the scalability to any wafer diameter, and the utilization of standard IC manufacturing equipment [9,10]. The Smart-Cut process was originally developed to manufacture SOI and has achieved a high degree of maturity with UNIBOND mass production [9,11,12], but its potential goes beyond SOI, in contrast to SIMOX. Smart Cut is a generic layer transfer technology that fills the gap between heteroepitaxy and single crystal thin film transfer to any type of substrate. It strongly enlarges the field of engineered composite substrates combining different thin layer materials on a given substrate to address the requirements of the most diverse applications. Smart-Cut technology is today the object of many studies and developments worldwide [13–19].
2. High volume SOI manufacturing Smart-Cut process has been the enabling technology, allowing large volume production of SOI wafers
Several IC suppliers are today in qualification and ramp-up of 300 mm fab running SOI based advanced applications. As the Smart-Cut process is based on standard semiconductor equipments, the transition from 200 to 300 mm has been enabled by the availability of the 300 mm toolset. 300 mm Unibond feasibility was demonstrated in 1997, samples were built in 2000, and a 300 mm pilot line is operating since January 2002. Now in a ramp-up, this first 300 mm experience proved that there was no major limitation for 300 mm Unibond . As 300 mm silicon wafers incorporate today the most advanced silicon wafer engineering, the SOI quality and manufacturability has been even improved when going to this new diameter. Nanotopography improvements are particularly beneficial. Table 1 gives a comparison in terms of equipment type and configuration for 200 and 300 mm lines. From a manufacturing point of view, the 300 mm line has been set up using the 200 mm experience and is really close to 200 mm line. The major change is in the carrier type since 300 mm wafers are handled in FOUP cassettes for all tools and all processing steps from incoming material to shipment.
Fig. 2. The UNIBOND process technological strength is the compatibility with mass production, the wide flexibility in top Si and buried oxide thicknesses definition, the scalability to any wafer diameter, the utilization of standard IC manufacturing equipment. Wafer size requirements for ULSI partially or fully depleted device architecture is 200 and 300 mm, while for MEMS, MOEMS, and Smart Power it is typically between 100 and 150 mm.
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
1057
Table 1 200 and 300 mm tool-set comparison Process step
200 mm
300 mm
Comment
Oxidation and HT anneal Implantation Cleaning Bonding Polishing Thickness measurement Defectivity monitoring
Vertical furnace double boat Batch 17 wafers Cassette less cleaner Automatic bonder Multiple head/platens Full wafer reflectometer SP1-DLS
Vertical furnace double boat Batch 13 wafers Cassette less cleaner Automatic bonder Multiple head/platens Full wafer reflectometer SP1-DLS
Boat designs adapted to 300 mm Medium current Exact copy New machine generation Integrated cleaning for 300 mm >4000 pts per wafer in 300 mm Also used for mapping after HF revelation
For high temperature treatment, a 300 mm boat that minimizes wafer stress is used. Oxide uniformity is typically same as for 200 mm. For the implantation step, the same machine is used meaning that hydrogen beam 00 is unchanged. A wheel for 12 wafers is installed instead 00 of a 8 wheel and the handling system is also converted. From a throughput point of view, area to be scanned is 00 30% higher in the 12 configuration and the wheel holds 13 wafers resulting in a throughput ratio of 50%. New source and beam line configuration are now used, allowing to reach 75 mA current when implanting at 20 keV, a typical energy for the new products generation. Such conditions correspond to 17 300 mm wafers implanted per hour. Because of FOUP operation, dry-in dry-out polishing machine is used, with end point detection by in situ reflectivity monitoring, which lowers wafer to wafer mean thickness variations.
3. Ultrathin products 3.1. New Unibond process generations In fully depleted SOI devices, the threshold voltage (Vt ) is linked to silicon film thickness. In order to guarantee Vt uniformity over all produced devices, silicon film thickness has to be strictly controlled. Industry thickness requirements [1] for 45 nm node lead to 10 A accuracy on a 300 mm wafer. As a general trend, it
Fig. 3. Smart-Cut extendibility chart showing product status towards production, depending on silicon and buried oxide layers thickness combinations.
appears that such high uniformity needs to be guaranteed at all spatial wavelengths down to the Angstrom scale, which is currently the domain of roughness measurement. The ‘‘nano-uniformity’’ will certainly be the key challenge in metrology as discussed later. Fig. 3 shows how Smart-Cut technology can be extended to very thin films, both for silicon and oxide silicon films are already running in prolayers. 500 A SOI product is today in advanced duction while 200 A Unibond feasibility has been prototyping. 100/200 A recently demonstrated. The roadmap in Table 2 has been defined to address ultrathin SOI layers for 65 nm node and beyond. This
Table 2 Unibond ultrathin SOI roadmap Time line
2000
2001
2002
2003
2004
Process generation Silicon layer thickness (A) Si unif 6r (A)
PD 1000 150 ±7
FD 500–700 100 ±7
UT1 200–700 70 ±6
UT2 200–300 30 ±5
XUT 200 10 ±2.5
1A 1.5 A 1500–2000 ±4
1A 1.5 A 1000–1500 ±4
1.5 A 3A
2A 4A 800–1500 ±3
2A 5A 800–1500 ±3
Si unif 6r; all wrs all sites (%) Roughness AFM (RMS) 1 · 1 lm 10 · 10 lm Box layer thickness (A) Box layer TTV (%)
1000–1500 ±3
1058
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
roadmap is focusing on both 200 and 300 mm wafers for ultrathin products with a full commonality for process and toolset technology. 3.2. Ultrathin film processing in production with UT1 Present production is designed for ±50 A process generation. In this roadmap, uniformity is calculated at 6r (mean 3r), with each wafer measured using more than 1700 points in 200 mm and 4000 points in 300 mm. Then, plotting min–max values for each wafer (M 3r and M þ 3r), overall uniformity is obtained, all wafers, all sites (Fig. 4). Uniformity is then driven by two parameters, wafer to wafer mean thickness variation and on-wafer sigma. For this typical 200 mm example, mean thickness is controlled at ±15 A 1r. while typical on-wafer values are around 4.5 A, Uniformity cannot be disconnected from surface roughness. Unibond UT1 is offering the best combination regarding these two parameters. For both for 1 · 1 and 10 · 10 lm AFM scans, we can see in Fig. 5 that roughness is kept at very good levels. Interface roughness also exhibits low values, typically less than RMS. 2A The 300 mm UT1 process is in ramping-up phase and total uniformity, with 3 mm edge is capable of ±50 A exclusion. All characterization parameters including defect density, roughness, HF defect density, Secco defects, metallic contamination, and electrical properties are already exhibiting the same capability as for high volume 200 mm.
Fig. 5. AFM surface roughness for 1 · 1 and 10 · 10 lm scans RMS respectively. for UT1 products, 1.5 and 2.7 A
thinner and even more uniform films. In Unibond process, final uniformity is defined by oxidation, implantation and polishing steps. In new process generations, optimization of oxidation and implantation conditions led to very uniform as-split off structures, uniformity (1r) (Fig. 6). UT1, UT2 approaching 1 A
3.3. Towards UT2 and XUT generations When comparing UT1 performance and ITRS targets, improvements need to be achieved going towards
Fig. 6. 200 mm (as-split off) map for new UT generation pro uniformity (1r)––range is 7 A. cesses showing 1.3 A
600
target LL
Silicon thickness (Å)
UL
550
LEGEND Mean - 3S Mean Si
500
Mean + 3S
± 30 Å all wafers all sites 450 201 195
189 152 146
140 133 125
119 113 107
99 93 87
81 46
40 34 27
19 13
7 1
Wafer Number
product. For all sites on all wafers, thickness is within Fig. 4. 200 mm UT1 overall thickness uniformity chart for a 550/1450 A (including wafer-to-wafer and on-wafer 6r thickness variations). 550 ± 30 A
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
and XUT process are based on such highly uniform (7 A range) SOI structure. Differences in these generations appear in the steps involved to erase surface roughness and obtain final SOI structure. Regarding Si film thickness, there is no limitation in the Smart-Cut process for low energy implantation and films are 5–10 keV is a typical range. Then, 200–500 A obtained and a TEM cross-section (Fig. 7) allows to verify that crystalline quality and interface sharpness is not degraded for these ultrathin films. This TEM picture also proves that excellent nano-uniformity can be achieved. Measured at a wafer level, UT2 exhibit standard for a 3 mm edge exclusion on deviations lower than 5 A, control of mean a 300 mm wafer. Combined with a ±5 A thickness value, wafer to wafer, UT2 is compatible with overall uniformity, as shown in Fig. 8 for 200/ ±20 A product. 1500 A Further improvements have been made in splitting and finishing steps leading to surface roughness of 1 and RMS at 1 · 1 and 10 · 10 lm scans respectively 3.5 A (Fig. 8). Compared to UT1 process, better thickness control at a wafer level is balanced by degraded properties at a lm scale. Projections in terms of silicon layer uniformity re performance for 2005 time frame, verified at quire ±10 A all measurement scales up to the wafer level. Fig. 9 shows an image of what will become the XUT genera-
Fig. 7. A TEM cross-section image of the top silicon layer from 300 mm Unibond . The picture a UT2 generation 500/1500 A shows very good silicon uniformity and a sharp silicon/BOX interface.
1059
Fig. 9. 200 mm XUT product thickness map. 520/1450 A, and range is <10 A for 1765 3 mm edge exclusion. Sigma is 1 A points measured.
tion with first results obtained in 200 mm, demonstrat standard deviation is achievable. ing that less than 2 A A similar performance is achieved in 300 mm where overall on-wafer uniformity is compatible with ±10 A distribution, all wafer all sites (Fig. 10). This result is based on a strict control of the wafer-to-wafer mean thickness, and the metrology had to be optimized to get level. repeatability and accuracy at the A On the XUT product, surface roughness is reduced at all frequencies. With RMS roughnesses of 1.2, 2.2 and respectively for 1 · 1, 10 · 10 and 40 · 40 lm scans 4.2 A (Fig. 11), a low threshold defect measurement can be applied even on a low reflectivity wafer such as 500/ product shown in Fig. 10. Low defect density 1450 A is obtained (<50 defects/wafer), including surface and sub-surface defects. Threading defects discrimination is obtained by HF decoration of silicon voids in the buried oxide (so-called HF defects). Typical HF defect density is 0.05 defect/cm2 . When entering such low defect density, accurate detection techniques are required and inspected surface sampling is no more allowed. Exact defect count is achieved by scanning 100% of the revealed wafer using SP1, then reviewing any single defect under SEM imaging to separate killer (voids) from nonkiller (particles) defects.
product. Total thickness variation is ±20 A. Fig. 8. UT2 300 mm overall thickness performance preliminary results for 200/1500 A Unibond . R ¼ 3:5 A RMS. 10 · 10 lm AFM scan on UT2 300 mm 200/1500 A
1060
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
3 mm edge exclusion. Sigma is 2.1 A and range is 12 A for 7525 points Fig. 10. 300 mm XUT product thickness map. 500/1500 A, overall thickness control, all wafers, all sites, for the silicon layer. measured. Such properties enable ±10 A
RMS roughnesses. 0.19 lm threshold Fig. 11. 1 · 1, 10 · 10 and 40 · 40 lm AFM scans on XUT product showing 1.2, 2.2 and 4.2 A SP1 defect detection is then performed with less than 50 defects detected on this 300 mm wafer, with 3 mm EE.
4. Advanced Smart-Cut substrates for the future IC technology Strained silicon is one of the latest substrate developments as an answer to the requirement of very high performance devices. The production of these substrates necessitates several Si and SiGe epitaxial steps in order to obtain the strained silicon layer at the substrate surface (Fig. 12). The strained Si film is epitaxially grown on relaxed Si1 x Gex , and the degree of strain achieved is a function of the germanium percentage. It has been shown that as a function of the built-in strain in the Si lattice an enhancement of the electron and hole mobility of about 50% or more can be achieved, which translates into an improved MOSFET performance [20–24]. Substrates with x ¼ 20% are today commercially available with dislocation densities between 104 and 106 cm2 for strained Si films of about 20 nm thickness. There is a correlation between the Ge content and crystal quality of the epitaxial layers. As the Ge content increases above 20%, the thickness of the epitaxial Si that can be strained decreases. There is a critical thickness above which the strain in the Si film relaxes impairing the film quality. Strained silicon bulk wafers are still far from meeting the specifications of state-of-the-art Si and SOI wafers but development continues at a very high pace.
Fig. 12. The production of strained Si substrates requires several Si and SiGe epitaxial steps to obtain the thin layer of strained silicon layer at the wafer surface.
Smart Cut is the technology that enables the development of ultrathin strained Si on insulator, which will be needed for the fully depleted MOSFET architecture of the 65 nm IC technology node, while reducing the overall cost-of-ownership of such high end substrates [25]. By transferring a thin layer of the relaxed Si1 x Gex from the starting epitaxial substrate to an oxidized handle wafer, a SOI-like structure is obtained that combines the advantages of higher mobility with those typical of SOI (Fig. 13). The development of
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
ultrathin strained Si on insulator is underway in order to meet the future substrate needs of the IC industry towards better performing devices while keeping the power consumption at low levels. The strong synergy between Si thickness on oxide) and the ultrathin SOI (<500 A ultrathin strained Si is one of the factors that makes possible the fast development of this new generation of 300 mm wafers. The fabrication of strained Si on insulator (sSOI) consists in two main steps. The bilayer of strained Si and relaxed Si1 x Gex is transferred and then the Si1 x Gex is etched selectively to Si. In spite of the removal of the SiGe layer the strain of the Si film is preserved by the bonding step [26]. Fig. 14 shows strain monitoring through the whole Smart-Cut process. One can observe that sSi strain does not change before and after the transfer. The potential wafer solutions offered by the SmartCut technology are already much greater than just SOI and strained silicon on insulator. A current development is silicon on quartz (SOQ). It offers a single crystal silicon layer on a fused silica substrate, a development that will be extendable to silicon on glass. Silicon on quartz will enable the industry to couple for the first time the Si IC state-of-the-art integration know-how with transparent substrates. SOQ is specially challenging because
SiGeOI
s-Si grown after Smart-Cut r-Si1-xGex BOX Si base
s-SOI
s-Si BOX Si base
Fig. 13. SiGe on insulator can be obtained as a template for a subsequent strained Si epitaxy (SiGeOI) or the strained Si layer can be transferred directly to form sSOI.
1061
Fig. 14. Strain characterization by Raman Scattering. Strain does not change during Smart-Cut process.
the mismatch of the thermal coefficients of quartz and Si. Fig. 15 shows an example of a 200 nm SOQ with a typical Si layer uniformity of ±6 nm (min–max). The RMS. surface roughness for a 5 · 5 lm scan is 1.7 A Crystal quality of the transferred Si film is preserved. Germanium on insulator on a silicon substrate is another very promising development of heterosubstrates. Ge offers a higher mobility than Si. It is analogous to SOQ in the sense that the thermal coefficients of Ge and Si do not match. GeOI is well suited for the formation of high-k gate oxides, which are deposited in an oxygen rich atmosphere. Fig. 16 shows a TEM crosssection of GeOI. The know-how acquired through the SOI development has opened another door, engineering of the bonding energy to allow post-process debonding of the useful layer. The debonding technology of IC processed silicon layers makes it possible to obtain silicon films 100
Fig. 15. 200 mm SOQ wafer. Si thickness is 200 nm, standard variation is less than 2 nm.
1062
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
Fig. 16. TEM cross-section of germanium on insulator. Substrate is silicon. Ge heterosubstrates obtained with the SmartCut technology is also of interest for the manufacturing of solar cells if combined with a GaAs epitaxial step.
Fig. 18. Example of SiCOI (SiC 6H on axis/oxide/poly SiC).
5. Conclusion times thinner than those obtained by the state-of-the-art wafer thinning techniques. Fully processed IC wafers are commonly lapped down to a thickness of 100–150 lm. The smart-card industry requires wafer thinning down to 40–50 lm, the state-of-the-art today. With debondable Smart Cut wafers, wafer scale processed silicon films in the range of 0.2–1 lm thickness can be obtained. The availability of this wafer technology will empower the IC industry with a wide range of totally new solutions and applications, mainly in packaging, advanced very flexible smart cards, and 3D-SOC. Fig. 17 shows an example of a 0.5 lm single crystal Si film on a plastic substrate, unprocessed and processed. The Smart-Cut process enables transfer of highquality monocrystalline SiC thin films [27]. SiC engineered substrates are attractive for the development of high-temperature, high-power, and high-frequency electronic devices, and also GaN-based optoelectronic devices. The SiC on insulator (SiCOI) is compatible with high temperature SiC and GaN epitaxial processes (>1000 C). The transfer of SiC thin films onto low-cost substrates such as silicon or poly-crystalline SiC wafers is a further interesting characteristic of such composite 00 substrates. Fig. 18 shows an example of a 2 SiC on insulator.
In addition to conventional SOI, the flexibility of the Smart-Cut technology and the development of heterosubstrates permit many interesting applications beyond the silicon world, in photonics, opto-electronics, high frequency and high power devices. The benefits of Smart Cut are numerous, it is scalable to any wafer size, it allows multiple layer transfers from a donor substrate, it has the flexibility to combine single crystal thin films of a given material with another substrate material to engineer a wafer according to the targeted application. Smart Cut is a technology proven in high volume manufacturing capable of scaling the buried dielectric and the top silicon film over several orders of magnitude, from lm to nm. In ultrathin SOI films, uniformity control better than 1 nm has been established on 300 mm Unibond wafers. Now, in the early years of the 21st century we will see substrate manufacturers acquire more responsibility in the making of ICs through the development of more complex, partially processed substrates, tailored to specific applications. More visibility of the IC integration process will be needed to enable the wafer manufacturers to develop the suitable wafer solutions in a similar manner to the evolution seen among the equipment manufacturers in the 90s.
Fig. 17. Examples of silicon on plastic.
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
Acknowledgements Though most of the work described in this review is the result of R&D work of several teams, the authors would like to single out the support received by the R&D, engineering and Manufacturing divisions of Soitec, and the Laboratory for Film and Circuit Transfer of LETI-CEA in Grenoble. Special thanks in particular to F. Letertre, Ian Cayrefourcq A.J. Auberton Herve, E. Arene, George Celler, and B. Ghyselen of SOITEC, and B. Aspar of LETI-CEA. References [1] http://public.itrs.net. [2] Bruel M. Nucl Instrum Meth B 1996;108:313–9. [3] Cristoloveanu S, Li SS. Electrical characterization of silicon on insulator materials and devices. Boston: Kluwer Academic Publishers; 1995. [4] Colinge J-P. Silicon-on-insulator technology: materials to VLSI. 2nd ed. Boston: Kluwer; 1997. [5] Pelloie J-L, Auberton-Herve A. Solid State Technol 2001;44(Nov.):63. [6] Bruel M. US Patent 5,374,564 issued 12-20-1994 (US Patent filed 9-15-1992, preceded by a French filing on 9-181991). [7] Bruel M. Electron Lett 1995;31(14):1201. [8] Bruel M. Nucl Instrum Meth B 1996;108:313–9. [9] Auberton-Herve AJ, Maleville C. In: IEEE SOI Conference, 2002. p. 1. [10] Maleville C et al. In: IEEE SOI Conference, 2001. p. 155.
1063
[11] Auberton-Herve AJ, Ghyselen B, Letertre F, Maleville C, Barge T, Bruel M. Electrochem Soc Proc 1999;99-3:93. [12] Maleville C, Moulin C, Neyret E, Cauble C, Cheung L, Moirin R. In: IEEE SOI Conference, 2002. p. 194. [13] Tong QY, Gutjahr K, Hopfe S, G€ osele U, Lee T-H. Appl Phys Lett 1997;70(11):1390. [14] Tong QY, Chao YL, Huang LJ, G€ osele U. Electron Lett 1999;35(4):341. [15] G€ osele U, Bluhm Y, Kastner G, Kopperschmidt P, Krauter G, Scholz R, et al. J Vac Sci Technol A 1999;17(4). [16] Kub FJ, Hobart KD, Pond JM, Kirchoefer SW. Electron Lett 1999;35(6):477. [17] Agarwal A, Haynes TE, Venezia VC, Eaglesham DJ, Weldon MK, Chabal YJ, et al. In: IEEE SOI Conference, 1997. p. 44. [18] Tong Q-Y, Scholz R, G€ osele U, Lee TH, Huang L-J, Chao Y-L, et al. Appl Phys Lett 1998;72:49. [19] Current MI, Farrens SN, Fuerfanger M, Kang S, Kirk HR, Malik IJ, et al. In: Proc. IEEE SOI Conference, 2001. p. 11. [20] Rim et al. Symp. VLSI Technology, June 2001. p. 59. [21] Fischetti MV, Laux SE. J Appl Phys 1996;80:2234–52. [22] Cheng S et al. IEEE Electr Device Lett 2001;(July). [23] Welser J, Hoyt JL, Gibbons JF. IEEE Electr Dev Lett 1994;15:100. [24] Cheng Z, Currie MT, Leitz CW, Taraschi G, Lee ML, Pitera A, et al. In: Mat. Res. Soc. Symp. Proc. 686, 2002. A.1.5.1. [25] Maleville C. In: SOI Techno. and Devices XI, ECS conference, 2003. PV 2003-05, p. 33. [26] Ghyselen B et al. In: ICSI3: The SiGe Conference, 2003. [27] Di Cioccio L, Le Tiec Y, Jaussaud C, Hugonnard-Bruyere E, Bruel M. Mater Sci Forum 1998;264–268:765.
Smart-Cut technology: from 300 mm ultrathin SOI production to advanced engineered substrates Christophe Maleville *, Carlos Mazure SOITEC SA, Parc Technologique Des Fontaines, Crolles Cedex 38926, France
The review of this paper was arranged by Prof. S. Cristoloveanu
Abstract The Smart-Cut process, based on hydrogen implantation and wafer bonding, is a generic thin layer process transfer. Unibond SOI wafers are today in volume production, showing that splitting and bonding steps can be controlled, with high yields. Taking advantage of standard equipments flexibility, the process has been successfully scaled up to 300 mm. Most advanced 200 mm processes were successfully transferred to 300 mm, with wafers showing uniformity and defectivity results compatible with industry requirements for fully depleted device applications. The number of wafer solutions offered by the Smart-Cut technology is already much greater than just SOI. Strained silicon on insulator, silicon on quartz (SOQ), single crystal silicon layer on plastic supports, silicon carbide on insulator, germanium on insulator, multilayer SOI structures are just few examples of the potential of Smart Cut to engineer and design new substrates to answer the demands of the industry. A review of the progress achieved is given. 2004 Elsevier Ltd. All rights reserved.
1. Introduction During the last decade, the substrate industry has 00 brought the 8 substrate technology to maturity with the introduction of Cop (crystal-originated particles) free wafers, and two major innovations at the substrate level have occurred: the development of 300 mm silicon has been the response to the 0.18 lm IC technology node with a more aggressive introduction for technologies below 100 nm, and SOI, silicon on insulator, has been the response to the IC requirements [1] of improved performance while reducing the parasitic substrate capacitances and leakage currents. The SOI substrates constitute without doubt a paradigm shift of the silicon IC industry. The early SOI days in the 70s and 80s as a niche substrate technology for military or space applications are long over. SIMOX, wafer bonding and grind back (BESOI), the first SOI wafer manufacturing technologies, have also strongly * Corresponding author. Tel.: +33-476-92-7584; fax: +33476-92-7501. E-mail address: [email protected] (C. Maleville).
improved during the past 10 years but the SOI boom arrived with the breakthrough made by the Smart-Cut technology [2] in the late 90s. Since then, commercial applications of SOI have grown exponentially, and entered the mainstream of UltraLarge Scale Integration (ULSI) ICs. The SOI wafer is a composite substrate with an active top Si layer decoupled from the support wafer. It is the first example of an engineered substrate addressing main-stream MOSFET performance requirements. The impact of SOI on partially and fully depleted devices, performance enhancement, reduction of leakage currents and power consumption, suitability for low voltage device architecture and so forth, have been very extensively studied for the past two decades [3–5]. But as the IC industry moves towards the development of the future 65, 45, 32 and 22 nm technology nodes, more innovations will be required at the substrate level towards the end of this decade, which will be driven mainly by the MOSFET design. The coupling between device architecture and composite substrate engineering will be stronger. The IC industry is experiencing a similar shift to the one seen in the 90s with the development of IC process modules by the equipment manufacturers.
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2003.12.029
1056
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
with consistent quality. Bernin facility, opened in 1998, is now running at full capacity, with 900k wafers starts per year. 200 mm experience is demonstrating production stability and Unibond products in all diameters up 00 to 12 are today qualified in production by IC manufacturers for applications ranging from thin films to thick films (Fig. 2). 2.1. 300 mm SOI wafer manufacturing
Fig. 1. The UNIBOND process is based on hydrogen implantation and wafer bonding to a handle substrate B. Hydrogen implantation induces formation of an in-depth weakened layer located at the mean ion penetration depth which leads to cleavage of a thin film from a donor substrate A.
Substrate engineering will increasingly become a key consideration for the device architecture and CMOS processing. Smart Cut is a bonding and thin layer transfer technique from a donor wafer onto a handle substrate [6–8]. The transferred layer thickness is pre-determined by the cleavage zone created via ion implantation (hydrogen, helium, argon, etc.). After the layer transfer, the cleaved surface of the thin film is treated, polished and annealed to ensure a silicon film and surface quality comparable to silicon prime wafers. The schematic process flow of Smart Cut SOI (UNIBOND ) is shown in Fig. 1. Its technological strength is the manufacturability of the Smart-Cut technology, the wide flexibility in top silicon and buried oxide thicknesses, the scalability to any wafer diameter, and the utilization of standard IC manufacturing equipment [9,10]. The Smart-Cut process was originally developed to manufacture SOI and has achieved a high degree of maturity with UNIBOND mass production [9,11,12], but its potential goes beyond SOI, in contrast to SIMOX. Smart Cut is a generic layer transfer technology that fills the gap between heteroepitaxy and single crystal thin film transfer to any type of substrate. It strongly enlarges the field of engineered composite substrates combining different thin layer materials on a given substrate to address the requirements of the most diverse applications. Smart-Cut technology is today the object of many studies and developments worldwide [13–19].
2. High volume SOI manufacturing Smart-Cut process has been the enabling technology, allowing large volume production of SOI wafers
Several IC suppliers are today in qualification and ramp-up of 300 mm fab running SOI based advanced applications. As the Smart-Cut process is based on standard semiconductor equipments, the transition from 200 to 300 mm has been enabled by the availability of the 300 mm toolset. 300 mm Unibond feasibility was demonstrated in 1997, samples were built in 2000, and a 300 mm pilot line is operating since January 2002. Now in a ramp-up, this first 300 mm experience proved that there was no major limitation for 300 mm Unibond . As 300 mm silicon wafers incorporate today the most advanced silicon wafer engineering, the SOI quality and manufacturability has been even improved when going to this new diameter. Nanotopography improvements are particularly beneficial. Table 1 gives a comparison in terms of equipment type and configuration for 200 and 300 mm lines. From a manufacturing point of view, the 300 mm line has been set up using the 200 mm experience and is really close to 200 mm line. The major change is in the carrier type since 300 mm wafers are handled in FOUP cassettes for all tools and all processing steps from incoming material to shipment.
Fig. 2. The UNIBOND process technological strength is the compatibility with mass production, the wide flexibility in top Si and buried oxide thicknesses definition, the scalability to any wafer diameter, the utilization of standard IC manufacturing equipment. Wafer size requirements for ULSI partially or fully depleted device architecture is 200 and 300 mm, while for MEMS, MOEMS, and Smart Power it is typically between 100 and 150 mm.
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
1057
Table 1 200 and 300 mm tool-set comparison Process step
200 mm
300 mm
Comment
Oxidation and HT anneal Implantation Cleaning Bonding Polishing Thickness measurement Defectivity monitoring
Vertical furnace double boat Batch 17 wafers Cassette less cleaner Automatic bonder Multiple head/platens Full wafer reflectometer SP1-DLS
Vertical furnace double boat Batch 13 wafers Cassette less cleaner Automatic bonder Multiple head/platens Full wafer reflectometer SP1-DLS
Boat designs adapted to 300 mm Medium current Exact copy New machine generation Integrated cleaning for 300 mm >4000 pts per wafer in 300 mm Also used for mapping after HF revelation
For high temperature treatment, a 300 mm boat that minimizes wafer stress is used. Oxide uniformity is typically same as for 200 mm. For the implantation step, the same machine is used meaning that hydrogen beam 00 is unchanged. A wheel for 12 wafers is installed instead 00 of a 8 wheel and the handling system is also converted. From a throughput point of view, area to be scanned is 00 30% higher in the 12 configuration and the wheel holds 13 wafers resulting in a throughput ratio of 50%. New source and beam line configuration are now used, allowing to reach 75 mA current when implanting at 20 keV, a typical energy for the new products generation. Such conditions correspond to 17 300 mm wafers implanted per hour. Because of FOUP operation, dry-in dry-out polishing machine is used, with end point detection by in situ reflectivity monitoring, which lowers wafer to wafer mean thickness variations.
3. Ultrathin products 3.1. New Unibond process generations In fully depleted SOI devices, the threshold voltage (Vt ) is linked to silicon film thickness. In order to guarantee Vt uniformity over all produced devices, silicon film thickness has to be strictly controlled. Industry thickness requirements [1] for 45 nm node lead to 10 A accuracy on a 300 mm wafer. As a general trend, it
Fig. 3. Smart-Cut extendibility chart showing product status towards production, depending on silicon and buried oxide layers thickness combinations.
appears that such high uniformity needs to be guaranteed at all spatial wavelengths down to the Angstrom scale, which is currently the domain of roughness measurement. The ‘‘nano-uniformity’’ will certainly be the key challenge in metrology as discussed later. Fig. 3 shows how Smart-Cut technology can be extended to very thin films, both for silicon and oxide silicon films are already running in prolayers. 500 A SOI product is today in advanced duction while 200 A Unibond feasibility has been prototyping. 100/200 A recently demonstrated. The roadmap in Table 2 has been defined to address ultrathin SOI layers for 65 nm node and beyond. This
Table 2 Unibond ultrathin SOI roadmap Time line
2000
2001
2002
2003
2004
Process generation Silicon layer thickness (A) Si unif 6r (A)
PD 1000 150 ±7
FD 500–700 100 ±7
UT1 200–700 70 ±6
UT2 200–300 30 ±5
XUT 200 10 ±2.5
1A 1.5 A 1500–2000 ±4
1A 1.5 A 1000–1500 ±4
1.5 A 3A
2A 4A 800–1500 ±3
2A 5A 800–1500 ±3
Si unif 6r; all wrs all sites (%) Roughness AFM (RMS) 1 · 1 lm 10 · 10 lm Box layer thickness (A) Box layer TTV (%)
1000–1500 ±3
1058
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
roadmap is focusing on both 200 and 300 mm wafers for ultrathin products with a full commonality for process and toolset technology. 3.2. Ultrathin film processing in production with UT1 Present production is designed for ±50 A process generation. In this roadmap, uniformity is calculated at 6r (mean 3r), with each wafer measured using more than 1700 points in 200 mm and 4000 points in 300 mm. Then, plotting min–max values for each wafer (M 3r and M þ 3r), overall uniformity is obtained, all wafers, all sites (Fig. 4). Uniformity is then driven by two parameters, wafer to wafer mean thickness variation and on-wafer sigma. For this typical 200 mm example, mean thickness is controlled at ±15 A 1r. while typical on-wafer values are around 4.5 A, Uniformity cannot be disconnected from surface roughness. Unibond UT1 is offering the best combination regarding these two parameters. For both for 1 · 1 and 10 · 10 lm AFM scans, we can see in Fig. 5 that roughness is kept at very good levels. Interface roughness also exhibits low values, typically less than RMS. 2A The 300 mm UT1 process is in ramping-up phase and total uniformity, with 3 mm edge is capable of ±50 A exclusion. All characterization parameters including defect density, roughness, HF defect density, Secco defects, metallic contamination, and electrical properties are already exhibiting the same capability as for high volume 200 mm.
Fig. 5. AFM surface roughness for 1 · 1 and 10 · 10 lm scans RMS respectively. for UT1 products, 1.5 and 2.7 A
thinner and even more uniform films. In Unibond process, final uniformity is defined by oxidation, implantation and polishing steps. In new process generations, optimization of oxidation and implantation conditions led to very uniform as-split off structures, uniformity (1r) (Fig. 6). UT1, UT2 approaching 1 A
3.3. Towards UT2 and XUT generations When comparing UT1 performance and ITRS targets, improvements need to be achieved going towards
Fig. 6. 200 mm (as-split off) map for new UT generation pro uniformity (1r)––range is 7 A. cesses showing 1.3 A
600
target LL
Silicon thickness (Å)
UL
550
LEGEND Mean - 3S Mean Si
500
Mean + 3S
± 30 Å all wafers all sites 450 201 195
189 152 146
140 133 125
119 113 107
99 93 87
81 46
40 34 27
19 13
7 1
Wafer Number
product. For all sites on all wafers, thickness is within Fig. 4. 200 mm UT1 overall thickness uniformity chart for a 550/1450 A (including wafer-to-wafer and on-wafer 6r thickness variations). 550 ± 30 A
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
and XUT process are based on such highly uniform (7 A range) SOI structure. Differences in these generations appear in the steps involved to erase surface roughness and obtain final SOI structure. Regarding Si film thickness, there is no limitation in the Smart-Cut process for low energy implantation and films are 5–10 keV is a typical range. Then, 200–500 A obtained and a TEM cross-section (Fig. 7) allows to verify that crystalline quality and interface sharpness is not degraded for these ultrathin films. This TEM picture also proves that excellent nano-uniformity can be achieved. Measured at a wafer level, UT2 exhibit standard for a 3 mm edge exclusion on deviations lower than 5 A, control of mean a 300 mm wafer. Combined with a ±5 A thickness value, wafer to wafer, UT2 is compatible with overall uniformity, as shown in Fig. 8 for 200/ ±20 A product. 1500 A Further improvements have been made in splitting and finishing steps leading to surface roughness of 1 and RMS at 1 · 1 and 10 · 10 lm scans respectively 3.5 A (Fig. 8). Compared to UT1 process, better thickness control at a wafer level is balanced by degraded properties at a lm scale. Projections in terms of silicon layer uniformity re performance for 2005 time frame, verified at quire ±10 A all measurement scales up to the wafer level. Fig. 9 shows an image of what will become the XUT genera-
Fig. 7. A TEM cross-section image of the top silicon layer from 300 mm Unibond . The picture a UT2 generation 500/1500 A shows very good silicon uniformity and a sharp silicon/BOX interface.
1059
Fig. 9. 200 mm XUT product thickness map. 520/1450 A, and range is <10 A for 1765 3 mm edge exclusion. Sigma is 1 A points measured.
tion with first results obtained in 200 mm, demonstrat standard deviation is achievable. ing that less than 2 A A similar performance is achieved in 300 mm where overall on-wafer uniformity is compatible with ±10 A distribution, all wafer all sites (Fig. 10). This result is based on a strict control of the wafer-to-wafer mean thickness, and the metrology had to be optimized to get level. repeatability and accuracy at the A On the XUT product, surface roughness is reduced at all frequencies. With RMS roughnesses of 1.2, 2.2 and respectively for 1 · 1, 10 · 10 and 40 · 40 lm scans 4.2 A (Fig. 11), a low threshold defect measurement can be applied even on a low reflectivity wafer such as 500/ product shown in Fig. 10. Low defect density 1450 A is obtained (<50 defects/wafer), including surface and sub-surface defects. Threading defects discrimination is obtained by HF decoration of silicon voids in the buried oxide (so-called HF defects). Typical HF defect density is 0.05 defect/cm2 . When entering such low defect density, accurate detection techniques are required and inspected surface sampling is no more allowed. Exact defect count is achieved by scanning 100% of the revealed wafer using SP1, then reviewing any single defect under SEM imaging to separate killer (voids) from nonkiller (particles) defects.
product. Total thickness variation is ±20 A. Fig. 8. UT2 300 mm overall thickness performance preliminary results for 200/1500 A Unibond . R ¼ 3:5 A RMS. 10 · 10 lm AFM scan on UT2 300 mm 200/1500 A
1060
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
3 mm edge exclusion. Sigma is 2.1 A and range is 12 A for 7525 points Fig. 10. 300 mm XUT product thickness map. 500/1500 A, overall thickness control, all wafers, all sites, for the silicon layer. measured. Such properties enable ±10 A
RMS roughnesses. 0.19 lm threshold Fig. 11. 1 · 1, 10 · 10 and 40 · 40 lm AFM scans on XUT product showing 1.2, 2.2 and 4.2 A SP1 defect detection is then performed with less than 50 defects detected on this 300 mm wafer, with 3 mm EE.
4. Advanced Smart-Cut substrates for the future IC technology Strained silicon is one of the latest substrate developments as an answer to the requirement of very high performance devices. The production of these substrates necessitates several Si and SiGe epitaxial steps in order to obtain the strained silicon layer at the substrate surface (Fig. 12). The strained Si film is epitaxially grown on relaxed Si1 x Gex , and the degree of strain achieved is a function of the germanium percentage. It has been shown that as a function of the built-in strain in the Si lattice an enhancement of the electron and hole mobility of about 50% or more can be achieved, which translates into an improved MOSFET performance [20–24]. Substrates with x ¼ 20% are today commercially available with dislocation densities between 104 and 106 cm2 for strained Si films of about 20 nm thickness. There is a correlation between the Ge content and crystal quality of the epitaxial layers. As the Ge content increases above 20%, the thickness of the epitaxial Si that can be strained decreases. There is a critical thickness above which the strain in the Si film relaxes impairing the film quality. Strained silicon bulk wafers are still far from meeting the specifications of state-of-the-art Si and SOI wafers but development continues at a very high pace.
Fig. 12. The production of strained Si substrates requires several Si and SiGe epitaxial steps to obtain the thin layer of strained silicon layer at the wafer surface.
Smart Cut is the technology that enables the development of ultrathin strained Si on insulator, which will be needed for the fully depleted MOSFET architecture of the 65 nm IC technology node, while reducing the overall cost-of-ownership of such high end substrates [25]. By transferring a thin layer of the relaxed Si1 x Gex from the starting epitaxial substrate to an oxidized handle wafer, a SOI-like structure is obtained that combines the advantages of higher mobility with those typical of SOI (Fig. 13). The development of
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
ultrathin strained Si on insulator is underway in order to meet the future substrate needs of the IC industry towards better performing devices while keeping the power consumption at low levels. The strong synergy between Si thickness on oxide) and the ultrathin SOI (<500 A ultrathin strained Si is one of the factors that makes possible the fast development of this new generation of 300 mm wafers. The fabrication of strained Si on insulator (sSOI) consists in two main steps. The bilayer of strained Si and relaxed Si1 x Gex is transferred and then the Si1 x Gex is etched selectively to Si. In spite of the removal of the SiGe layer the strain of the Si film is preserved by the bonding step [26]. Fig. 14 shows strain monitoring through the whole Smart-Cut process. One can observe that sSi strain does not change before and after the transfer. The potential wafer solutions offered by the SmartCut technology are already much greater than just SOI and strained silicon on insulator. A current development is silicon on quartz (SOQ). It offers a single crystal silicon layer on a fused silica substrate, a development that will be extendable to silicon on glass. Silicon on quartz will enable the industry to couple for the first time the Si IC state-of-the-art integration know-how with transparent substrates. SOQ is specially challenging because
SiGeOI
s-Si grown after Smart-Cut r-Si1-xGex BOX Si base
s-SOI
s-Si BOX Si base
Fig. 13. SiGe on insulator can be obtained as a template for a subsequent strained Si epitaxy (SiGeOI) or the strained Si layer can be transferred directly to form sSOI.
1061
Fig. 14. Strain characterization by Raman Scattering. Strain does not change during Smart-Cut process.
the mismatch of the thermal coefficients of quartz and Si. Fig. 15 shows an example of a 200 nm SOQ with a typical Si layer uniformity of ±6 nm (min–max). The RMS. surface roughness for a 5 · 5 lm scan is 1.7 A Crystal quality of the transferred Si film is preserved. Germanium on insulator on a silicon substrate is another very promising development of heterosubstrates. Ge offers a higher mobility than Si. It is analogous to SOQ in the sense that the thermal coefficients of Ge and Si do not match. GeOI is well suited for the formation of high-k gate oxides, which are deposited in an oxygen rich atmosphere. Fig. 16 shows a TEM crosssection of GeOI. The know-how acquired through the SOI development has opened another door, engineering of the bonding energy to allow post-process debonding of the useful layer. The debonding technology of IC processed silicon layers makes it possible to obtain silicon films 100
Fig. 15. 200 mm SOQ wafer. Si thickness is 200 nm, standard variation is less than 2 nm.
1062
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
Fig. 16. TEM cross-section of germanium on insulator. Substrate is silicon. Ge heterosubstrates obtained with the SmartCut technology is also of interest for the manufacturing of solar cells if combined with a GaAs epitaxial step.
Fig. 18. Example of SiCOI (SiC 6H on axis/oxide/poly SiC).
5. Conclusion times thinner than those obtained by the state-of-the-art wafer thinning techniques. Fully processed IC wafers are commonly lapped down to a thickness of 100–150 lm. The smart-card industry requires wafer thinning down to 40–50 lm, the state-of-the-art today. With debondable Smart Cut wafers, wafer scale processed silicon films in the range of 0.2–1 lm thickness can be obtained. The availability of this wafer technology will empower the IC industry with a wide range of totally new solutions and applications, mainly in packaging, advanced very flexible smart cards, and 3D-SOC. Fig. 17 shows an example of a 0.5 lm single crystal Si film on a plastic substrate, unprocessed and processed. The Smart-Cut process enables transfer of highquality monocrystalline SiC thin films [27]. SiC engineered substrates are attractive for the development of high-temperature, high-power, and high-frequency electronic devices, and also GaN-based optoelectronic devices. The SiC on insulator (SiCOI) is compatible with high temperature SiC and GaN epitaxial processes (>1000 C). The transfer of SiC thin films onto low-cost substrates such as silicon or poly-crystalline SiC wafers is a further interesting characteristic of such composite 00 substrates. Fig. 18 shows an example of a 2 SiC on insulator.
In addition to conventional SOI, the flexibility of the Smart-Cut technology and the development of heterosubstrates permit many interesting applications beyond the silicon world, in photonics, opto-electronics, high frequency and high power devices. The benefits of Smart Cut are numerous, it is scalable to any wafer size, it allows multiple layer transfers from a donor substrate, it has the flexibility to combine single crystal thin films of a given material with another substrate material to engineer a wafer according to the targeted application. Smart Cut is a technology proven in high volume manufacturing capable of scaling the buried dielectric and the top silicon film over several orders of magnitude, from lm to nm. In ultrathin SOI films, uniformity control better than 1 nm has been established on 300 mm Unibond wafers. Now, in the early years of the 21st century we will see substrate manufacturers acquire more responsibility in the making of ICs through the development of more complex, partially processed substrates, tailored to specific applications. More visibility of the IC integration process will be needed to enable the wafer manufacturers to develop the suitable wafer solutions in a similar manner to the evolution seen among the equipment manufacturers in the 90s.
Fig. 17. Examples of silicon on plastic.
C. Maleville, C. Mazure / Solid-State Electronics 48 (2004) 1055–1063
Acknowledgements Though most of the work described in this review is the result of R&D work of several teams, the authors would like to single out the support received by the R&D, engineering and Manufacturing divisions of Soitec, and the Laboratory for Film and Circuit Transfer of LETI-CEA in Grenoble. Special thanks in particular to F. Letertre, Ian Cayrefourcq A.J. Auberton Herve, E. Arene, George Celler, and B. Ghyselen of SOITEC, and B. Aspar of LETI-CEA. References [1] http://public.itrs.net. [2] Bruel M. Nucl Instrum Meth B 1996;108:313–9. [3] Cristoloveanu S, Li SS. Electrical characterization of silicon on insulator materials and devices. Boston: Kluwer Academic Publishers; 1995. [4] Colinge J-P. Silicon-on-insulator technology: materials to VLSI. 2nd ed. Boston: Kluwer; 1997. [5] Pelloie J-L, Auberton-Herve A. Solid State Technol 2001;44(Nov.):63. [6] Bruel M. US Patent 5,374,564 issued 12-20-1994 (US Patent filed 9-15-1992, preceded by a French filing on 9-181991). [7] Bruel M. Electron Lett 1995;31(14):1201. [8] Bruel M. Nucl Instrum Meth B 1996;108:313–9. [9] Auberton-Herve AJ, Maleville C. In: IEEE SOI Conference, 2002. p. 1. [10] Maleville C et al. In: IEEE SOI Conference, 2001. p. 155.
1063
[11] Auberton-Herve AJ, Ghyselen B, Letertre F, Maleville C, Barge T, Bruel M. Electrochem Soc Proc 1999;99-3:93. [12] Maleville C, Moulin C, Neyret E, Cauble C, Cheung L, Moirin R. In: IEEE SOI Conference, 2002. p. 194. [13] Tong QY, Gutjahr K, Hopfe S, G€ osele U, Lee T-H. Appl Phys Lett 1997;70(11):1390. [14] Tong QY, Chao YL, Huang LJ, G€ osele U. Electron Lett 1999;35(4):341. [15] G€ osele U, Bluhm Y, Kastner G, Kopperschmidt P, Krauter G, Scholz R, et al. J Vac Sci Technol A 1999;17(4). [16] Kub FJ, Hobart KD, Pond JM, Kirchoefer SW. Electron Lett 1999;35(6):477. [17] Agarwal A, Haynes TE, Venezia VC, Eaglesham DJ, Weldon MK, Chabal YJ, et al. In: IEEE SOI Conference, 1997. p. 44. [18] Tong Q-Y, Scholz R, G€ osele U, Lee TH, Huang L-J, Chao Y-L, et al. Appl Phys Lett 1998;72:49. [19] Current MI, Farrens SN, Fuerfanger M, Kang S, Kirk HR, Malik IJ, et al. In: Proc. IEEE SOI Conference, 2001. p. 11. [20] Rim et al. Symp. VLSI Technology, June 2001. p. 59. [21] Fischetti MV, Laux SE. J Appl Phys 1996;80:2234–52. [22] Cheng S et al. IEEE Electr Device Lett 2001;(July). [23] Welser J, Hoyt JL, Gibbons JF. IEEE Electr Dev Lett 1994;15:100. [24] Cheng Z, Currie MT, Leitz CW, Taraschi G, Lee ML, Pitera A, et al. In: Mat. Res. Soc. Symp. Proc. 686, 2002. A.1.5.1. [25] Maleville C. In: SOI Techno. and Devices XI, ECS conference, 2003. PV 2003-05, p. 33. [26] Ghyselen B et al. In: ICSI3: The SiGe Conference, 2003. [27] Di Cioccio L, Le Tiec Y, Jaussaud C, Hugonnard-Bruyere E, Bruel M. Mater Sci Forum 1998;264–268:765.