Statistical control of VLSI fabrication processes

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World Abstracts on Mlcroelectronics and Rehabllity

Statistical conttul of VLSI fabrication processes. PURNENDU K MOZUMBER and ANDRZFJ J STROJWAS IEEE Trans Compon, Hybrids mfg Technol 14(3), 467 (September 1991) In this paper we propose a profit-based framework for an integrated CAD-CAM system for present and future VLSI design and manufacturing The ineflictencies of present day CAM systems are due to the lack of appropriate methodologies for process momtonng and statistical techmques to analyze the in-process and end-of-process data Methodologles for momtorlng lots in fabncatlon lines using in Sltu measurements and controlhng lots using the multivariate distribution of observable m-process parameters are developed at Carnegie Mellon University The software system which implements the new algorithms have shown encouraging results when applied to industrial fabrication lines Evaluation of modelling refinements on work sampling statistics. ELINORS PAPE and CHIA-Tzu HUANG Comput lnd. Engng 21(1-4), 179 (1991) A spreadsheet program is presented as a design tool for work sampling studies The program incorporates the alternatmg Po~sson process (APP) model for process fluctuation and allows for evaluation of process parameters with, or without, a finite sample size correction Prodnction scheduling algorithms for a semicoodnctor test facifity. REHAUZSOY, LouIs A MARTIN-VEGA,CHUNG-YEE LEE and PAUL A LEONARD. IEEE Trans Semlcond. Mfg 4(4), 270 (November 1991) The objective of this study is to develop production scheduling algorithms for semiconductor test operations The operations in the facility under study are charactenzed by a broad product mix, variable lot sizes and yields, long and variable setup times, and limited test equipment capacity The approach presented in this paper starts by dividing the facility or job shop into a number of workcenters The method then proceeds to sequence one workcenter at a time_ A disjunctive graph representation of the entire faohty is used to capture interactions between workcenters The introduction of different management objecUves leads to different workcenter problems and different production scheduling algorithms This paper presents algorithms for two different workcenter problems. Directions for future research are also discussed

Using distributed topology update and preplanned configurations to achieve trunk network survivability. BRIANA COAN et al 1EEE Trans. Rehab. 40(4), 404 (October 1991) The extenswe deployment of high-bandwidth fiber-optic transmission facilities in the telephone trunk network has increased the amount of damage that can be caused by a smgle physical failure The increased vulnerability of the trunk network has respired a wide range of recent work on survivability, which is the problem of improving the ability of the trunk network to provide service after a physical failure We propose a new modular approach to survivablhty. It is intended for a trunk network consisting of high-bandwidth fiber-optic links connected through reconfigurable digital cross-connect nodes It works for both node and link failures Our approach comprises a distributed protocol with two parts First, cause the surviving digital cross-connect nodes to converge to an agreement on the topology (t.e, what is up and what is down) Second, based on the agreed topology and on a precomputed plan for that topology, reconfigure the digRal cross-connect nodes to restore as much call-carrying capacity as possible The modularity of our approach comes from separating the problem of devising a distnbuted fault-tolerant protocol to determine what the failure ts from the problem of designing a network reconfiguration for that failure. An expert system framework for machine fault diagnosis. MURALIKRISHNAMURTHIand DON T PHILLIPS Comput, lnd

Engng 22(I), 67 (1992) This research focuses on two major issues related to the design, development, and implementaUon of machine fault dtagnosss expert systems (1) investlgat,on of the actual cognitive process of human diagnostic experts, and (2) analysts of the current practices in the development of machine fault diagnosis expert systems The investigation of the human diagnostic reasoning process has resulted m the abstraction and capturing of the human ablhty to learn, understand, and diagnose different machinery belonging to a particular class The captured abstractions of human diagnostic expert)se have been integrated with the expert system development expertise of knowledge engineers to provide a customized expert system shell for developing machine fault diagnosis expert systems The designed machine fault diagnosis shell reduces the development time, effort and skdl making use of generalized modules for knowledge acquisition, knowledge verification, application system generation, learning, explanation, and eliminates the burden of designing and developing each application diagnosis expert system separately The developed shell has been validated by generating a prototype fault diagnosis expert system for a Cincinnati Mllacron 786 robot

Analyzing quality for better testing. KEMONTASCHIOGLOU Test Measurement Wld, 62 (November 1991) Quality impact analysts develops an algebra of quality that makes it possible to quantify and manipulate quahty Short and long loop manufacturing feedback using a multisensor assembly test chip. JAMESN SWEET,et al IEEE Trans Compon Hybrids mfg Technol 14(3), 529 (September 1991) A family of silicon test chips has been developed for use in making diagnostic measurements dunng electronics assembly These assembly test chips (ATCs) contain sensors that measure a number of variables associated with assembled IC degradation; including, the degree of integrated circuit (IC) corrosion, handling damage, ESD threat, ppmv moisture or humidity, mechanical stress, mobile ion density, bond pad cratermg, and high-speed logm degradation The chips in the ATC family are intended to give manufactunng feedback in four ways direct feedback m evaluation of an assembly manufactunng hne in an objective, nonmtruslve way, before and after comparisons on an assembly production line when an individual process, material, or piece of equipment has been changed, resident lifetime monitor for system package aging and ongoing rehablhty projection, and thermal, mechanical, d c. electrical, and high frequency mock-up evaluation of packaging (including multichip) schemes

Two approaches to array fault tolerance in the IBM enterprise system/9000H type 9121 processor. P R TURGEON, A R STEEL and M R, CHARLEBOIS IBM J, Res Dev 35(3), 382 (May 1991) The system design of the IBM Enterprise System/9000 (rM) Type 9121 processor was Intended to provide high performance and dense packaging within an air-cooled system Packaging and technology factors had a major influence on the fault-tolerance strategies chosen This paper describes the effect that this design point had on the fault-tolerant capabdiues of two critical 9121 array applicauons Although the design challenges faced by these array applications initially appeared to be very similar, the resulting solutions represent very different designs with dlffenng fault-tolerance capabilities The rationale for these approaches is given, and the error-correction algorithms are described Computerized tolerance techniques. MOHAMMADELHAMUL HUQ and Horcc,-Cm~oZI~ANG. Comput. md Engng 21(1-4), 165 (1991) The intense global competition to produce quality products at low cost has led many industrial nations to consider mechanical tolerances as a key factor to bring about cost savings as well as be competitive In the last two