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constant voltage stress on mos gate oxides
Microelectron. Reliab., Vol. 37, No. 7, pp. 1045-1051, 1997 © 1997 Elsevier Science Ltd All rights reserved. Printed in Great Britain
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STUDY OF UNIPOLAR PULSED RAMP AND COMBINED RAMPED/CONSTANT VOLTAGE STRESS ON MOS GATE OXIDES A. M A R T I N , P. O ' S U L L I V A N and A. M A T H E W S O N National Microelectronics Research Centre (NMRC), University College Cork, Lee Maltings, Prospect Row, Cork, Ireland (Received 31 January 1996; in revised form 20 June 1996)
Al~tract--MOS gate oxide capacitors over a wide range of oxide thicknesses (10.9-28 nm) were stressed using a unipolar pulsed voltage ramp and combined ramped/constant voltage stress measurements. The reliability measurements were performed with several different bias conditions in order to assess the effects of the measurement conditions on times to breakdown and breakdown fields. In the first part it was verified that the unipolar pulsed ramp yields breakdown distributions which are identical to those of a widely used staircase ramp. In the second part the unipolar pulsed ramp was used for pre-stress prior to a constant stress and measurement results were compared to those of a ramped/constant stress with a staircase ramp. In several cases a ramp prior to a constant stress increases time to breakdown. The observations made in this study imply that the time to breakdown of a constant stress in the Fowler-Nordheim tunneling regime is strongly dependent on charge trapping and, therefore, on the stressing history of the oxide. Finally, it is shown that the combined ramped/constant voltage stress is a valuable tool for monitoring extrinsic and intrinsic breakdown properties when applying stress parameters in the correct way. © 1997 Elsevier Science Ltd.
INTRODUCTION The ramped voltage stress (RVS) and constant voltage stress (CVS) are widely used in industry for the characterization of breakdown properties of MOS gate oxides. RVS records, in a short time, defect related and intrinsic breakdowns of an oxide. However, CVS measurements monitor the time to breakdown (t~) of the oxide. Because the lifetime at operating voltage is important for long term reliability, the t~ of the CVS is used nearly exclusively for the prediction of lifetimes [1, 2]. The t~ of a CVS is traded as a standard for the characterization of oxide quality. But the CVS has the disadvantage of monitoring the defect related breakdowns with poor resolution unless the stress bias is set to very low fields which would result in measurement times in the order of hours, days or weeks. Such long measurements are not suitable for short wafer level reliability measurements. When the advantages of CVS and RVS are combined the stress sequence of Fig. 1 can be used for reliability measurements. The aim of this study is the assessment of the time efficient combined reliability stress for monitoring extrinsic oxide breakdowns and intrinsic t~ which can be subsequently used for lifetime predictions. The significance of the work must be seen in the following aspects. Similar combined stresses (Fig. 1) are performed in industry for long term oxide monitoring [3, 4] but the effect of the pre-stress is neglected. The extrinsic breakdowns of an oxide reliability measurement are the
most important since they cause early field failures. Therefore, it is necessary to monitor them with a high resolution which can be achieved with a combined ramped/constant stress without introducing long measurement times. A pre-stressing voltage ramp is applied prior to the CVS. This type of measurement is often used but the form of the pre-stress varies for different semiconductor manufacturers [3, 5, 6]. The pre-set can consist of a staircase ramp [3, 7], a unipolar pulsed ramp (UPR) [8, 9] or several steps with irregular step widths (tstep) and step heights (Es,ep) [4-6, 10, 11]. In this study a U P R is applied as the pre-stress. For the combined stress of Fig. 1, the t~ is only recorded for the CVS. The time of the pre-stressing ramp is not included in the t~. However, breakdowns which occurred during the ramp were included in the analysis and in the tbd distributions of Weibull plots a s tbd = 0 S.
In earlier work on thermally grown oxides on polycrystalline silicon [12, 13] it was observed that when a CVS measurement is preceded by a ramp, a longer t~ and higher charge to breakdown (Q~) can be monitored than with a CVS alone. This important aspect is investigated in this study for MOS gate oxides because long term oxide reliability can be overestimated when t~ and Q~ are enhanced due to the combined stress of Fig. 1. In the first part of this work breakdown fields of a U P R (Fig. 2) were compared to those of a staircase ramp for a wide range of stress parameters to
1045
1046
A. Martin et al. Fmkl[MVlcml RVS
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Table 1. Stress conditions for the comparison between a staircase ramp and a unipolar pulsed ramp
cvs
Ramp type
CV
memmed Esiep
curn~!
R = ~,~v/t~,o r [MV/cm/s]
N .... [MV/cm]
t,o~ [s]
No~ [MV/cm]
Staircase
0.1/I.0
l.l
--
--
UPR
0.1/1.0 0.1/1.0 0.1/1.0 0.1/1.0
1.1 1.1 1.1 1.1
0.15 1.0 2.5 5.0
1.0 1.0 1.0 1.0
imelpity dzeck
E $1& Ek~ ImI
1
I
t step
I low
;
'.qc--~,'
l
0
2
3
4
Fig. 1. Schematic bias conditions of the combined ramped/constant voltage stress performed with a unipolar pulsed ramp.
validate the U P R for the c o m b i n e d r a m p e d / c o n s t a n t stress. In the second part the c o m b i n e d stress is performed with various stress conditions for the assessment o f the tbd increase. In order to gain insight into the t~ e n h a n c e m e n t with a pre-stress c u r r e n t time ( l - t ) characteristics were investigated. Finally, it is s h o w n that a U P R / C V S stress is a useful tool for m o n i t o r i n g oxide reliability without overestimating oxide lifetimes when the stress parameters are carefully chosen. EXPERIMENTS AND SAMPLES All m e a s u r e m e n t s were performed on the wafer level with a HP4062 Parametric Test System at room t e m p e r a t u r e a n d biases in the F o w l e r - N o r d h e i m ( F - N ) tunneling regime. M O S gate oxides were stressed in a thickness range o f 10.9-28 nm. F o r the small area capacitors, 10 duplicates per site and 40 sites per wafer allowed m a n y measurements to be carried out on the same statistical population. All
measurements were performed with the silicon substrate in accumulation. The oxides were thermally grown o n an n- a n d p-type silicon substrate. Test capacitors had degenerately doped n+-polysilicon gates. A U P R (Fig. 2) was applied for RVS measurements in this work. The r a m p was first described in the work of Hallberg [9]. Later, its advantages were discussed in the work o f H e i m a n n [14] a n d the use o f the U P R instead o f a staircase r a m p was suggested. In a recent publication of Neely [15] this r a m p was proposed to be necessary for thin oxide testing. It has the a d v a n t a g e of detecting oxide b r e a k d o w n at low bias levels, E~ow,without placing an upper limit on the tunnel currents at the stress level with a pre-defined b r e a k d o w n current. The U P R was extensively used in earlier characterization work for thermally grown oxides on polycrystalline silicon [16, 17]. In a set o f experiments the staircase r a m p was c o m p a r e d to a U P R with various parameters for tjo~, E~ow a n d Est.... M e a s u r e m e n t s were performed on a 20 n m M O S gate oxide. The r a m p rate was defined as R = E~,op/t,,ep for all applied ramps. In the first experiment RVS was performed with a staircase r a m p and a UPR. The u n i p o l a r r a m p times at ELowranged from 0.15 s to 5 s. The stress conditions are listed in detail in Table 1. Figure 3 presents the m e a s u r e m e n t results which show no deviations between the intrinsic parts of the
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Fig. 2. Schematic bias conditions of the unipolar pulsed ramp (UPR).
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1047
Voltage stress on MOS gate oxides 1 0 . S ] ~ ~ = ~ = = = = ~
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Table 3. Stress conditions for a unipolar pulsed ramp with various E ~ and E~owvalues
/
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5
6
7
8
9
10
Field [MVIcrai
Fig. 4. ~ V characteristics of a staircase ramp and a UPR with &w = 2.5 s and a ramp rate of (0.1 MV/cm)/1 s of data of Fig. 3.
breakdown distributions. This is an important result because the staircase ramp and the U P R exhibit identical breakdown fields. The current-voltage (l-V) characteristics were recorded during the RVS measurements of the first experiment. In Fig. 4 the I - V characteristics of the staircase ramp are compared to those of a U P R with t~ow= 2.5 s. The l - V c u r v e s were chosen from samples which broke down at fields equal to Ebds0 of the Weibull plot in Fig. 3. It can be observed that the I - V characteristics are identical for a staircase ramp and a UPR. Only very small statistical site to site variations can be seen from the inset of Fig. 4. This gives further evidence that a U P R and a staircase ramp result in identical breakdown distributions. In terms of Q~, a U P R and a staircase ramp inject the same quantity of charge during the measurement independently of the low voltage step of the UPR, since I - V curves are identical (Qb~ = EL x /step). In the second experiment the starting field of the U P R was varied: 1.1 MV/cm < E+t,F,< 8.1 MV/cm. Table 2 presents, in detail, all stress parameters of the second experiment. A difference between the distributions was not observed which indicated that the starting field up to 8 MV/cm does not influence the breakdown fields. In the third experiment with the stress parameters of Table 3 the low bias level of the ramp, E~owand Estart were varied from 0.2 MV/cm to 8.1 MV/cm. The measured breakdown distributions were identical for
Table 2. Stress conditions for a unipolar pulsed ramp with various Est,, values R = E+t+p/tst+p
[MV/cm/s] 0.1/1.0 0.1/1.0 0.1/1.0 0.1/1.0
E+.... [MV/cm]
tlo+ Is]
Elow [MV/cm]
1.1 2.1 4.1 8.1
1.0 1.0 1.0 1.0
1.0 1.0 1.0 1.0
E+. . . .
tlow
Eiow
[MV/cm]
[s]
[MV/cm]
0.2 1.1 2.1 4.1 8.1
1.0 1.0 1.0 1.0 1.0
0.1 1.0 2.0 4.0 8.0
R = Est+p/tst+
[MV/cm/s] 0.1/1.0 0.1/I.0 0.1/1.0 0.1/1.0 0.1/1.0
all U P R values. This implied that the level of the low field bias up to 8.1 MV/cm does not affect the breakdown distributions of these oxides either. In summary, it can be concluded from the results of these experiments that the unipolar pulsed ramp [9, 14], for a wide range of ramp parameters, does not result in a breakdown distribution different to that of a staircase ramp. The significance of the results is that a U P R can be applied in an RVS measurement instead of a staircase ramp without changing breakdown fields.
COMBINED RVS/CVS STRESS Combined RVS/CVS measurements were performed with the bias conditions shown in Fig. I. This type of measurement had been used for the characterization of oxides which were thermally grown on polycrystalline silicon. It was found that the pre-stress increased the t~ [12, 13]. A t~ enhancement was also recorded in experiments for MOS gate oxides. Figure 5 shows tbd distributions of a virgin and pre-stressed 15.4 nm MOS gate oxide in a Weibull plot. The virgin oxide was only subjected to a CVS while the pre-stressed oxide was biased with a ramp prior to the CVS (Fig. 1). It is clear from Fig. 5 that a pre-stress can increase t~. From other experiments with pre-stressed oxides it can be concluded that the tb~ enhancement is
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t
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I
'
~
~llml
i
t
I
I
fO
Fig. 5. t~ Distributions of virgin and pre-stressed 15.4 nm gate oxides on an n-type substrate for a CVS at 12.6MV/cm. The pre-stressing ramp rate was R = (0.05 MV/cm)/s.
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A. Martin et al.
strongly dependent on the oxide thickness and decreases for thinner oxides [8]. It also depends on the ramp rate of the pre-stressing ramp. An example for this dependence is shown in the next section. Since breakdowns which occurred during the ramp were included in the t~ distributions the t~ enhancement is not a screening effect. In order to verify that the enhancement due to the pre-stress is not an artefact of the U P R , measurements were performed with pre-stresses consisting of a staircase ramp and, in comparison, a U P R . Figure 6 presents the t~ distributions of two pre-stressed oxides which were subjected to a U P R and a staircase ramp. The distributions of the pre-stressed oxides are statistically identical and both show a tu enhancement. For comparison, the distribution of the virgin oxide is also shown in Fig. 6. Measurement results from oxide processes of other semiconductor manufacturers and different thicknesses [18] are in agreement with the observation from Fig. 6. This is an important finding which clearly shows that the same tbd enhancement is measurable with a U P R and staircase ramp. Measurements were also performed for various pre-stress conditions of the U P R to assess the dependence of the t~d enhancement on E~t.... Figure 7 shows tbd distributions of two pre-stressed gate oxides with ramps started at 3 and 7 MV/cm and t~ distributions of a virgin gate oxide. It can be observed that the distribution of the pre-stressed oxides are statistically the same. Identical results were found for oxides with other thicknesses which indicate that an E, . . . . up to 7 MV/cm does not affect the t~ distribution of the pre-stressed oxide. The results from these experiments clearly demonstrate that the tbd increase is an effect which is mainly influenced by fields in the F - N tunneling regime and is, therefore, of great importance for highly accelerated reliability measurements.
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Fig. 7. tu Distributions of a virgin and two pre-stressed 20 nm gate oxides on an n-type substrate for a CVS at 10 MV/cm and UPR starting at: E~,~r,= 3 and 7 MV/cm.
The charge to breakdown (Q~) was also monitored during the combined stress. Q~ distributions for a virgin and a pre-stressed 10.9 nm oxide are shown in Fig. 8. Q~ is the sum of the injected charge of the pre-stress and the injected charge during the CVS until breakdown. It can be seen that the Q~ is higher with the pre-stress. Increased Q~ and t~ due to a ramped pre-stress can overestimate oxide reliability. Therefore, it is important to test for these increases when a ramp is performed prior to a CVS and to take a possible t~ enhancement into account.
tu DEPENDENCE ON RAMP RATE In a further experiment on a 20 nm gate oxide the ramp rate of the pre-stressing U P R was varied from (0.1 MV/cm)/4 s to (0.1 MV/cm)/0.15 s, while Eto~r = 1 MV/cm and t~ow= 1 s were constant. Figure 9 shows the results of the measurements. The tbd distributions of the virgin oxide and the
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Fig. 6. t~ Distributions of a virgin and two pre-stressed 22.5nm gate oxides on p-type silicon for a CVS at 11 MV/cm. The pre-stresses consisted of a UPR and a staircase ramp.
10
IO
Fig. 8. Q~ distributions of virgin and pre-stressed 10.9 nm gate oxides on an n-type substrate for a CVS at 12.8 MV/cm.
1049
Voltage stress on MOS gate oxides ,
I -0.~ -1 -1.5 -2 -2.5 -3 -3.5
i
.-
all pre-stressed oxides since it depends strongly on the processing conditions, the oxide thicknesses, the pre-stress parameters and the time resolution of the measurement equipment [8, 11, 21].
j
DISCUSSION OF OXIDE BREAKDOWN AND the INCREASE CVS at 10MVIcm
;o
looo
Fig. 9. t~ Distributions of a virgin and four pre-stressed 20 nm gate oxides on an n-type substrate using pre-stresses with different ramp rates.
pre-stressed oxide with the fastest ramp show identical tbd values. No difference in tt~ is recognized between these two distributions. For all of the other ramps with slower ramp rates the pre-stress enhanced the t~. This is an important result. It indicates that with a fast pre-stressing ramp the combined RVS/CVS stress can be used as a reliability measurement without introducing a t~ enhancement. The Qbd distributions of this set of measurements showed the same trend as those of t~. The Q~ increase was large for slow ramps and vanished for the fastest ramp [8].
l-t CHARACTERISTICS Figure 10 shows the current-time (l-t) characteristics of the CVS measurements of Fig. 9 for a virgin and four pre-stressed oxides. Figure 10 demonstrates that the CVS currents are different at the start and converge after a short time. It appears that the same amount of net charge is trapped in the oxides (virgin and pre-stressed) from this point on. A similar result was obtained [19] when the l - t curves converged for a CVS and a CVS with an additional stress. Not only the current values of the l - t curves are different. It can be seen from Fig. 10 that the curvature also differs for virgin and pre-stressed oxides. The virgin oxide exhibits an I-t characteristic with an initial steep increase due to positive charge build up in the oxide [20]. For all pre-stressed oxides this increase is much lower or even disappears [21]. The later decrease of the current indicates that negative charge trapping is dominant in the oxide [19l. From measurement results on pre-stressed oxides with current bias [21] it is clear that the initial rate of positive charge build up during the CVS plays a significant role for oxide degradation and breakdown. The lower the rate of initial charge trapping at the high CVS bias the higher the enhancement of t~ can become. However, this effect can not be seen for
Two types of oxide breakdown can be observed: the electrical and the thermal breakdown. For thick oxides, only thermal oxide breakdowns are measured with a reliability stress when the capacitor is melted at a defective oxide site and a conductive path is established. However, for thin oxide, tox < 5 nm, local electrical breakdown can also be detected [22]. For thick oxides it is possible that many electrical breakdowns occur before the final thermal breakdown. It is understood that an electrical breakdown does not result in a conductive path through the oxide. However, a thermal breakdown occurs consequently after an electrical breakdown when the energy is sufficient to melt the material surrounding the defective site [23]. This can occur at high field, or, e.g. at sites with oxide thinning. Local electrical breakdowns are reported in the literature [22, 23] and are observable by light emission from the breakdown site due to current crowding. However, these local electrical breakdowns are not destructive. Therefore, it is possible that during the pre-stress many electrical breakdowns occur which do not destroy the oxide. By eliminating many regions where electrical breakdown can trigger thermal breakdown the measured time to thermal breakdown (t~) can increase due to a lower probability of thermal breakdown at high fields. This is one possible explanation for the t~ increase. However, this mechanism can not be detected by electrical breakdown measurements of thick oxides as they were performed in this work. Another possible reason for a t~ increase can be
:~
-- -5..5
I b. "'
I
I c'zl
i
~-5.6
~-3.7 -5.0.8I
I time Incl
10
100
Fig. 10. The initial part of current-time curves of virgin and several-ramp-rates-pre-stressed20 nm gate oxides for a CVS at 10 MV/cm.
1050
A. Martin et al.
coulombic repulsion by trapped electrons at defective sites. Wolters and van der Schoot [24] describe, in more detail, coulombic repulsion due to trapped electrons in their work. Electrons which are trapped at defective sites during the pre-stress do not degrade the oxide because of the low fields. But they repel consequently injected electrons at high fields of the CVS and, therefore, "anneal out" defects. From the observations of this study it can be said that the t~ enhancement with a pre-stress is connected to the charge trapping in the oxide layer during the steps of the pre-stress. These charges decrease the CVS current and the rate of the charge build up in the oxide at the start of the CVS. I - t characteristics in this and earlier studies have indicated that the rate of positive charge formation is an indicator of oxide degradation [21]. The lower the initial increase of the CVS current the higher is the lb,l increase. Results of more recent work [25] tie in with those of this study in that the low voltage pulses of a UPR do not enhance the tbd. It can even be said that when unipolar high frequency pulses are applied during the pre-stress, less charge is trapped in the oxide and as a result the tbd enhancement decreases [21, 26]. This gives evidence that: (1) the pulsed pre-stress does not enhance the lifetime in comparison to a pre-stressing staircase ramp, but will even decrease the t~d enhancement when sufficiently high frequencies are applied during the pre-stress; (2) the amount of trapped charge in the oxide at the beginning of the CVS has a major effect on the lbd increase. PRACTICAL APPLICATION A RVS/CVS stress with a ramp rate of R = (0.3 MV/cm)/0.3 s and CVS at 9.8 MV/cm were performed on over 5000 larger capacitors for the assessment of the combined reliability stress. Only one capacitor per site was available on the wafer.
'l fa ,
0.1
,,,W /
I
10
!00
!000
Fig. 11. Lifetime distributions of virgin and pre-stressed oxides on an n-type substrate testing large area capacitors.
i 0
1
2
3
4
5
6
7 8 9 ~d lbtVl~l
10
Fig. 12. Histogram of defect related breakdowns of the pre-stressed oxides testing large area capacitors of data of Fig. 11.
Therefore, the sample sizes for the measurements are limited to less than 40 capacitors. The tbd distributions of virgin and pre-stressed oxides are compared in Fig. 11. Taking into account the small sample sizes, it can be observed that the tbd are distributed in the same way. This shows that the fast pre-stressing ramp does not increase t~. Note that many breakdowns happened at time zero. Only in the case of the pre-stressing ramp can these initial breakdowns be further analyzed because they occurred during the ramp of the combined stress. Figure 12 shows a histogram of the breakdown voltages recorded during the ramp. It is obvious that additional information is provided from this detailed distribution of extrinsic breakdowns. Since the extrinsic failures are the most important, this aspect demonstrates the significant advantage of the combined ramped/ constant stress. SUMMARY AND CONCLUSIONS In this paper a combined ramped/constant stress has been assessed for the monitoring of breakdown properties of MOS gate oxides. A unipolar pulsed ramp (UPR) was applied during the ramped pre-stress. It has been shown that the UPR for a range of stress parameters results in breakdown distributions identical to those of a widely used staircase ramp. From the results of this study it can be concluded that a UPR can replace a staircase ramp in applications of a simple RVS and combined RVS/CVS without altering the measured results. The results of the combined RVS/CVS measurements have shown that the t~ can be increased when a slow ramp is applied during the pre-stress. However, for a fast pre-stressing ramp no t~ enhancement was monitored. In this case, the combined RVS/CVS measurement is a valuable tool for the characterization of breakdown properties in a short time. Extrinsic failures are recorded with a
Voltage stress on MOS gate oxides high resolution during the pre-stressing ramp while intrinsic t~ values are measured during the constant stress. It was verified that the tbd increase with a pre-stress is not a screening effect of the preceding ramp or an artefact of the U P R . The tb~ increase was only observed for field biases in the F - N regime. It is a phenomenon restricted to this range which is of importance for highly accelerated reliability measurements. Further, the study gave evidence that the charge trapping during the pre-stress is the reason for the lbd enhancement. The rate of initial positive charge trapping during the CVS is an indicator for oxide degradation and breakdown. Two possible physical mechanisms are discussed which can both explain the t~ increase by an "annealing o u t " of defective sites. When the RVS/CVS stress is applied to a gate oxide as a reliability measurement it is necessary to ensure that the pre-stress consists of a fast ramp which does not increase the tbd and does not overestimate oxide lifetimes at operating conditions. REFERENCES
1. Chen, I. C., Holland, S. and Hu, C., A quantitative model for time-dependent breakdown in SiO2. IEEE International ReliabiliO' Physics Symposium (IRPS'85), 1985, pp. 24-31. 2. Suehle, J. S., Chaparala, P., Messick, C., Miller, W. M. and Boyko, K., Experimental investigation of the validity of TDDB voltage acceleration models. IEEE International Wafer Level Reliability Workshop Final Report (WLR'93), 1993, pp. 59-67. 3. Kamolz, M., CSQ-test: a special J-ramp method approved for fast routine testing of thin dielectric films. International Wafer Level Reliability Workshop Final Report (WLR'91), 1991, pp. 121-132. 4. Vollertsen, R.-P. and Abadeer, W. W., Influence of stress design on the parameters evaluated from breakdown distributions of thin oxide. Proceedings of the 4th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'93), 1993, pp. 195-200. 5. Strong, A.. Wu, E. and Bolam, R., Dielectric step stress and life stress comparison. IEEE International Integrated Reliability Workshop Final Report (IRW'95), 1995, p. 165. 6. Schnable, G. L. and Swartz, G. A., In-process voltage stressing to increase reliability of MOS integrated circuits. Microelectron. Reliab., 1988, 28(5), 757-781. 7. Berman, A., Time-zero dielectric reliability test by a ramped method. IEEE International Reliability Physics Symposium (1PRS'81), 1981, pp. 204-209. 8. Martin, A., Suehle, J. S., Chaparala, P., O'Sullivan, O., Mathewson, A. and Messick, C., Assessing MOS gate oxide reliability on wafer level with ramped and constant voltage and current stress. IEEE International Integrated Reliability Workshop Final Report (IRW'95), 1995, pp. 81-91. 9. Hallberg, O., NMOS breakdown characteristics compared with accelerated life tests and field data. IEEE International Reliability Physics Symposium (IRPS'81), 1981, pp. 28-33. 10. King, J. C., Chan, W. Y. and Hu, C., Efficient gate oxide defect screen for VLSI reliability. 1EEE International Electron Devices Meeting (IEDM'94), 1994, pp. 597~500.
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11. Martin, A., Ribbrock, T., O'Sullivan, P. and Mathewson, A., Enhancement of t~ of MOS gate oxides with a single-step pre-stress prior to a CVS in the Fowler-Nordheim regime. Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'96), pp. 1647-1650. 12. Martin, A., O'Sullivan, P. and Mathewson, A., Comparison of inter-polysilicon oxide lifetime using ramped and constant voltage measurements. Proceedings of the 5th European Symposium on ReliabiliO" of Electron Devices, Failure Physics and Analysis (ESREF'94), 1994, pp. 163-168. 13. Martin, A., O'Sullivan, P. and Mathewson, A., Correlation of lifetimes from CVS to RVS using the 1/E-model for thermally grown oxides on polysilicon. IEEE International Integrated Reliability Workshop Final Report (IRW'94), 1994, pp. 106-112. 14. Heimann, P. A., An operational definition for breakdown of thin thermal oxides of silicon. 1EEE Trans. Electron Devices, 1983, 30(10), 1366-1368. 15. Neely, J. S., Measurement and analysis of breakdown fields on thin oxide MOS capacitors with high series resistance, international Wafer Level Reliability Workshop Final Report (WLR'91), 1991, pp. I11-120. 16. Martin, A., O'Sullivan, P., Mathewson, A., Mason B. and Beech, C., Evaluation of the lifetime and failure probability for interpoly oxides from RVS measurements. Microelectron. J., 1994, 25(7), 553-557. 17. Martin, A., O'Sullivan, P. and Mathewson, A., A practical lifetime prediction method for interpoly oxides. Electron Tech., 1994, 27(1), 55 64. 18. Martin, A., O'Sullivan, P. and Mathewson, A., Assessment of a unipolar pulsed ramp for the characterisation of MOS gate oxide reliability. IEEE International Integrated Reliability Workshop Final Report (IRW'95), 1995, p. 158. 19. Olivo, P., Ricc6, B, and Sangiori, E., Electron trapping/detrapping within thin SiO2 films in the high field tunneling regime. J. Appl. Phys., 1983, 54(9), 5267-5276. 20. Weinberg, Z. A. and Nguyen, T. N., The relation between positive charge and breakdown in metaloxide-silicon structures. J. Appl. Phys., 1987, 61(5), 1947-1956. 21. Martin, A., Suehle, J. S., Chaparala, P., O'Sullivan, P. and Mathewson, A., A new oxide degradation mechanism for stresses in the Fowler-Nordheim tunneling regime. IEEE International ReliabiliO, Physics Symposium (IRPS'96), 1996, pp. 67-76. 22. Depas, M., Heyns, M. M. and Mertens, P. W., Ultra-thin gate oxide breakdown. European Semiconductor, March 1996, 45-46. 23. Nafria, M., Sun6, J. and Aymerich, X., Exploratory observations of post-breakdown conduction in polycrystalline-silicon and metal-gated thin-oxide metaloxide-semiconductor capacitors. J. Appl. Phys., 1993, 73(1), 205-215. 24. Wolters, D. R. and van der Schoot, J. J., Kinetics of charge trapping in dielectrics. J. Appl. Phys., 1985, 58(2), 831-837. 25. Duane, R., Martin, A., O'Donovan, P., Hurley, P., O'Sullivan, P. and Mathewson, A., Investigation of trapped charge in oxides under Fowler-Nordheim stress using low-bias conditions. Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'96), pp. 1623-1626. 26. Chaparala, P., Suehle, J. S., Messick, C. and Roush, M., Electric field dependent dielectric breakdown of intrinsic SiO2 films under dynamic stress. IEEE International Reliability Physics Symposium (IRPS'96), 1996, pp. 61-66.
Pergamon PII: S0026--2714(96)00267-3
0026-2714/97 $17.00 + 0.00
STUDY OF UNIPOLAR PULSED RAMP AND COMBINED RAMPED/CONSTANT VOLTAGE STRESS ON MOS GATE OXIDES A. M A R T I N , P. O ' S U L L I V A N and A. M A T H E W S O N National Microelectronics Research Centre (NMRC), University College Cork, Lee Maltings, Prospect Row, Cork, Ireland (Received 31 January 1996; in revised form 20 June 1996)
Al~tract--MOS gate oxide capacitors over a wide range of oxide thicknesses (10.9-28 nm) were stressed using a unipolar pulsed voltage ramp and combined ramped/constant voltage stress measurements. The reliability measurements were performed with several different bias conditions in order to assess the effects of the measurement conditions on times to breakdown and breakdown fields. In the first part it was verified that the unipolar pulsed ramp yields breakdown distributions which are identical to those of a widely used staircase ramp. In the second part the unipolar pulsed ramp was used for pre-stress prior to a constant stress and measurement results were compared to those of a ramped/constant stress with a staircase ramp. In several cases a ramp prior to a constant stress increases time to breakdown. The observations made in this study imply that the time to breakdown of a constant stress in the Fowler-Nordheim tunneling regime is strongly dependent on charge trapping and, therefore, on the stressing history of the oxide. Finally, it is shown that the combined ramped/constant voltage stress is a valuable tool for monitoring extrinsic and intrinsic breakdown properties when applying stress parameters in the correct way. © 1997 Elsevier Science Ltd.
INTRODUCTION The ramped voltage stress (RVS) and constant voltage stress (CVS) are widely used in industry for the characterization of breakdown properties of MOS gate oxides. RVS records, in a short time, defect related and intrinsic breakdowns of an oxide. However, CVS measurements monitor the time to breakdown (t~) of the oxide. Because the lifetime at operating voltage is important for long term reliability, the t~ of the CVS is used nearly exclusively for the prediction of lifetimes [1, 2]. The t~ of a CVS is traded as a standard for the characterization of oxide quality. But the CVS has the disadvantage of monitoring the defect related breakdowns with poor resolution unless the stress bias is set to very low fields which would result in measurement times in the order of hours, days or weeks. Such long measurements are not suitable for short wafer level reliability measurements. When the advantages of CVS and RVS are combined the stress sequence of Fig. 1 can be used for reliability measurements. The aim of this study is the assessment of the time efficient combined reliability stress for monitoring extrinsic oxide breakdowns and intrinsic t~ which can be subsequently used for lifetime predictions. The significance of the work must be seen in the following aspects. Similar combined stresses (Fig. 1) are performed in industry for long term oxide monitoring [3, 4] but the effect of the pre-stress is neglected. The extrinsic breakdowns of an oxide reliability measurement are the
most important since they cause early field failures. Therefore, it is necessary to monitor them with a high resolution which can be achieved with a combined ramped/constant stress without introducing long measurement times. A pre-stressing voltage ramp is applied prior to the CVS. This type of measurement is often used but the form of the pre-stress varies for different semiconductor manufacturers [3, 5, 6]. The pre-set can consist of a staircase ramp [3, 7], a unipolar pulsed ramp (UPR) [8, 9] or several steps with irregular step widths (tstep) and step heights (Es,ep) [4-6, 10, 11]. In this study a U P R is applied as the pre-stress. For the combined stress of Fig. 1, the t~ is only recorded for the CVS. The time of the pre-stressing ramp is not included in the t~. However, breakdowns which occurred during the ramp were included in the analysis and in the tbd distributions of Weibull plots a s tbd = 0 S.
In earlier work on thermally grown oxides on polycrystalline silicon [12, 13] it was observed that when a CVS measurement is preceded by a ramp, a longer t~ and higher charge to breakdown (Q~) can be monitored than with a CVS alone. This important aspect is investigated in this study for MOS gate oxides because long term oxide reliability can be overestimated when t~ and Q~ are enhanced due to the combined stress of Fig. 1. In the first part of this work breakdown fields of a U P R (Fig. 2) were compared to those of a staircase ramp for a wide range of stress parameters to
1045
1046
A. Martin et al. Fmkl[MVlcml RVS
E
Table 1. Stress conditions for the comparison between a staircase ramp and a unipolar pulsed ramp
cvs
Ramp type
CV
memmed Esiep
curn~!
R = ~,~v/t~,o r [MV/cm/s]
N .... [MV/cm]
t,o~ [s]
No~ [MV/cm]
Staircase
0.1/I.0
l.l
--
--
UPR
0.1/1.0 0.1/1.0 0.1/1.0 0.1/1.0
1.1 1.1 1.1 1.1
0.15 1.0 2.5 5.0
1.0 1.0 1.0 1.0
imelpity dzeck
E $1& Ek~ ImI
1
I
t step
I low
;
'.qc--~,'
l
0
2
3
4
Fig. 1. Schematic bias conditions of the combined ramped/constant voltage stress performed with a unipolar pulsed ramp.
validate the U P R for the c o m b i n e d r a m p e d / c o n s t a n t stress. In the second part the c o m b i n e d stress is performed with various stress conditions for the assessment o f the tbd increase. In order to gain insight into the t~ e n h a n c e m e n t with a pre-stress c u r r e n t time ( l - t ) characteristics were investigated. Finally, it is s h o w n that a U P R / C V S stress is a useful tool for m o n i t o r i n g oxide reliability without overestimating oxide lifetimes when the stress parameters are carefully chosen. EXPERIMENTS AND SAMPLES All m e a s u r e m e n t s were performed on the wafer level with a HP4062 Parametric Test System at room t e m p e r a t u r e a n d biases in the F o w l e r - N o r d h e i m ( F - N ) tunneling regime. M O S gate oxides were stressed in a thickness range o f 10.9-28 nm. F o r the small area capacitors, 10 duplicates per site and 40 sites per wafer allowed m a n y measurements to be carried out on the same statistical population. All
measurements were performed with the silicon substrate in accumulation. The oxides were thermally grown o n an n- a n d p-type silicon substrate. Test capacitors had degenerately doped n+-polysilicon gates. A U P R (Fig. 2) was applied for RVS measurements in this work. The r a m p was first described in the work of Hallberg [9]. Later, its advantages were discussed in the work o f H e i m a n n [14] a n d the use o f the U P R instead o f a staircase r a m p was suggested. In a recent publication of Neely [15] this r a m p was proposed to be necessary for thin oxide testing. It has the a d v a n t a g e of detecting oxide b r e a k d o w n at low bias levels, E~ow,without placing an upper limit on the tunnel currents at the stress level with a pre-defined b r e a k d o w n current. The U P R was extensively used in earlier characterization work for thermally grown oxides on polycrystalline silicon [16, 17]. In a set o f experiments the staircase r a m p was c o m p a r e d to a U P R with various parameters for tjo~, E~ow a n d Est.... M e a s u r e m e n t s were performed on a 20 n m M O S gate oxide. The r a m p rate was defined as R = E~,op/t,,ep for all applied ramps. In the first experiment RVS was performed with a staircase r a m p and a UPR. The u n i p o l a r r a m p times at ELowranged from 0.15 s to 5 s. The stress conditions are listed in detail in Table 1. Figure 3 presents the m e a s u r e m e n t results which show no deviations between the intrinsic parts of the
laUStlfelDent
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O
o.s
cumulative failure
i ha(-L~(l-F))
C
-0. -I
Bm
-1.5
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-2.3 ..~ !
!
tl~t
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Fig. 2. Schematic bias conditions of the unipolar pulsed ramp (UPR).
-3.5
Sbd IMV/ml Fig. 3. Breakdown distributions of a staircase ramp and the unipolar pulsed ramp with various t~owvalues for a 20 nm oxide on an n-type silicon substrate.
1047
Voltage stress on MOS gate oxides 1 0 . S ] ~ ~ = ~ = = = = ~
,il-Y
I
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Table 3. Stress conditions for a unipolar pulsed ramp with various E ~ and E~owvalues
/
I
I
+ +I2
3
] 4
5
6
7
8
9
10
Field [MVIcrai
Fig. 4. ~ V characteristics of a staircase ramp and a UPR with &w = 2.5 s and a ramp rate of (0.1 MV/cm)/1 s of data of Fig. 3.
breakdown distributions. This is an important result because the staircase ramp and the U P R exhibit identical breakdown fields. The current-voltage (l-V) characteristics were recorded during the RVS measurements of the first experiment. In Fig. 4 the I - V characteristics of the staircase ramp are compared to those of a U P R with t~ow= 2.5 s. The l - V c u r v e s were chosen from samples which broke down at fields equal to Ebds0 of the Weibull plot in Fig. 3. It can be observed that the I - V characteristics are identical for a staircase ramp and a UPR. Only very small statistical site to site variations can be seen from the inset of Fig. 4. This gives further evidence that a U P R and a staircase ramp result in identical breakdown distributions. In terms of Q~, a U P R and a staircase ramp inject the same quantity of charge during the measurement independently of the low voltage step of the UPR, since I - V curves are identical (Qb~ = EL x /step). In the second experiment the starting field of the U P R was varied: 1.1 MV/cm < E+t,F,< 8.1 MV/cm. Table 2 presents, in detail, all stress parameters of the second experiment. A difference between the distributions was not observed which indicated that the starting field up to 8 MV/cm does not influence the breakdown fields. In the third experiment with the stress parameters of Table 3 the low bias level of the ramp, E~owand Estart were varied from 0.2 MV/cm to 8.1 MV/cm. The measured breakdown distributions were identical for
Table 2. Stress conditions for a unipolar pulsed ramp with various Est,, values R = E+t+p/tst+p
[MV/cm/s] 0.1/1.0 0.1/1.0 0.1/1.0 0.1/1.0
E+.... [MV/cm]
tlo+ Is]
Elow [MV/cm]
1.1 2.1 4.1 8.1
1.0 1.0 1.0 1.0
1.0 1.0 1.0 1.0
E+. . . .
tlow
Eiow
[MV/cm]
[s]
[MV/cm]
0.2 1.1 2.1 4.1 8.1
1.0 1.0 1.0 1.0 1.0
0.1 1.0 2.0 4.0 8.0
R = Est+p/tst+
[MV/cm/s] 0.1/1.0 0.1/I.0 0.1/1.0 0.1/1.0 0.1/1.0
all U P R values. This implied that the level of the low field bias up to 8.1 MV/cm does not affect the breakdown distributions of these oxides either. In summary, it can be concluded from the results of these experiments that the unipolar pulsed ramp [9, 14], for a wide range of ramp parameters, does not result in a breakdown distribution different to that of a staircase ramp. The significance of the results is that a U P R can be applied in an RVS measurement instead of a staircase ramp without changing breakdown fields.
COMBINED RVS/CVS STRESS Combined RVS/CVS measurements were performed with the bias conditions shown in Fig. I. This type of measurement had been used for the characterization of oxides which were thermally grown on polycrystalline silicon. It was found that the pre-stress increased the t~ [12, 13]. A t~ enhancement was also recorded in experiments for MOS gate oxides. Figure 5 shows tbd distributions of a virgin and pre-stressed 15.4 nm MOS gate oxide in a Weibull plot. The virgin oxide was only subjected to a CVS while the pre-stressed oxide was biased with a ramp prior to the CVS (Fig. 1). It is clear from Fig. 5 that a pre-stress can increase t~. From other experiments with pre-stressed oxides it can be concluded that the tb~ enhancement is
,_, 0"t
t
i"+'}t I-- t l
I
'
~
~llml
i
t
I
I
fO
Fig. 5. t~ Distributions of virgin and pre-stressed 15.4 nm gate oxides on an n-type substrate for a CVS at 12.6MV/cm. The pre-stressing ramp rate was R = (0.05 MV/cm)/s.
1048
A. Martin et al.
strongly dependent on the oxide thickness and decreases for thinner oxides [8]. It also depends on the ramp rate of the pre-stressing ramp. An example for this dependence is shown in the next section. Since breakdowns which occurred during the ramp were included in the t~ distributions the t~ enhancement is not a screening effect. In order to verify that the enhancement due to the pre-stress is not an artefact of the U P R , measurements were performed with pre-stresses consisting of a staircase ramp and, in comparison, a U P R . Figure 6 presents the t~ distributions of two pre-stressed oxides which were subjected to a U P R and a staircase ramp. The distributions of the pre-stressed oxides are statistically identical and both show a tu enhancement. For comparison, the distribution of the virgin oxide is also shown in Fig. 6. Measurement results from oxide processes of other semiconductor manufacturers and different thicknesses [18] are in agreement with the observation from Fig. 6. This is an important finding which clearly shows that the same tbd enhancement is measurable with a U P R and staircase ramp. Measurements were also performed for various pre-stress conditions of the U P R to assess the dependence of the t~d enhancement on E~t.... Figure 7 shows tbd distributions of two pre-stressed gate oxides with ramps started at 3 and 7 MV/cm and t~ distributions of a virgin gate oxide. It can be observed that the distribution of the pre-stressed oxides are statistically the same. Identical results were found for oxides with other thicknesses which indicate that an E, . . . . up to 7 MV/cm does not affect the t~ distribution of the pre-stressed oxide. The results from these experiments clearly demonstrate that the tbd increase is an effect which is mainly influenced by fields in the F - N tunneling regime and is, therefore, of great importance for highly accelerated reliability measurements.
1.21
0 ~
1]
.~
-2
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~ASlalt.
~.-,u~
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tlxl [teal
I000
Fig. 7. tu Distributions of a virgin and two pre-stressed 20 nm gate oxides on an n-type substrate for a CVS at 10 MV/cm and UPR starting at: E~,~r,= 3 and 7 MV/cm.
The charge to breakdown (Q~) was also monitored during the combined stress. Q~ distributions for a virgin and a pre-stressed 10.9 nm oxide are shown in Fig. 8. Q~ is the sum of the injected charge of the pre-stress and the injected charge during the CVS until breakdown. It can be seen that the Q~ is higher with the pre-stress. Increased Q~ and t~ due to a ramped pre-stress can overestimate oxide reliability. Therefore, it is important to test for these increases when a ramp is performed prior to a CVS and to take a possible t~ enhancement into account.
tu DEPENDENCE ON RAMP RATE In a further experiment on a 20 nm gate oxide the ramp rate of the pre-stressing U P R was varied from (0.1 MV/cm)/4 s to (0.1 MV/cm)/0.15 s, while Eto~r = 1 MV/cm and t~ow= 1 s were constant. Figure 9 shows the results of the measurements. The tbd distributions of the virgin oxide and the
cumulative failure
o.~ o~
•
J , ~
CVS at lOMV/cm /
¢,
0.8
I
;r'
v i ~ oxide
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1000 tt,d (L'cl
Fig. 6. t~ Distributions of a virgin and two pre-stressed 22.5nm gate oxides on p-type silicon for a CVS at 11 MV/cm. The pre-stresses consisted of a UPR and a staircase ramp.
10
IO
Fig. 8. Q~ distributions of virgin and pre-stressed 10.9 nm gate oxides on an n-type substrate for a CVS at 12.8 MV/cm.
1049
Voltage stress on MOS gate oxides ,
I -0.~ -1 -1.5 -2 -2.5 -3 -3.5
i
.-
all pre-stressed oxides since it depends strongly on the processing conditions, the oxide thicknesses, the pre-stress parameters and the time resolution of the measurement equipment [8, 11, 21].
j
DISCUSSION OF OXIDE BREAKDOWN AND the INCREASE CVS at 10MVIcm
;o
looo
Fig. 9. t~ Distributions of a virgin and four pre-stressed 20 nm gate oxides on an n-type substrate using pre-stresses with different ramp rates.
pre-stressed oxide with the fastest ramp show identical tbd values. No difference in tt~ is recognized between these two distributions. For all of the other ramps with slower ramp rates the pre-stress enhanced the t~. This is an important result. It indicates that with a fast pre-stressing ramp the combined RVS/CVS stress can be used as a reliability measurement without introducing a t~ enhancement. The Qbd distributions of this set of measurements showed the same trend as those of t~. The Q~ increase was large for slow ramps and vanished for the fastest ramp [8].
l-t CHARACTERISTICS Figure 10 shows the current-time (l-t) characteristics of the CVS measurements of Fig. 9 for a virgin and four pre-stressed oxides. Figure 10 demonstrates that the CVS currents are different at the start and converge after a short time. It appears that the same amount of net charge is trapped in the oxides (virgin and pre-stressed) from this point on. A similar result was obtained [19] when the l - t curves converged for a CVS and a CVS with an additional stress. Not only the current values of the l - t curves are different. It can be seen from Fig. 10 that the curvature also differs for virgin and pre-stressed oxides. The virgin oxide exhibits an I-t characteristic with an initial steep increase due to positive charge build up in the oxide [20]. For all pre-stressed oxides this increase is much lower or even disappears [21]. The later decrease of the current indicates that negative charge trapping is dominant in the oxide [19l. From measurement results on pre-stressed oxides with current bias [21] it is clear that the initial rate of positive charge build up during the CVS plays a significant role for oxide degradation and breakdown. The lower the rate of initial charge trapping at the high CVS bias the higher the enhancement of t~ can become. However, this effect can not be seen for
Two types of oxide breakdown can be observed: the electrical and the thermal breakdown. For thick oxides, only thermal oxide breakdowns are measured with a reliability stress when the capacitor is melted at a defective oxide site and a conductive path is established. However, for thin oxide, tox < 5 nm, local electrical breakdown can also be detected [22]. For thick oxides it is possible that many electrical breakdowns occur before the final thermal breakdown. It is understood that an electrical breakdown does not result in a conductive path through the oxide. However, a thermal breakdown occurs consequently after an electrical breakdown when the energy is sufficient to melt the material surrounding the defective site [23]. This can occur at high field, or, e.g. at sites with oxide thinning. Local electrical breakdowns are reported in the literature [22, 23] and are observable by light emission from the breakdown site due to current crowding. However, these local electrical breakdowns are not destructive. Therefore, it is possible that during the pre-stress many electrical breakdowns occur which do not destroy the oxide. By eliminating many regions where electrical breakdown can trigger thermal breakdown the measured time to thermal breakdown (t~) can increase due to a lower probability of thermal breakdown at high fields. This is one possible explanation for the t~ increase. However, this mechanism can not be detected by electrical breakdown measurements of thick oxides as they were performed in this work. Another possible reason for a t~ increase can be
:~
-- -5..5
I b. "'
I
I c'zl
i
~-5.6
~-3.7 -5.0.8I
I time Incl
10
100
Fig. 10. The initial part of current-time curves of virgin and several-ramp-rates-pre-stressed20 nm gate oxides for a CVS at 10 MV/cm.
1050
A. Martin et al.
coulombic repulsion by trapped electrons at defective sites. Wolters and van der Schoot [24] describe, in more detail, coulombic repulsion due to trapped electrons in their work. Electrons which are trapped at defective sites during the pre-stress do not degrade the oxide because of the low fields. But they repel consequently injected electrons at high fields of the CVS and, therefore, "anneal out" defects. From the observations of this study it can be said that the t~ enhancement with a pre-stress is connected to the charge trapping in the oxide layer during the steps of the pre-stress. These charges decrease the CVS current and the rate of the charge build up in the oxide at the start of the CVS. I - t characteristics in this and earlier studies have indicated that the rate of positive charge formation is an indicator of oxide degradation [21]. The lower the initial increase of the CVS current the higher is the lb,l increase. Results of more recent work [25] tie in with those of this study in that the low voltage pulses of a UPR do not enhance the tbd. It can even be said that when unipolar high frequency pulses are applied during the pre-stress, less charge is trapped in the oxide and as a result the tbd enhancement decreases [21, 26]. This gives evidence that: (1) the pulsed pre-stress does not enhance the lifetime in comparison to a pre-stressing staircase ramp, but will even decrease the t~d enhancement when sufficiently high frequencies are applied during the pre-stress; (2) the amount of trapped charge in the oxide at the beginning of the CVS has a major effect on the lbd increase. PRACTICAL APPLICATION A RVS/CVS stress with a ramp rate of R = (0.3 MV/cm)/0.3 s and CVS at 9.8 MV/cm were performed on over 5000 larger capacitors for the assessment of the combined reliability stress. Only one capacitor per site was available on the wafer.
'l fa ,
0.1
,,,W /
I
10
!00
!000
Fig. 11. Lifetime distributions of virgin and pre-stressed oxides on an n-type substrate testing large area capacitors.
i 0
1
2
3
4
5
6
7 8 9 ~d lbtVl~l
10
Fig. 12. Histogram of defect related breakdowns of the pre-stressed oxides testing large area capacitors of data of Fig. 11.
Therefore, the sample sizes for the measurements are limited to less than 40 capacitors. The tbd distributions of virgin and pre-stressed oxides are compared in Fig. 11. Taking into account the small sample sizes, it can be observed that the tbd are distributed in the same way. This shows that the fast pre-stressing ramp does not increase t~. Note that many breakdowns happened at time zero. Only in the case of the pre-stressing ramp can these initial breakdowns be further analyzed because they occurred during the ramp of the combined stress. Figure 12 shows a histogram of the breakdown voltages recorded during the ramp. It is obvious that additional information is provided from this detailed distribution of extrinsic breakdowns. Since the extrinsic failures are the most important, this aspect demonstrates the significant advantage of the combined ramped/ constant stress. SUMMARY AND CONCLUSIONS In this paper a combined ramped/constant stress has been assessed for the monitoring of breakdown properties of MOS gate oxides. A unipolar pulsed ramp (UPR) was applied during the ramped pre-stress. It has been shown that the UPR for a range of stress parameters results in breakdown distributions identical to those of a widely used staircase ramp. From the results of this study it can be concluded that a UPR can replace a staircase ramp in applications of a simple RVS and combined RVS/CVS without altering the measured results. The results of the combined RVS/CVS measurements have shown that the t~ can be increased when a slow ramp is applied during the pre-stress. However, for a fast pre-stressing ramp no t~ enhancement was monitored. In this case, the combined RVS/CVS measurement is a valuable tool for the characterization of breakdown properties in a short time. Extrinsic failures are recorded with a
Voltage stress on MOS gate oxides high resolution during the pre-stressing ramp while intrinsic t~ values are measured during the constant stress. It was verified that the tbd increase with a pre-stress is not a screening effect of the preceding ramp or an artefact of the U P R . The tb~ increase was only observed for field biases in the F - N regime. It is a phenomenon restricted to this range which is of importance for highly accelerated reliability measurements. Further, the study gave evidence that the charge trapping during the pre-stress is the reason for the lbd enhancement. The rate of initial positive charge trapping during the CVS is an indicator for oxide degradation and breakdown. Two possible physical mechanisms are discussed which can both explain the t~ increase by an "annealing o u t " of defective sites. When the RVS/CVS stress is applied to a gate oxide as a reliability measurement it is necessary to ensure that the pre-stress consists of a fast ramp which does not increase the tbd and does not overestimate oxide lifetimes at operating conditions. REFERENCES
1. Chen, I. C., Holland, S. and Hu, C., A quantitative model for time-dependent breakdown in SiO2. IEEE International ReliabiliO' Physics Symposium (IRPS'85), 1985, pp. 24-31. 2. Suehle, J. S., Chaparala, P., Messick, C., Miller, W. M. and Boyko, K., Experimental investigation of the validity of TDDB voltage acceleration models. IEEE International Wafer Level Reliability Workshop Final Report (WLR'93), 1993, pp. 59-67. 3. Kamolz, M., CSQ-test: a special J-ramp method approved for fast routine testing of thin dielectric films. International Wafer Level Reliability Workshop Final Report (WLR'91), 1991, pp. 121-132. 4. Vollertsen, R.-P. and Abadeer, W. W., Influence of stress design on the parameters evaluated from breakdown distributions of thin oxide. Proceedings of the 4th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'93), 1993, pp. 195-200. 5. Strong, A.. Wu, E. and Bolam, R., Dielectric step stress and life stress comparison. IEEE International Integrated Reliability Workshop Final Report (IRW'95), 1995, p. 165. 6. Schnable, G. L. and Swartz, G. A., In-process voltage stressing to increase reliability of MOS integrated circuits. Microelectron. Reliab., 1988, 28(5), 757-781. 7. Berman, A., Time-zero dielectric reliability test by a ramped method. IEEE International Reliability Physics Symposium (1PRS'81), 1981, pp. 204-209. 8. Martin, A., Suehle, J. S., Chaparala, P., O'Sullivan, O., Mathewson, A. and Messick, C., Assessing MOS gate oxide reliability on wafer level with ramped and constant voltage and current stress. IEEE International Integrated Reliability Workshop Final Report (IRW'95), 1995, pp. 81-91. 9. Hallberg, O., NMOS breakdown characteristics compared with accelerated life tests and field data. IEEE International Reliability Physics Symposium (IRPS'81), 1981, pp. 28-33. 10. King, J. C., Chan, W. Y. and Hu, C., Efficient gate oxide defect screen for VLSI reliability. 1EEE International Electron Devices Meeting (IEDM'94), 1994, pp. 597~500.
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11. Martin, A., Ribbrock, T., O'Sullivan, P. and Mathewson, A., Enhancement of t~ of MOS gate oxides with a single-step pre-stress prior to a CVS in the Fowler-Nordheim regime. Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'96), pp. 1647-1650. 12. Martin, A., O'Sullivan, P. and Mathewson, A., Comparison of inter-polysilicon oxide lifetime using ramped and constant voltage measurements. Proceedings of the 5th European Symposium on ReliabiliO" of Electron Devices, Failure Physics and Analysis (ESREF'94), 1994, pp. 163-168. 13. Martin, A., O'Sullivan, P. and Mathewson, A., Correlation of lifetimes from CVS to RVS using the 1/E-model for thermally grown oxides on polysilicon. IEEE International Integrated Reliability Workshop Final Report (IRW'94), 1994, pp. 106-112. 14. Heimann, P. A., An operational definition for breakdown of thin thermal oxides of silicon. 1EEE Trans. Electron Devices, 1983, 30(10), 1366-1368. 15. Neely, J. S., Measurement and analysis of breakdown fields on thin oxide MOS capacitors with high series resistance, international Wafer Level Reliability Workshop Final Report (WLR'91), 1991, pp. I11-120. 16. Martin, A., O'Sullivan, P., Mathewson, A., Mason B. and Beech, C., Evaluation of the lifetime and failure probability for interpoly oxides from RVS measurements. Microelectron. J., 1994, 25(7), 553-557. 17. Martin, A., O'Sullivan, P. and Mathewson, A., A practical lifetime prediction method for interpoly oxides. Electron Tech., 1994, 27(1), 55 64. 18. Martin, A., O'Sullivan, P. and Mathewson, A., Assessment of a unipolar pulsed ramp for the characterisation of MOS gate oxide reliability. IEEE International Integrated Reliability Workshop Final Report (IRW'95), 1995, p. 158. 19. Olivo, P., Ricc6, B, and Sangiori, E., Electron trapping/detrapping within thin SiO2 films in the high field tunneling regime. J. Appl. Phys., 1983, 54(9), 5267-5276. 20. Weinberg, Z. A. and Nguyen, T. N., The relation between positive charge and breakdown in metaloxide-silicon structures. J. Appl. Phys., 1987, 61(5), 1947-1956. 21. Martin, A., Suehle, J. S., Chaparala, P., O'Sullivan, P. and Mathewson, A., A new oxide degradation mechanism for stresses in the Fowler-Nordheim tunneling regime. IEEE International ReliabiliO, Physics Symposium (IRPS'96), 1996, pp. 67-76. 22. Depas, M., Heyns, M. M. and Mertens, P. W., Ultra-thin gate oxide breakdown. European Semiconductor, March 1996, 45-46. 23. Nafria, M., Sun6, J. and Aymerich, X., Exploratory observations of post-breakdown conduction in polycrystalline-silicon and metal-gated thin-oxide metaloxide-semiconductor capacitors. J. Appl. Phys., 1993, 73(1), 205-215. 24. Wolters, D. R. and van der Schoot, J. J., Kinetics of charge trapping in dielectrics. J. Appl. Phys., 1985, 58(2), 831-837. 25. Duane, R., Martin, A., O'Donovan, P., Hurley, P., O'Sullivan, P. and Mathewson, A., Investigation of trapped charge in oxides under Fowler-Nordheim stress using low-bias conditions. Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'96), pp. 1623-1626. 26. Chaparala, P., Suehle, J. S., Messick, C. and Roush, M., Electric field dependent dielectric breakdown of intrinsic SiO2 films under dynamic stress. IEEE International Reliability Physics Symposium (IRPS'96), 1996, pp. 61-66.