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Study on high breakdown voltage GaN-based vertical field effect transistor with interfacial charge engineering for power applications
Accepted Manuscript Study on high breakdown voltage GaN-based vertical field effect transistor with interfacial charge engineering for power applications Jiangfeng Du, Dong Liu, Yong Liu, Zhiyuan Bai, Zhiguang Jiang, Yang Liu, Qi Yu PII:
S0749-6036(17)31417-9
DOI:
10.1016/j.spmi.2017.07.018
Reference:
YSPMI 5128
To appear in:
Superlattices and Microstructures
Received Date: 9 June 2017 Revised Date:
0749-6036 0749-6036
Accepted Date: 7 July 2017
Please cite this article as: J. Du, D. Liu, Y. Liu, Z. Bai, Z. Jiang, Y. Liu, Q. Yu, Study on high breakdown voltage GaN-based vertical field effect transistor with interfacial charge engineering for power applications, Superlattices and Microstructures (2017), doi: 10.1016/j.spmi.2017.07.018. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
ACCEPTED MANUSCRIPT
Study on High Breakdown Voltage GaN-based Vertical Field Effect Transistor with Interfacial Charge Engineering for Power Applications Jiangfeng Du,a) Dong Liu, Yong Liu, Zhiyuan Bai, Zhiguang Jiang, Yang Liu, and Qi Yu State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of
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China, Chengdu, 610054, P. R. China
ABSTRACT: A high voltage GaN-based vertical field effect transistor with interfacial charge engineering (GaN ICE-VFET) is proposed and its breakdown mechanism is presented. This vertical FET features oxide trenches which show a fixed negative charge at the oxide/GaN interface. In the off-state, firstly, the trench oxide layer acts as a field plate; secondly, the n-GaN buffer layer is
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inverted along the oxide/GaN interface and thus a vertical hole layer is formed, which acts as a virtual p-pillar and laterally depletes the n-buffer pillar. Both of them modulate electric field distribution in the device and significantly increase the breakdown voltage (BV). Compared with a conventional GaN vertical FET, the BV of GaN ICE-VFET is increased from 1148V to 4153V with the
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same buffer thickness of 20 µm. Furthermore, the proposed device achieves a great improvement in the tradeoff between BV and on-resistance; and its figure of merit even exceeds the GaN one-dimensional limit.
Keywords: GaN HFETs, Vertical, Heterostructure, Breakdown voltage, Power device 1. Introduction
Gallium nitride (GaN) have attracted a lot of interest for applications in high-power electronics which operate at high
temperatures and high frequencies. In the past decades, the advancements of technology make the application prospect of GaN
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lateral heterostructure field effect transistors (FETs) more and more realistic [1~3]. However, the vertical devices are more desirable than lateral ones because of the superior on-state resistance (Ron) [4~6]. Due to the lack of suitable substrates with acceptable defect density (<106 cm-3) and process complexities, there were challenges for GaN vertical field effect transistors (GaN-VFET) to show their high performance in power electronic fileds during the past years. To solve the substrate problems of GaN-VFETs, Nie et al. reported a result of a fabricated outstanding GaN-based vertical transistor in 2014 [7]. Then Ramya et al.
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reported another excellent GaN vertical transistor by utilizing selective area regrowth p-GaN layer in 2015 [8]. These results indicate that high performance homoepitaxial growth on GaN substrates has been realized, and the fabrication technology for GaN vertical transistor has become continuously mature.
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Although the fabrication problems have been solved for a certain extent, the reported values of BV for GaN -VFETs are still not so satisfactory. The reported highest average breakdown E-field (150 V/µm) is far below the GaN theoretical limit (340 V/µm) [9]. Indeed the BV of GaN-VFETs is determined by the depletion zone of reverse-biased p-GaN/n-buffer junction [6], and the buffer layers within GaN VFETs are almost not completely depleted, which is an obstacle for increasing the BV of GaN-VFETs. Besides, there is always a serious trade-off between BV and Ron for conventional GaN-VFETs. To achieve a higher BV without Ron-deterioration, many methods have been carried out. One method is the edge-termination technology which can avoid the premature breakdown; however it does not contribute to expanding the depletion width. Moreover, p-type buried layers and Superjunction structures have been introduced in the buffer layer of GaN-VFETs to achieve high breakdown voltages [9,10]. The p-type buried layers or Superjunction for GaN-VFETs are generally formed by implanting Mg into GaN buffer layers [11]. ___________ a)
Corresponding author: Jiangfeng Du. Electronic mail: [email protected]
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ACCEPTED MANUSCRIPT However there is still a big challenge to effectively activate Mg in a buried GaN buffer layer [4], therefore the both designs face the difficulty in forming p+-pillar or p+-buried layers. It has been proved that Al2O3 shows a fixed charge when contacted with AGaN or GaN which has been studied a lot as gate oxide in GaN MISHEMTs [12,13]. In this work, we propose a novel GaN-VFETs possessing high BV without Ron deterioration by utilizing negative fixed interface charges, and a realizable fabrication process is also introduced. In the proposed device, BV can reach as high as 4153V and the figure of merit (FOM) has
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even exceeded the GaN 1D-limit. 2. Device structure and physic model
The proposed structure is based on GaN current aperture vertical electron transistor (CAVET) [11], and two oxide layers are formed on left and sides of the device as shown in FIG. 1. The negative fixed charge exists at the oxide/GaN interface and its density is equal to the total charge dose in the buffer layer. The thickness of Al0.23Ga0.77N barrier, GaN channel, and n-GaN buffer
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are 15 nm, 25 nm, and 20 µm, respectively. And the doping concentration of n-GaN buffer and n+-GaN substrate layer are 2×1016 cm-3 and 5×1017 cm-3, respectively. What’s more, a 110-nm-thick p-type GaN layer with hole concentration of 5×1017 cm-3 is placed under the gate electrode to realize a normally-off design [14]. Moreover, the p-type current blocking layers (p-CBL) are connected
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to the source, and related structure-specific parameters are listed in TABLE I.
FIG. 1. Schematic illustration of the proposed GaN ICE-VFET. The negative fixed interfacial charge (No) is set to the oxide/GaN interface.
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TABLE I. Structure-specific parameters of GaN ICE-VFET
Symbol NBuf NCBL No LG LGS LCBL LAP Lo TCBL TBuf
Values 2×1016 cm-3 3.5×1017 cm-3 6×1012 cm-2 4 µm 0.5 µm 2 µm 2 µm 1 µm 0.5 µm 20 µm
Parameter Captions Buffer doping concentration P-CBL doping concentration Negative fixed charge density Gate length Gate-source distance p-CBL length Current aperture length Oxide trench length p-CBL thickness Buffer layer thickness
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ACCEPTED MANUSCRIPT 2.1. Negative charge at Oxide/GaN interface It has been proved that there are negative fixed charges with a high density (~1013 cm–2) at the Al2O3/(Al)GaN interface, and researchers have tried to use them for normally-off device [14,15]. The negative fixed charges are not totally caused by the polarization effect of GaN, because the high-density fixed charges can be observed at Al2O3/(SiO2 or Si) interface as well [16,17]. Dutta et al. speculated that the negative charge may be derived from the oxygen interstitials in their research [18].
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The experimental data reported by Tapajna indicated that the negative oxide charge almost completely located at the oxide/GaN interface [19]. Meanwhile, the Al2O3 film deposited by atomic layer deposition (ALD) showed relatively low electronic state densities (~1011 cm–2eV-1) in the Al2O3/n-GaN system [20,21]. Indeed the interface state density has a small dependence on the thickness of Al2O3, and thicker Al2O3 film shows lower interface states density [22]. It is assumed that the bulk oxide charges and
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built-up negative charges can be neglected and all the negative charges are formed at the oxide/GaN interface in this work.
(a) Al2O3/n-GaN
(b) Al2O3/p-GaN
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FIG. 2. Representation of the (a) Al2O3/n-GaN and (b) Al2O3/p-GaN and their band bending under influence of negative fixed interfacial charge.
2.2. Influence of interfacial charge on GaN
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Firstly, the influence of interfacial charges on GaN is discussed. The schematic structure of the Al2O3/n-GaN and Al2O3/p-GaN is shown in FIG. 2. In the Si-based MOSFETs, the charges at gate oxide/Si interface have been deeply investigated, and the results indicate that the charges could seriously influence the band bending of Si and make the threshold voltage uncontrollable [16]. Similarly, the negative fixed interfacial charges give rise to band bending of GaN as shown in FIG. 2. The n-GaN would be inverted when the fixed charge density QSS is higher than Qinv as shown in equation (1).
Qinv = q ⋅ N d ⋅ xd = 2qε sε 0 N d Φ s
(1)
where q is the elementary charge; Nd is the n-GaN doping density; xd is the width of space charge region; εs, ε0 are the permittivity of vacuum and the GaN’s relative permittivity, respectively; and ΦS is the built-in potential needed for strong inversion, which can be calculated from:
Φ s = 2Φ Fn = 2 ⋅
kT N d ln q ni 3
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ACCEPTED MANUSCRIPT Based on the calculations, Qinv is about 7.2×1011 q/cm2 at Nd =2×1016 cm-3. Under the influence of negative charges, the increased majority carrier density leads to accumulation condition for p-type GaN, whereas the n-GaN surface is inverted and a hole layer with high-density is induced below this surface. For the inversion condition, the hole density reaches up to ~1018 cm-3 near the n-GaN interface, and the hole and electron density are recovered as far away from the interface.
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2.3. GaN ICE-VFET Conventional CAVET can be improved by using an oxide layer locating at the buffer sides, such as SiO2 or Al2O3, which can introduce negative fixed charges at their interfaces with GaN. This interfacial charge engineering vertical FET can be named as GaN ICE-VFET.
Due to the influence of fixed negative interfacial charges (~1013 cm–2), the n-type GaN buffer side surface is inverted along the oxide/GaN interface, inducing a high-density hole inversion layer (p+-hole inversion pillar). When a negative drain voltage is
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applied on GaN ICE-VFET, the p+-hole inversion pillar laterally depletes the n-buffer pillar. Thus the whole buffer works as a superjunction-like p+n consisting of the p+-hole inversion pillar and n-pillar buffer pillar. Though the interface fixed charge is
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2-dimensional, the boundary conditions of Poisson equation for ICE-VFET could be considered as the limiting case of SJ-VFET. When the negative drain bias increases, more holes will be depleted and the depletion region in n-GaN pillar expands. Under the bias of breakdown voltage, the induced ICE-holes are exhausted; and the electric field line terminates at the negative interfacial charges in ICE-VFET, and the E-field distribution becomes more uniform and thus a much higher BV is obtained. In the proposed structure, the Al2O3 pillars work as oxide field plates and supplies the interfacial negative charges. When the total charges in n-GaN buffer are equal to the negative fixed charges, the charge balance could be realized and the BV could reach the highest value.
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3. Simulation models and process issues
In this work, the characteristics of GaN ICE-VFET are studied with Sentaurus device simulation, and a realizable process is also introduced.
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3.1. Simulation models
The simulation is based on TCAD methodology [23], and the doping-dependence and high-field-saturation models for mobility are included. The SRH and van Overstraeten–de Man avalanche models are used for recombination. And the 2DEG density at
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AlGaN/GaN interface is automatically calculated by polarization models. Though the charge trapping and de-trapping dominate the terminal current at high voltage below breakdown, the experimental trapping profiles and concentrations are not precisely known. However, the maximum voltage for a semiconductor device is limited by the avalanche breakdown induced by impact ionization process. Using the Chynoweth’s equation: = /
(3)
′
′
′
= () ( ( ) ( ))
(4)
The impact ionization coefficients for electrons (αn) and holes (αp) in GaN have been successfully measured by using a pulsed electron beam technique [24]. From the measured data for electrons and holes in GaN at room temperature: αn =1.5 × 105 cm−1 and bn = 1.41 × 107 Vcm−1; αp = 6.4 × 105 cm−1 and bp = 1.46 × 107 Vcm−1. The breakdown voltage is defined as the voltage when impact ionization integral reaches 1. The other parameters in this model are from standard package proposed by Synopsys Inc. [25] 4
ACCEPTED MANUSCRIPT 3.2. Process issues Al2O3 shows good thermal and electrical properties for power electronic applications and it is a leading candidate for realizing the proposed device. Several deposition techniques, such as thermal and plasma enhanced atomic layer deposition (T-ALD and PE-ALD) have been extensively studied in GaN MISHEMTs. The challenge in device fabrication would be how to control the fixed charges at Al2O3/GaN interface. Recently, lots of works about controlling the interface charge density in GaN MISHEMTs have been reported by Hahn et al.[14] Besides, Buckley et al. indicated that when the deposition temperature varies from 150°C to
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350°C the negative fixed charge at the Al2O3/SiO2 interface increases almost linearly from 2×1012 to 8×1012 cm-2.[17] Their achievements inspire us to realize the control of charge density by using a suitable growth temperature with good etching method and pre-treatment for deposition.
Although Al2O3 is well suited to the proposed device, other compatible oxides can also be used. Since not all oxides are capable of generating oxide/GaN interface charges, fluorine plasma treatment is a straightforward way to supply negative charges, and it
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has been successfully used to implant the negative ions into gate oxide [26]. Similar technological process could be utilized in the proposed device and the negative charge density could be controlled more precisely with this process. The GaN ICE-VFET could be realized by utilizing methods mentioned in references [8,27]. Firstly, the n-GaN buffer, p-CBL
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layer, GaN channel and Al0.23Ga0.77N barrier are deposited and regrown with the method in reference [8], and then ohmic contact is completed. Secondly, a deep trench is etched by deep reactive ion etching. Thirdly, surface preparation before oxide deposition is done for controlling the fixed charges. Then, oxide layers are deposited in the trench by ALD [27], and the interface charges will be adjusted by controlling the process conditions. Finally, electrode metals and passivation are deposited. 4. Results and discussion
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4.1. Device characteristics
FIG. 3 shows the equipotential contours in conventional CAVET and ICE-VFET. The CAVET owns same parameters in Table I except the oxide layer. Its BV and Ron are 1148 V and 1.42 mΩ·cm2, respectively. As shown in FIG. 3, the buffer layer of the conventional device is incompletely depleted and the depletion depth is about 8 µm. Well due to the vertical hole layer induced by
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negative charges, the buffer layer is completely depleted in ICE-VFET.
FIG. 3. Simulated equi-potential contours for the CAVET and ICE-VFET with Al2O3 layer at breakdown, the detail parameters are listed in TABLE I.
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ACCEPTED MANUSCRIPT FIG. 4 shows the E-field distributions at x=3 µm, the critical E-field for bulk GaN has been suggested as 3.75 MV/cm in reported results [28, 29]. Since the buffer thickness is more than the depletion width, the depletion of n-buffer is mainly expanded laterally rather than vertically, so that an increase in depletion charge reduces the inversion hole, and the E-field in buffer becomes
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well-distribution as shown in FIG. 4. As a result, the BV of the ICE-VFET increases by 262% compared with the CAVET.
FIG. 4. E-field distributions at x=3 µm in CAVET and ICE-VFET at charge balance.
4.2. Charge imbalance
Similar to SJ-FET, the charge imbalance between the interfacial charges and ionized buffer impurities is concerned in the
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proposed device as well. FIG. 5 shows BV of ICE-VFET varies with the negative fixed interfacial charge density. BV firstly
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increases with the increase of interfacial charge density (No), then it falls as the No larger than 5.5×1012 cm-2.
FIG. 5. Breakdown voltage varies with the negative fixed interfacial charge density of ICE-VFET.
The amount of the fixed negative charges and ionized buffer impurities are named as Qo and Qn respectively, and the relationship between their imbalance and BV is studied and shown in FIG. 6. When Qo Qn, there is a lot of surplus holes even if the buffer layer is completely depleted, and there is an E-field peak at the bottom corner of oxide, consequently the BV is limited as well. When Qo = Qn, the buffer layer can be totally depleted and BV reach highest value. 6
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FIG. 6. Vertical E-field distribution as a function of charge imbalance
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4.3. Optimization of Ron
The proposed device can obtain an even lower Ron than conventional CAVET by simultaneously increasing the negative charge density and buffer doping concentration. However, the increase of buffer doping density raises the horizontal electric field strength
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and then the breakdown voltage is decreased, therefore the buffer doping density should be set in a reasonable level. FIG. 7 shows how BV and Ron both decrease with the increase of the doping concentration of the buffer. With the increase of buffer doping dose, it becomes more difficult for p+-hole pillar to deplete the n-GaN buffer and the horizontal electric field strength raises drastically, therefore the device breakdown at a relatively lower BV. When doping concentration of the buffer (Nbuf) is set as 2×1016 cm-3, the FOM of ICE-VFET (with buffer thickness of 20 µm) get the highest value, and the device possesses high BV and
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low Ron at the same time (BV=4153 V and Ron=1.89 mΩ•cm2).
FIG. 7. BV and Ron as functions of buffer doping concentration. Ron is achieved at Vds=2 V and Vgs=2 V.
Owing to the electric lines flux through both the semiconductor and oxide pillars, the whole system (semiconductor and the oxide) behaves like semiconductor with an effective dielectric constant k (keff). If the oxide is HK (e.g. kO > kS), then kO > keff > kS. Considering the Poisson equation below, it can be seen that high kO (keff is high as well) allows for keeping a high Neff (effect doping concentration for the system), leading to a reduced Ron for the ICE-VFET with HK oxide.
=−
=−
!! "# $ !!
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However, E-field at oxide/GaN interface will be strongly influenced by the oxide permittivity, thus it needs to be discussed further. 7
ACCEPTED MANUSCRIPT 4.4. Optimization of the oxide permittivity In the ICE-VFET, there are two main limitations for BV. One is the avalanche of CBL/buffer junction; and the other is the peak E-field formed at the bottom corner of oxide. The above discussions are both based on the Al2O3, and some oxides with different permittivity densities will be analyzed furtherly in this section. We firstly assume the desirable low-K (LK) and high-K oxides (HK) own the same characteristics of Al2O3 except for the permittivity in the simulation.
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In the proposed structure, the n-pillar buffer is also depleted in the x direction by the MIS capacitor, which consists of the source (M) /oxide (I) /n-buffer (S). With the increasing kO the MIS capacitor (CMIS = kOε0/d) increase, which consequently raise the lateral depletion width in the n-pillars buffer.
Moreover, according to Gauss’s law, there is a large discontinuity of E-field at the interface of two different dielectrics due to the continuation of electric line flux. The E-field at the oxide side (Eo) and at the GaN side (Es) have a relationship as follow, (6)
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εoEo =εsEs
where εo and εs are the permittivity for oxide and GaN, respectively. This discontinuity will further enhance the E-field peak at the
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interface, and a larger permittivity difference between GaN and oxide makes the peak E-field even higher.
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FIG. 8. Breakdown voltage varies with the permittivity of oxide in ICE-VFET at different density of interface charge.
When charge balance was achieved at Qo=Qn, the buffer layer is fully depleted at breakdown, and BV decreases with the K value as shown in FIG. 8. The reason is that LK could effectively reduce the MIS capacitor, and then the lateral E-field strength would be
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reduced. Besides, the E-field peak at GaN/oxide could be depressed by utilizing the LK oxide according to equation (6), and a higher BV can be achieved.
When the charges of the interfacial charges and buffer doping dose are unbalanced, the buffer has not been fully depleted while the device has already broken down. The peak E-field at the bottom corner of oxide layer and the avalanche of CBL/buffer junction would limit the BV of the proposed device. The BV firstly increases with the increase of K until K=Kop, indicating that the effect of the expanding depletion width is dominating for the BV. Then BV decreases with the increase of K, indicating that the increased E-field strength peak is dominating for the BV. It can also be seen that Kop1 is larger than Kop2, where Kop1 and Kop2 stand for the optimal K value for BV for No = 10×1012cm-2 and 2×1012cm-2 respectively. Because when the Qo is less than Qn, the peak E-field at the bottom corner of oxide is not very high and allows for a larger K value to further deplete the buffer layer by the MIS capacitor, and thus a slightly larger K value of oxide is conducive to improve the breakdown voltage. 8
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FIG. 9. Optimal BV versus Ron for proposed ICE-VFET with different buffer doping concentrations. The ‘Sim.’ and ‘Exp.’ in this figure are the simulation results and experimental data of GaN-based vertical devices.
FIG. 9 shows the optimal BV versus Ron for ICE-VFET and reported GaN-based vertical devices including CAVET, JFET, and vertical MOSFET [30-37]. Compared with the simulation results and reported experimental data, the proposed ICE-VFET shows a
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good performance in BV and Ron, and the result has also exceeded the GaN 1D-limit. 5. Conclusion
A high-voltage GaN-based vertical FET with oxide/GaN interfacial charges is presented, and its breakdown mechanism has been investigated. By utilizing the interfacial charges, the proposed ICE-VFET device shows both high BV and low Ron simultaneously. Compared with a conventional GaN vertical FET with buffer thickness of 20 µm, BV is markedly increased from 1148 V to 4153 V. The high-performance GaN-based ICE-VFET has been optimized and its figure of merit even exceeds the GaN
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1-D limit. This design shows good prospects in future power electronic applications. Acknowledgments
The study was financially supported by the National Natural Science Foundation of China under projects No. 61376078 and and
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[30] N. Shrestha, Y. Li, E. Chang, Optimal design of the multiple-apertures-GaN-based vertical HEMTs with SiO2 current blocking layer, J. Comput. Electron. 15, 154–162 (2016).
[31] S. Kim, Y. Yoon, J. Kim, S. Cho, J. Lee, and I. Kang, Electrical Characteristics of Enhancement-Mode n-Channel Vertical GaN MOSFETs and the Effects of Sidewall Slope, J. Electr. Eng. Technol. 10(3), 1131-1137 (2015). [32] T. Oka, T. Ina, Y. Ueno, and J. Nishii, 1.8mΩ•cm2 vertical GaN-based trench metal oxide semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation, Applied Physics Express. 8, 054101 (2015).
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[33] T. Oka, Y. Ueno, T. Ina, K. Hasegawa, Vertical GaN-based trench metal oxide semiconductor field-effect transistors on a free-standing GaN substrate with blocking voltage of 1.6 kV, Applied Physics Express. 7,021002 (2014). [34] E. Kang, Y. Kim, Design of Trench Gate GaN Power MOSFET using Al2O3 Gate Oxide, Journal of Physics: Conference Series. 352, 012025 (2012).
[35] I. C. Kizilyalli and O. Aktas, Characterization of vertical GaN p–n diodes and junction field-effect transistors on bulk GaN
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down to cryogenic temperatures, Semicond. Sci. Technol. 30, 12400 (2015). [36] D. Ji and S. Chowdhury, Design of 1.2 kV Power Switches With Low RON Using GaN-Based Vertical JFET, IEEE Trans.
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Electron Devices. 62, 8 (2015).
[37] Q. Diduck, H.Nie, B. Alvarez, A. Edwards, D.Bour, O. Aktas, D. Disney, and I. C. Kizilyalli, 1000V Vertical JFET Using Bulk GaN, Ecs Transactions. 58 (4), 295-298 (2013).
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Highlights
A high voltage GaN ICE-VFET is proposed and its breakdown mechanism is presented. We have got all optimized structure parameters of the GaN ICE-VFET.
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The breakdown voltage and on-resistance are 4153 V and 1.89 mΩ•cm2, respectively.
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Its figure of merit even exceeds the GaN one-dimensional limit.
S0749-6036(17)31417-9
DOI:
10.1016/j.spmi.2017.07.018
Reference:
YSPMI 5128
To appear in:
Superlattices and Microstructures
Received Date: 9 June 2017 Revised Date:
0749-6036 0749-6036
Accepted Date: 7 July 2017
Please cite this article as: J. Du, D. Liu, Y. Liu, Z. Bai, Z. Jiang, Y. Liu, Q. Yu, Study on high breakdown voltage GaN-based vertical field effect transistor with interfacial charge engineering for power applications, Superlattices and Microstructures (2017), doi: 10.1016/j.spmi.2017.07.018. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
ACCEPTED MANUSCRIPT
Study on High Breakdown Voltage GaN-based Vertical Field Effect Transistor with Interfacial Charge Engineering for Power Applications Jiangfeng Du,a) Dong Liu, Yong Liu, Zhiyuan Bai, Zhiguang Jiang, Yang Liu, and Qi Yu State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of
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China, Chengdu, 610054, P. R. China
ABSTRACT: A high voltage GaN-based vertical field effect transistor with interfacial charge engineering (GaN ICE-VFET) is proposed and its breakdown mechanism is presented. This vertical FET features oxide trenches which show a fixed negative charge at the oxide/GaN interface. In the off-state, firstly, the trench oxide layer acts as a field plate; secondly, the n-GaN buffer layer is
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inverted along the oxide/GaN interface and thus a vertical hole layer is formed, which acts as a virtual p-pillar and laterally depletes the n-buffer pillar. Both of them modulate electric field distribution in the device and significantly increase the breakdown voltage (BV). Compared with a conventional GaN vertical FET, the BV of GaN ICE-VFET is increased from 1148V to 4153V with the
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same buffer thickness of 20 µm. Furthermore, the proposed device achieves a great improvement in the tradeoff between BV and on-resistance; and its figure of merit even exceeds the GaN one-dimensional limit.
Keywords: GaN HFETs, Vertical, Heterostructure, Breakdown voltage, Power device 1. Introduction
Gallium nitride (GaN) have attracted a lot of interest for applications in high-power electronics which operate at high
temperatures and high frequencies. In the past decades, the advancements of technology make the application prospect of GaN
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lateral heterostructure field effect transistors (FETs) more and more realistic [1~3]. However, the vertical devices are more desirable than lateral ones because of the superior on-state resistance (Ron) [4~6]. Due to the lack of suitable substrates with acceptable defect density (<106 cm-3) and process complexities, there were challenges for GaN vertical field effect transistors (GaN-VFET) to show their high performance in power electronic fileds during the past years. To solve the substrate problems of GaN-VFETs, Nie et al. reported a result of a fabricated outstanding GaN-based vertical transistor in 2014 [7]. Then Ramya et al.
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reported another excellent GaN vertical transistor by utilizing selective area regrowth p-GaN layer in 2015 [8]. These results indicate that high performance homoepitaxial growth on GaN substrates has been realized, and the fabrication technology for GaN vertical transistor has become continuously mature.
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Although the fabrication problems have been solved for a certain extent, the reported values of BV for GaN -VFETs are still not so satisfactory. The reported highest average breakdown E-field (150 V/µm) is far below the GaN theoretical limit (340 V/µm) [9]. Indeed the BV of GaN-VFETs is determined by the depletion zone of reverse-biased p-GaN/n-buffer junction [6], and the buffer layers within GaN VFETs are almost not completely depleted, which is an obstacle for increasing the BV of GaN-VFETs. Besides, there is always a serious trade-off between BV and Ron for conventional GaN-VFETs. To achieve a higher BV without Ron-deterioration, many methods have been carried out. One method is the edge-termination technology which can avoid the premature breakdown; however it does not contribute to expanding the depletion width. Moreover, p-type buried layers and Superjunction structures have been introduced in the buffer layer of GaN-VFETs to achieve high breakdown voltages [9,10]. The p-type buried layers or Superjunction for GaN-VFETs are generally formed by implanting Mg into GaN buffer layers [11]. ___________ a)
Corresponding author: Jiangfeng Du. Electronic mail: [email protected]
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ACCEPTED MANUSCRIPT However there is still a big challenge to effectively activate Mg in a buried GaN buffer layer [4], therefore the both designs face the difficulty in forming p+-pillar or p+-buried layers. It has been proved that Al2O3 shows a fixed charge when contacted with AGaN or GaN which has been studied a lot as gate oxide in GaN MISHEMTs [12,13]. In this work, we propose a novel GaN-VFETs possessing high BV without Ron deterioration by utilizing negative fixed interface charges, and a realizable fabrication process is also introduced. In the proposed device, BV can reach as high as 4153V and the figure of merit (FOM) has
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even exceeded the GaN 1D-limit. 2. Device structure and physic model
The proposed structure is based on GaN current aperture vertical electron transistor (CAVET) [11], and two oxide layers are formed on left and sides of the device as shown in FIG. 1. The negative fixed charge exists at the oxide/GaN interface and its density is equal to the total charge dose in the buffer layer. The thickness of Al0.23Ga0.77N barrier, GaN channel, and n-GaN buffer
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are 15 nm, 25 nm, and 20 µm, respectively. And the doping concentration of n-GaN buffer and n+-GaN substrate layer are 2×1016 cm-3 and 5×1017 cm-3, respectively. What’s more, a 110-nm-thick p-type GaN layer with hole concentration of 5×1017 cm-3 is placed under the gate electrode to realize a normally-off design [14]. Moreover, the p-type current blocking layers (p-CBL) are connected
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to the source, and related structure-specific parameters are listed in TABLE I.
FIG. 1. Schematic illustration of the proposed GaN ICE-VFET. The negative fixed interfacial charge (No) is set to the oxide/GaN interface.
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TABLE I. Structure-specific parameters of GaN ICE-VFET
Symbol NBuf NCBL No LG LGS LCBL LAP Lo TCBL TBuf
Values 2×1016 cm-3 3.5×1017 cm-3 6×1012 cm-2 4 µm 0.5 µm 2 µm 2 µm 1 µm 0.5 µm 20 µm
Parameter Captions Buffer doping concentration P-CBL doping concentration Negative fixed charge density Gate length Gate-source distance p-CBL length Current aperture length Oxide trench length p-CBL thickness Buffer layer thickness
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ACCEPTED MANUSCRIPT 2.1. Negative charge at Oxide/GaN interface It has been proved that there are negative fixed charges with a high density (~1013 cm–2) at the Al2O3/(Al)GaN interface, and researchers have tried to use them for normally-off device [14,15]. The negative fixed charges are not totally caused by the polarization effect of GaN, because the high-density fixed charges can be observed at Al2O3/(SiO2 or Si) interface as well [16,17]. Dutta et al. speculated that the negative charge may be derived from the oxygen interstitials in their research [18].
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The experimental data reported by Tapajna indicated that the negative oxide charge almost completely located at the oxide/GaN interface [19]. Meanwhile, the Al2O3 film deposited by atomic layer deposition (ALD) showed relatively low electronic state densities (~1011 cm–2eV-1) in the Al2O3/n-GaN system [20,21]. Indeed the interface state density has a small dependence on the thickness of Al2O3, and thicker Al2O3 film shows lower interface states density [22]. It is assumed that the bulk oxide charges and
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built-up negative charges can be neglected and all the negative charges are formed at the oxide/GaN interface in this work.
(a) Al2O3/n-GaN
(b) Al2O3/p-GaN
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FIG. 2. Representation of the (a) Al2O3/n-GaN and (b) Al2O3/p-GaN and their band bending under influence of negative fixed interfacial charge.
2.2. Influence of interfacial charge on GaN
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Firstly, the influence of interfacial charges on GaN is discussed. The schematic structure of the Al2O3/n-GaN and Al2O3/p-GaN is shown in FIG. 2. In the Si-based MOSFETs, the charges at gate oxide/Si interface have been deeply investigated, and the results indicate that the charges could seriously influence the band bending of Si and make the threshold voltage uncontrollable [16]. Similarly, the negative fixed interfacial charges give rise to band bending of GaN as shown in FIG. 2. The n-GaN would be inverted when the fixed charge density QSS is higher than Qinv as shown in equation (1).
Qinv = q ⋅ N d ⋅ xd = 2qε sε 0 N d Φ s
(1)
where q is the elementary charge; Nd is the n-GaN doping density; xd is the width of space charge region; εs, ε0 are the permittivity of vacuum and the GaN’s relative permittivity, respectively; and ΦS is the built-in potential needed for strong inversion, which can be calculated from:
Φ s = 2Φ Fn = 2 ⋅
kT N d ln q ni 3
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ACCEPTED MANUSCRIPT Based on the calculations, Qinv is about 7.2×1011 q/cm2 at Nd =2×1016 cm-3. Under the influence of negative charges, the increased majority carrier density leads to accumulation condition for p-type GaN, whereas the n-GaN surface is inverted and a hole layer with high-density is induced below this surface. For the inversion condition, the hole density reaches up to ~1018 cm-3 near the n-GaN interface, and the hole and electron density are recovered as far away from the interface.
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2.3. GaN ICE-VFET Conventional CAVET can be improved by using an oxide layer locating at the buffer sides, such as SiO2 or Al2O3, which can introduce negative fixed charges at their interfaces with GaN. This interfacial charge engineering vertical FET can be named as GaN ICE-VFET.
Due to the influence of fixed negative interfacial charges (~1013 cm–2), the n-type GaN buffer side surface is inverted along the oxide/GaN interface, inducing a high-density hole inversion layer (p+-hole inversion pillar). When a negative drain voltage is
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applied on GaN ICE-VFET, the p+-hole inversion pillar laterally depletes the n-buffer pillar. Thus the whole buffer works as a superjunction-like p+n consisting of the p+-hole inversion pillar and n-pillar buffer pillar. Though the interface fixed charge is
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2-dimensional, the boundary conditions of Poisson equation for ICE-VFET could be considered as the limiting case of SJ-VFET. When the negative drain bias increases, more holes will be depleted and the depletion region in n-GaN pillar expands. Under the bias of breakdown voltage, the induced ICE-holes are exhausted; and the electric field line terminates at the negative interfacial charges in ICE-VFET, and the E-field distribution becomes more uniform and thus a much higher BV is obtained. In the proposed structure, the Al2O3 pillars work as oxide field plates and supplies the interfacial negative charges. When the total charges in n-GaN buffer are equal to the negative fixed charges, the charge balance could be realized and the BV could reach the highest value.
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3. Simulation models and process issues
In this work, the characteristics of GaN ICE-VFET are studied with Sentaurus device simulation, and a realizable process is also introduced.
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3.1. Simulation models
The simulation is based on TCAD methodology [23], and the doping-dependence and high-field-saturation models for mobility are included. The SRH and van Overstraeten–de Man avalanche models are used for recombination. And the 2DEG density at
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AlGaN/GaN interface is automatically calculated by polarization models. Though the charge trapping and de-trapping dominate the terminal current at high voltage below breakdown, the experimental trapping profiles and concentrations are not precisely known. However, the maximum voltage for a semiconductor device is limited by the avalanche breakdown induced by impact ionization process. Using the Chynoweth’s equation: = /
(3)
′
′
′
= () ( ( ) ( ))
(4)
The impact ionization coefficients for electrons (αn) and holes (αp) in GaN have been successfully measured by using a pulsed electron beam technique [24]. From the measured data for electrons and holes in GaN at room temperature: αn =1.5 × 105 cm−1 and bn = 1.41 × 107 Vcm−1; αp = 6.4 × 105 cm−1 and bp = 1.46 × 107 Vcm−1. The breakdown voltage is defined as the voltage when impact ionization integral reaches 1. The other parameters in this model are from standard package proposed by Synopsys Inc. [25] 4
ACCEPTED MANUSCRIPT 3.2. Process issues Al2O3 shows good thermal and electrical properties for power electronic applications and it is a leading candidate for realizing the proposed device. Several deposition techniques, such as thermal and plasma enhanced atomic layer deposition (T-ALD and PE-ALD) have been extensively studied in GaN MISHEMTs. The challenge in device fabrication would be how to control the fixed charges at Al2O3/GaN interface. Recently, lots of works about controlling the interface charge density in GaN MISHEMTs have been reported by Hahn et al.[14] Besides, Buckley et al. indicated that when the deposition temperature varies from 150°C to
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350°C the negative fixed charge at the Al2O3/SiO2 interface increases almost linearly from 2×1012 to 8×1012 cm-2.[17] Their achievements inspire us to realize the control of charge density by using a suitable growth temperature with good etching method and pre-treatment for deposition.
Although Al2O3 is well suited to the proposed device, other compatible oxides can also be used. Since not all oxides are capable of generating oxide/GaN interface charges, fluorine plasma treatment is a straightforward way to supply negative charges, and it
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has been successfully used to implant the negative ions into gate oxide [26]. Similar technological process could be utilized in the proposed device and the negative charge density could be controlled more precisely with this process. The GaN ICE-VFET could be realized by utilizing methods mentioned in references [8,27]. Firstly, the n-GaN buffer, p-CBL
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layer, GaN channel and Al0.23Ga0.77N barrier are deposited and regrown with the method in reference [8], and then ohmic contact is completed. Secondly, a deep trench is etched by deep reactive ion etching. Thirdly, surface preparation before oxide deposition is done for controlling the fixed charges. Then, oxide layers are deposited in the trench by ALD [27], and the interface charges will be adjusted by controlling the process conditions. Finally, electrode metals and passivation are deposited. 4. Results and discussion
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4.1. Device characteristics
FIG. 3 shows the equipotential contours in conventional CAVET and ICE-VFET. The CAVET owns same parameters in Table I except the oxide layer. Its BV and Ron are 1148 V and 1.42 mΩ·cm2, respectively. As shown in FIG. 3, the buffer layer of the conventional device is incompletely depleted and the depletion depth is about 8 µm. Well due to the vertical hole layer induced by
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negative charges, the buffer layer is completely depleted in ICE-VFET.
FIG. 3. Simulated equi-potential contours for the CAVET and ICE-VFET with Al2O3 layer at breakdown, the detail parameters are listed in TABLE I.
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well-distribution as shown in FIG. 4. As a result, the BV of the ICE-VFET increases by 262% compared with the CAVET.
FIG. 4. E-field distributions at x=3 µm in CAVET and ICE-VFET at charge balance.
4.2. Charge imbalance
Similar to SJ-FET, the charge imbalance between the interfacial charges and ionized buffer impurities is concerned in the
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proposed device as well. FIG. 5 shows BV of ICE-VFET varies with the negative fixed interfacial charge density. BV firstly
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increases with the increase of interfacial charge density (No), then it falls as the No larger than 5.5×1012 cm-2.
FIG. 5. Breakdown voltage varies with the negative fixed interfacial charge density of ICE-VFET.
The amount of the fixed negative charges and ionized buffer impurities are named as Qo and Qn respectively, and the relationship between their imbalance and BV is studied and shown in FIG. 6. When Qo
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FIG. 6. Vertical E-field distribution as a function of charge imbalance
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4.3. Optimization of Ron
The proposed device can obtain an even lower Ron than conventional CAVET by simultaneously increasing the negative charge density and buffer doping concentration. However, the increase of buffer doping density raises the horizontal electric field strength
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and then the breakdown voltage is decreased, therefore the buffer doping density should be set in a reasonable level. FIG. 7 shows how BV and Ron both decrease with the increase of the doping concentration of the buffer. With the increase of buffer doping dose, it becomes more difficult for p+-hole pillar to deplete the n-GaN buffer and the horizontal electric field strength raises drastically, therefore the device breakdown at a relatively lower BV. When doping concentration of the buffer (Nbuf) is set as 2×1016 cm-3, the FOM of ICE-VFET (with buffer thickness of 20 µm) get the highest value, and the device possesses high BV and
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low Ron at the same time (BV=4153 V and Ron=1.89 mΩ•cm2).
FIG. 7. BV and Ron as functions of buffer doping concentration. Ron is achieved at Vds=2 V and Vgs=2 V.
Owing to the electric lines flux through both the semiconductor and oxide pillars, the whole system (semiconductor and the oxide) behaves like semiconductor with an effective dielectric constant k (keff). If the oxide is HK (e.g. kO > kS), then kO > keff > kS. Considering the Poisson equation below, it can be seen that high kO (keff is high as well) allows for keeping a high Neff (effect doping concentration for the system), leading to a reduced Ron for the ICE-VFET with HK oxide.
=−
=−
!! "# $ !!
(5)
However, E-field at oxide/GaN interface will be strongly influenced by the oxide permittivity, thus it needs to be discussed further. 7
ACCEPTED MANUSCRIPT 4.4. Optimization of the oxide permittivity In the ICE-VFET, there are two main limitations for BV. One is the avalanche of CBL/buffer junction; and the other is the peak E-field formed at the bottom corner of oxide. The above discussions are both based on the Al2O3, and some oxides with different permittivity densities will be analyzed furtherly in this section. We firstly assume the desirable low-K (LK) and high-K oxides (HK) own the same characteristics of Al2O3 except for the permittivity in the simulation.
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In the proposed structure, the n-pillar buffer is also depleted in the x direction by the MIS capacitor, which consists of the source (M) /oxide (I) /n-buffer (S). With the increasing kO the MIS capacitor (CMIS = kOε0/d) increase, which consequently raise the lateral depletion width in the n-pillars buffer.
Moreover, according to Gauss’s law, there is a large discontinuity of E-field at the interface of two different dielectrics due to the continuation of electric line flux. The E-field at the oxide side (Eo) and at the GaN side (Es) have a relationship as follow, (6)
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εoEo =εsEs
where εo and εs are the permittivity for oxide and GaN, respectively. This discontinuity will further enhance the E-field peak at the
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interface, and a larger permittivity difference between GaN and oxide makes the peak E-field even higher.
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FIG. 8. Breakdown voltage varies with the permittivity of oxide in ICE-VFET at different density of interface charge.
When charge balance was achieved at Qo=Qn, the buffer layer is fully depleted at breakdown, and BV decreases with the K value as shown in FIG. 8. The reason is that LK could effectively reduce the MIS capacitor, and then the lateral E-field strength would be
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reduced. Besides, the E-field peak at GaN/oxide could be depressed by utilizing the LK oxide according to equation (6), and a higher BV can be achieved.
When the charges of the interfacial charges and buffer doping dose are unbalanced, the buffer has not been fully depleted while the device has already broken down. The peak E-field at the bottom corner of oxide layer and the avalanche of CBL/buffer junction would limit the BV of the proposed device. The BV firstly increases with the increase of K until K=Kop, indicating that the effect of the expanding depletion width is dominating for the BV. Then BV decreases with the increase of K, indicating that the increased E-field strength peak is dominating for the BV. It can also be seen that Kop1 is larger than Kop2, where Kop1 and Kop2 stand for the optimal K value for BV for No = 10×1012cm-2 and 2×1012cm-2 respectively. Because when the Qo is less than Qn, the peak E-field at the bottom corner of oxide is not very high and allows for a larger K value to further deplete the buffer layer by the MIS capacitor, and thus a slightly larger K value of oxide is conducive to improve the breakdown voltage. 8
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FIG. 9. Optimal BV versus Ron for proposed ICE-VFET with different buffer doping concentrations. The ‘Sim.’ and ‘Exp.’ in this figure are the simulation results and experimental data of GaN-based vertical devices.
FIG. 9 shows the optimal BV versus Ron for ICE-VFET and reported GaN-based vertical devices including CAVET, JFET, and vertical MOSFET [30-37]. Compared with the simulation results and reported experimental data, the proposed ICE-VFET shows a
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good performance in BV and Ron, and the result has also exceeded the GaN 1D-limit. 5. Conclusion
A high-voltage GaN-based vertical FET with oxide/GaN interfacial charges is presented, and its breakdown mechanism has been investigated. By utilizing the interfacial charges, the proposed ICE-VFET device shows both high BV and low Ron simultaneously. Compared with a conventional GaN vertical FET with buffer thickness of 20 µm, BV is markedly increased from 1148 V to 4153 V. The high-performance GaN-based ICE-VFET has been optimized and its figure of merit even exceeds the GaN
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1-D limit. This design shows good prospects in future power electronic applications. Acknowledgments
The study was financially supported by the National Natural Science Foundation of China under projects No. 61376078 and and
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Fluorinated Gate Stack, IEEE Electron Device Lett. 36, 4 (2015).
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Threshold Voltage AlGaN/GaN Power Metal-Insulator-Semiconductor High Electron Mobility Transistor Using Multilayer
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[33] T. Oka, Y. Ueno, T. Ina, K. Hasegawa, Vertical GaN-based trench metal oxide semiconductor field-effect transistors on a free-standing GaN substrate with blocking voltage of 1.6 kV, Applied Physics Express. 7,021002 (2014). [34] E. Kang, Y. Kim, Design of Trench Gate GaN Power MOSFET using Al2O3 Gate Oxide, Journal of Physics: Conference Series. 352, 012025 (2012).
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down to cryogenic temperatures, Semicond. Sci. Technol. 30, 12400 (2015). [36] D. Ji and S. Chowdhury, Design of 1.2 kV Power Switches With Low RON Using GaN-Based Vertical JFET, IEEE Trans.
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Electron Devices. 62, 8 (2015).
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ACCEPTED MANUSCRIPT
Highlights
A high voltage GaN ICE-VFET is proposed and its breakdown mechanism is presented. We have got all optimized structure parameters of the GaN ICE-VFET.
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The breakdown voltage and on-resistance are 4153 V and 1.89 mΩ•cm2, respectively.
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Its figure of merit even exceeds the GaN one-dimensional limit.