Switched-resistor: A new family of sampled-data circuits

Int. J. Electron. Commun. (AEÜ) 63 (2009) 366 – 373 www.elsevier.de/aeue

Switched-resistor: A new family of sampled-data circuits Behnam Sedighi∗ , Mehrdad Sharif Bakhtiar Department of Electrical Engineering, Sharif University of Technology, Azadi Ave., Tehran 14588, Iran Received 13 September 2007; accepted 10 February 2008

Abstract This paper introduces “switched-resistor” circuits as a new family of current-mode sampled-data circuits with improved accuracy and linearity. Advantages of the switched-resistor circuits for high-speed and low-voltage applications are demonstrated. A switched-resistor biquad band-pass filter with a quality factor of 10 and clock frequency of 100 MHz, fabricated in a 0.18 m CMOS process, is also presented. The filter consumes 9 mW from 1.8 V supply. 䉷 2008 Elsevier GmbH. All rights reserved. Keywords: Sampled-data systems; Switched circuits; Current-mode circuits; Band-pass filters

1. Introduction In the past decades, switched-capacitor (SC) circuits have been the most popular solution for sampled-data systems. However, the reduced supply voltage of advanced CMOS technologies has imposed new challenges on the design of SC circuits especially for the high-speed applications [1] and new methods such as switched-opamp (SO) or clockboosting are introduced to overcome these challenges [1–4]. Switched-current (SI) circuits are a potential alternative to SC circuits for low-voltage applications due to lower voltage swing. They do not require high-density linear capacitors as well [5,6]. Unfortunately, accuracy of SI circuits depends on transistor matching. Furthermore, non-idealities such as charge injection of the switches result in higher distortion compared to SC circuits [5]. Dynamic range of SI circuits is also shown to be lower than SC circuits [6]. This paper presents a new family of current-mode sampled-data circuits referred to as switched-resistor (see appendix for a discussion about terminology) [7]. Accuracy of the switched-resistor (SR) circuits depends on resistor ∗ Corresponding author. Tel.: +98 21 6616 4370; fax: +98 21 6602 3261.

E-mail addresses: [email protected] (B. Sedighi), [email protected] (M.S. Bakhtiar). 1434-8411/$ - see front matter 䉷 2008 Elsevier GmbH. All rights reserved. doi:10.1016/j.aeue.2008.02.007

matching which is better than that of transistors. Since the V /I relation is linear, distortion is reduced compared with conventional SI circuits. In SR circuits, all switches are connected to a constant voltage. Hence, charge injection of the switches is signal independent and clock bootstrapping is not required. Moreover, SR circuits do not require accurate capacitors. Capacitive loading of the operational amplifiers is low, facilitating the design of high-speed circuits. Although SR circuits bear some resemblance with activeRC circuits (both use opamps, resistors and capacitors), the transfer function of a SR circuit depends only on resistor ratios. In contrast, transfer function of the active-RC circuits depends on the absolute value of the resistors and capacitors. For instance, frequency response of a SR filter is accurate without tuning while an active-RC filter requires tuning to compensate for the variations in fabrication process. The idea of using resistors in sample-and-hold (S/H) circuits has been proposed in [8,9]. Our work not only presents a different approach for the realization of a S/H, but also presents a new family of circuits that can be used in a variety of applications such as filtering, analog-to-digital conversion, etc. This paper is structured as follows. In Section 2, we introduce basic circuits for SR signal processing. In Section 3, properties of SR circuits regarding accuracy and speed are

B. Sedighi, M.S. Bakhtiar / Int. J. Electron. Commun. (AEÜ) 63 (2009) 366 – 373

investigated. In Section 4, a second-order band-pass SR filter is presented. Finally, conclusions are drawn in Section 5.

367

S3

Dummy (always On)

R1

φ2

Next stage

S0 S1

2. Switched-resistor circuits lin

φ1

CH

S2

R2 S4

φ1e

φ2

VREF

2.1. Switched-resistor S/H

lout φ2e VREF

We start this section with a conventional SI S/H shown in Fig. 1 (usually referred to as the second generation SI S/H) [10]. During the first clock phase, 1 , transistor M1 is connected as an MOS diode and input current is sampled. In the succeeding clock phase, 2 , switch S1 turns off and the gate-source voltage of M1 is kept unchanged. Therefore, M1 continues to draw the same amount of current if connected to a proper load (usually another diode connected transistor). A primary source of error in the SI S/H is the charge injected by switch S1. Charge injection issue is difficult to handle in SI circuits because of the nonlinear V /I characteristic of transistors [5]. Returning to Fig. 1, if the charge injected by S1 generates a small deviation in the gate-source voltage ( VGS ), the output current will have an error equal to VGS gm , where gm is the transconductance of M1. Both VGS and gm are signal-dependent. For a high-accuracy S/H, however, a constant charge injection as well as a linear V/I relation is desired. The switched-resistor S/H, shown in Fig. 2, operates similar to the SI circuit of Fig. 1. In phase 1 , the input current is converted to voltage and sampled on the hold capacitor

Fig. 3. SR amplifier.

CH . At the end of 1 , the output voltage of the amplifier is Vo [n] = VREF − (R + Ron2 )Iin [n],

(1)

where Iin [n] is the nth sample of the input and Ron2 is the on-resistance of the switch S2. When switch S1 turns off, the output voltage of the amplifier will be held unchanged. In the next clock phase, 2 , S2 is open and resistor R is connected to the following stage through S3. The output node is kept at VREF and the output current is given by   1 VREF − Vo [n] Iout n + = Iin [n], (2) = 2 R + Ron3 where Ron2 is assumed to be equal to Ron3 (on resistance of S3) which means that S2 and S3 must be similar. As shown in Fig. 2, switch S1 turns off slightly before S2. Therefore, charge injection of S2 and S3 does not affect the accuracy of the sampled signal.

2.2. Switched-resistor amplifier VDD φ1 IB

φ2 lin

φ1

φ2

lout

S1 M1

φ1 CGS

VREF

S3 φ2

R

φ1

CH

φ1

S2 Iin S1

Iout =

R1 + Ron0 Iin , (R1 + Ron3 )(R2 + Ron4 )

(3)

where RonX is the on resistance of the switch SX. If switches S0 and S3 are similar and S4 is sized such that

Fig. 1. Conventional SI S/H.

Iout

Switched-resistor circuits can be utilized to construct accurate gain blocks as shown in Fig. 3. Operation of the circuit in the sampling phase (1 ) is similar to that of Fig. 2. In the hold phase, switches S1 and S2 are turned off and R1 and R2 are connected to the input of the next stage. The output signal is given by

φ2 φ1e

φ1e

Vo

Ron4 = (R2 /R1 )Ron3 then the gain of the amplifier (G) will be   Iout R1 G= . =− 1+ Iin R2

(4)

(5)

As it can be seen, accuracy of the gain depends on resistor matching.

φ2e

2.3. Switched-resistor integrator

VREF

Fig. 2. Proposed SR S/H and clocking scheme.

A switched-resistor integrator is shown in Fig. 4. Assuming the input Iin2 to be zero for the moment, in phase 1

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φ2

φ1

RF φ1e

R

R

CH1

φ1

lin2

lin1

S1

S2

φ1e

φ2e

VREF

VREF

CH

CH2

lin

R/ lout

VREF

VoPP VDD/2

0 ISH

VREF

Fig. 4. SR integrator.

the left-hand side S/H in Fig. 4 is sampling and the voltage across CH1 is VCH1 [n] = −R(Iin1 [n] + Iout [n]/),

(6)

where  is defined by the ratio of resistors as shown in Fig. 4. At the next phase, 2 , the voltage across CH2 is given by VCH2 [n + 1] = −VCH1 [n].

(7)

Using (6) and (7), output current is derived as Iout [n + 1] =

VCH2 [n + 1] = Iin1 [n] + Iout [n]. R/

(8)

The resulting transfer function in z-domain is Iout (z) =

 Iin1 (z). z−1

(9)

Similar procedure can be applied to the other input Iin2 . The complete transfer function of the circuit can be expressed as Iout (z) =

z−1  Iin1 (z) − Iin2 (z). −1 1−z 1 − z−1

(10)

Eq. (10) indicates that both delaying and delay-free lossless integrators can be realized by this circuit.

2.4. Very low-voltage SR circuits The minimum supply voltage of an SR circuit is either determined by the minimum supply voltage of the opamp or the minimum clock level to turn the switches on. Successful implementation of very low-voltage opamps has been reported [2,3]. In such low-voltage opamps, it is necessary to set the quiescent output voltage of the opamp close to half the supply voltage (VDD /2) in order to have the maximum possible voltage swing. In the SR circuit of Fig. 2, the input current is zero in quiescent condition. Consequently, the input nodes and output node of the opamp will have the same quiescent value (i.e. VREF ), mandating that VREF must be about VDD /2. In very low-voltage opamps, it is usually difficult to bias the input pair of the opamp at VDD /2 since for VDD < 2VTH (VTH is threshold voltage of transistors), neither N-type nor P-type input differential pair will function.

Fig. 5. Very low-voltage SR circuit shown in the sampling phase; opamp has a P-type input pair.

In such cases, the solution of Fig. 5 can be used. A similar method has been used in [9]. In this circuit, the input nodes of the opamp are biased at VREF which can be close to ground. Meanwhile, output is biased at RF ISH +VREF which can be set close to VDD /2 by proper selection of ISH . This method can be applied to all the aforementioned SR circuits. The drawback of this method is the increased thermal noise caused by the current source ISH [9]. In SR circuits, switches do not experience voltage swing (unlike the case of SC circuits) and even in the very lowvoltage circuit of Fig. 5, clock boosting is not required for the NMOS switches since VDD is higher than VREF by at least one threshold plus two overdrive voltages (for the input pair of the opamp to operate correctly). On the other hand, if, by any reason, we use N-type input pair for the opamp of Fig. 5, VREF must be close to VDD . Using NMOS switches in this case mandates using clock-boosting. Using PMOS switches would be another solution but with the increased on-resistance of the switches. Note that there is no need for clock-bootstrapping in SR circuits.

3. Properties of switched-resistor circuits 3.1. Precision Accuracy of a switched-resistor circuit is primarily determined by the ratio of resistors. This is an advantage of SR circuits compared with conventional SI circuits. As an example, for the CMOS technology used in this work, achieving 0.1% matching in SC, SR and SI implementations requires: • SC: two 400 fF MIM capacitors each having an area of 400 m2 . • SR: two non-silicided poly resistors each having an area of 200 m2 with 20 fF parasitic capacitance to substrate.

B. Sedighi, M.S. Bakhtiar / Int. J. Electron. Commun. (AEÜ) 63 (2009) 366 – 373

• SI: two transistors each having an area of 1000 m2 with about 5 pF gate-source capacitance. Although the best matching result provided in process design kit is 0.02% for capacitors and 0.05% for resistors, such an extreme matching of components is rarely required and SR circuits meet the requirements of many applications. As seen in the previous section, on-resistance of the switches also affects the accuracy of the SR circuits, though, only the ratio of the on-resistances is important. To prevent mismatch of the switches from degrading the accuracy, on-resistance of the switches must be selected sufficiently smaller than the resistors they are in series with. For instance, a lower Ron , compared to R in (1) and (2), reduces the effect of switch mismatch on the total precision of the circuit. An example will be provided in Section 4. As shown in the previous section, all switches within the circuits are connected to a constant voltage (VREF ). Thus, the charge injected by the switches is constant and results in a constant offset at the output. This offset can be diminished by differential operation. The finite low-frequency gain (ADC ) of the opamp causes both offset and gain-error. For the basic S/H circuit of Fig. 2, it can be shown that the output current is Iout [n] =

VREF ADC + Iin [n]. 1 + ADC 1 + ADC

(11)

The first term in the right-hand side of (11) is a constant offset and the second term is a gain-error equal to 1/ADC . A similar gain-error is also observed in the SC circuit [11]. In the SR circuit, due to resistive load, a single stage opamp may not be able to provide a sufficient DC gain. Hence, a two-stage opamp is required. For deep-submicron CMOS technologies, SC circuits are also designed with two-stage opamps because of the low supply voltage [1–4]. The difference between opamps in SR and SC circuits is the lower gain of the second stage of the opamp in case of the SR circuit. This can be solved by increasing the gain of the first stage using gain-boosting technique.

3.2. Speed The maximum clock frequency of an SR circuit is determined by the settling time of the output voltage of the opamp. We use the simplified circuit of Fig. 6 to determine the time constant for the output voltage of the opamp. We assume that the circuit is driven by another SR circuit and the opamp has a first-order frequency response. Transfer function of the circuit in Fig. 6 can then be found as Vo (s) Vi (s)

−RF /RS    =  , (Cin +CH )RF 1+RF /RS +s s2 +CH RF +1 u u (12)

369

RF

RS

CH

Vi Vo Cin Cout

Fig. 6. Model of an SR circuit in the sampling phase.

where u is the open loop unity-gain frequency of the opamp with a total load capacitance of CLtot = Cout +

Cin CH , Cin + CH

(13)

where Cin and Cout are the total parasitic capacitances at the input and output nodes of the opamp, respectively. The transfer function in (12) often has two widely apart poles. The time constant of the step response, which is determined by the smaller pole, can be approximated by SR ≈ RF CH +

1 + RF /RS . u

(14)

An availing property of SR circuits is that the load capacitance of the opamp, given by (13), is significantly smaller than that of a similar SC circuit. For instance, considering the parasitic capacitances at the input/output nodes of the opamp (Cin and Cout ) to be 0.2CH , the total load capacitance of the opamp will be 0.37CH . On the other hand, in the SC circuits, the load capacitance which includes the sampling capacitor of the subsequent stage is usually larger than the hold capacitor (see [1] for an example). Therefore, a certain u could be realized more easily in case of the SR circuit. The lower load capacitance makes SR circuits attractive for upcoming CMOS technologies with supply voltage below 1 V where the reduced voltage swing would compel to reduce the KT/C thermal noise by increasing the size of the capacitors in order to preserve signal-to-noise ratio.

3.3. Dynamic range Maximum dynamic range of an SR circuit is limited by the thermal and flicker noises generated by switches, resistors and opamps. For the SR amplifier shown in Fig. 3, the total noise referred to the output node of the amplifier is 2 vn2 ≈ KT /CH + [4KT (R1 R2 ) + vn,op ]BWn ,

(15)

2 where K is Boltzamann constant, T is temperature, vn,op is the input referred noise of the opamp and BWn is the noise bandwidth. With our interest in high-frequency applications, flicker noise is neglected. The first term in the right-hand side of (15) is the sampled noise of resistor R1 and switches

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in the sampling phase and the second term is the noise of the resistors and opamp in the hold mode. With similar bandwidth for all stages of a circuit, noise bandwidth can be calculated from (12) as BWn =

  1 1 = . f−3 dB ≈ 2 2 2SR 4SR

compare the performance of SR circuits to that of SC circuits in nominal supply voltage of a deep submicron CMOS technology. Therefore, a comparison is also provided in the last part of this section.

(16)

4.1. Structure of the filter

Signal-to-noise ratio (SNR) can be calculated as SNR = 10 log = 10 log

2 /8 IOpp in2 2 /8 IOpp vn2 /(R1 R2 )2

= 10 log

2 VOpp

8vn2

,

A second-order band-pass filter with a center frequency (fc ) of one-fifth the sampling frequency and a quality factor (Q) of 10 was designed. The block diagram of the biquad filter is depicted in Fig. 7(a). It can be shown that the transfer function of the filter is

(17)

H (z) =

where in2 is the output noise, IOpp is the peak-to-peak amplitude of the output current and VOpp is the peak-to-peak voltage swing at the output of the opamp. It must be added that SNR of an SR circuit could also be determined by calculation of equivalent output noise current instead of output noise voltage. However, the latter is preferred since it relates the dynamic range to the voltage swing at the output of the opamp, a design parameter determined by the supply voltage of the system.

Y (z) z−1 [e − cd + (bd − e)z−1 ] = . X(z) 1 − (2 − ac)z−1 + (1 − ab)z−2

(18)

The corresponding filter is shown in Fig. 7(b). For the sake of simplicity, single ended version of the circuit is shown though the actual circuit is fully differential. It must be noted that the transfer function of a band-pass biquad must have two zeros at z=±1. Since we were mostly interested in accuracy of fc and Q as a measure of the performance, the zero in z = 1 was not realized. As a result, the attenuation of the filter at low frequencies is limited to about 20 dB. The filter coefficients were realized by unit element during layout, and due to rounding of the coefficients, the final center frequency and Q of the filter are found to be 0.1994fCLK and 9.96, respectively. The value of R in Fig. 7(b) is 1.8 k. The effect of the on-resistance of switches is cancelled out by placing dummy transistors (M5, 6 and M11, 12) in

4. SR filter In this section, we present a prototype SR circuit. Apart from idea proofing, one aim of this prototyping has been to

e + X(z)

bz-1-c 1-z-1

az-1 1-z-1

d

+ Y(z)

(a) φ1

φ1

Rin

Vin

M1 VDD

M2 VDD

VDD R

R

CH

M5

M6

M3

M4

CH

φ1 CH

R2=R/b M7

A2

A1 VREF φ1e

φ1e

φ2e

φ2e V

M8 REF

VDD

R

R

R3=R/c

M11

M12

M9

M10

CH

A3

A4 VREF φ1e

φ1e φ2e

φ2 R4=RF /d

φ2e

R1=R/a VREF

Iout

R4=RF /e

(b) Fig. 7. (a) Block diagram of the filter; (b) SR realization of the filter.

R6=RF A5

VREF

Vout

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371

VDD VB4 M23 Vout+

M9

VB1

M16

M10

M7

VB2

M15

M8

VB3 CC

M13 Vin+

M1

M2

M14

VB4 M24 Vout-

VB3

Vin-

M5

M6

CC

M12

M11

M22

M21 M3

VCMFB

M4

Fig. 8. Operational amplifier.

series with the resistors. On-resistance of each switch is approximately 1/40 of the resistor it is in series with (e.g. 42 for M5, 6). Therefore, the impact of mismatch between onresistances (which is calculated to be 2% in the worst case) is negligible. The bias voltage (VREF ), which is set by the common-mode feedback circuit of the opamps in the fully differential implementation, is 0.5 V which results in a 1.3 V gate-to-source voltage for NMOS switches at 1.8 V supply voltage. This value is high enough to eliminate any need for clock-boosting. Input and output signals of the filter can be either current or voltage. For convenience, we selected voltage signaling. Input voltage is converted to current by resistor Rin as shown in Fig. 7(b). Output current is also converted to voltage using an additional operational amplifier (A5) which also drives the large PAD capacitance.

4.2. Operational amplifier A two-stage operational amplifier, shown in Fig. 8, was designed. The first stage of the opamp is a folded cascode amplifier and the second stage is a simple common source circuit. Compensation is performed using cascode Miller technique. The opamp is similar to what is used in [4] except for the gain-boosting that is utilized in the first stage (M11–14 in Fig. 8). Since the length of M9 and M10 was significantly larger than that of M3 and M4, it was not necessary to apply the gain-boosting to P-type current sources (M7–10). Increasing the length of M3 and M4 (while keeping W/L unchanged) would slow down the circuit since the parasitic drain capacitance of M3 and M4 contributed to the main non-dominant pole of the first stage. Specifications of the opamp are given in Table 1 .

4.3. Measurements The biquad filter was fabricated in 0.18 m CMOS process. Resistors were implemented using non-silicided

Table 1. Specifications of the opamp DC gain Unity-gain frequency Phase margin Power consumption

86 dB@RL = 1.8 k 640 MHz 68◦ 2.1 mW@VDD = 1.8 V

p-type polysilicon. Fig. 9(a) shows the frequency response of the filter at different clock frequencies. The pass-band gain of the filter (after considering a 12 dB attenuation caused by input/output matching circuitry on the PCB) is 4 dB. At 100 MHz clock, pass-band gain reduces to 3.4 dB. The measured fc /fCLK and Q are 0.1991 and 9.85, respectively. As clock rate approaches 100 MHz, Q increases because of the incomplete settling of the signals within the filter. As shown in Fig. 9(b), Q reaches to 11.2 at fCLK = 100 MHz. The output noise spectrum of the filter is shown in Fig. 10. Output noise is 0.81 mVrms which corresponds to 53 dB maximum SNR. Fig. 11 shows the chip photograph. Power consumption of the filter core is 9 mW. Specifications of the filter are summarized in Table 2.

4.4. Comparison In Table 3 , performance of the filter is compared with the band-pass SC filters. The traditional figure of merit (FOM) of “power/(pole ×fCLK )” is also presented in this table. The proposed filter demonstrates a low FOM. However, this comparison is not completely fair because power consumption of a filter is also a function of technology, SNR and quality factor. As it can be seen, there are other filters in Table 3 that provide higher SNR (although with higher supply voltage). In summary, we can conclude that the performance of SR is at least comparable with that of SC.

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Fig. 11. Chip photograph; the chip is realized on a multiproject die.

Table 2. Summary of performance Filter type Supply voltage Center frequency (fc ) Quality factor (Q) Max. clock frequency SNR@IM3 = 1% Power consumption Active chip area Technology

2nd order, band-pass 1.8 V 0.2fCLK 10 100 MHz 53 dB 9 [email protected] V supply 0.1 mm2 0.18 m

Table 3. Comparison Ref.

Fig. 9. (a) Measured response of the filter at fCLK = 50, 80 and 100 MHz; (b) pass-band of the filter at fCLK = 100 MHz.

[12]

[13]

[14]

[15]

This work

Filter type BPF BPF BPF BPF BPF Order 6 6 12 14 2 Tech. (m) 0.6 0.35 0.35 0.18 0.18 VDD (V) 3.3 3 3 1.8 1.8 fCLK (MHz) 43 64 112 88 100 fc (MHz) 10.7 10.7 28 44 20 Bandwidth (MHz) 0.2 0.4 3.8 6.2 2 Output noise (mVrms ) 0.23 – 2.53 3.08 0.81 Dynamic range (dB) 61 62 37 33 53 Total power (mW) 16 42 225 250 9 FOM (pW/Hz) 62 109 174 204 45

5. Conclusion

Fig. 10. Measured output noise at fCLK = 100 MHz.

Basic building blocks for switched-resistor signal processing have been introduced in this paper and properties of SR circuits regarding precision, speed and dynamic range have been studied. A high-speed, high Q, biquad filter has also been designed using SR circuits and the functionality of the circuit has been verified using an experimental 0.18 m CMOS test chip. It has been shown that the performance of SR can be comparable to that of SC. This together with the capability of operation in very low-voltage applications and the low capacitive load of the opamps, makes switched resistor a candidate for future sampled-data systems.

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Acknowledgment The authors would like to thank Mr. H. Movahedian for helpful discussions during layout and fabrication.

Appendix A A.1. About the terminology The term switched-resistor has been used in the literatures previously. In some papers switched-resistor simply implies a mechanism for switching resistors in order to have a digitally controllable resistor [16]. In the context of filter design, switched-resistor term was utilized in [17] where resistors of an active-RC filter, implemented by MOS transistors, were switched in/out of the filter for the sake of tuning. Recently a new method for tuning continuous-time filters was proposed and the resulting circuit was referred to as switchedR-MOSFET-C [18]. Although these circuits are completely different from the circuits in this paper, authors selected the term switched-resistor because of the sampled-data nature of the presented circuits and specially their correspondence with switched-capacitor and switched-current approaches.

References [1] Aloisi W, Giustolisi G, Palumbo G. Exploiting the highfrequency performance of low-voltage low-power sc filters. IEEE J Solid-State Circuits 2004;51:77–84. [2] Crols J, Steyaert M. Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages. IEEE J Solid-State Circuits 1994;29:936–42. [3] Keskin M, Moon UK, Temes GC. A 1-V 10-MHz clock rate 13-bit CMOS delta-sigma modulator using unity-gain-reset opamps. IEEE J Solid-State Circuits 2002;37:817–24. [4] Abo AM, Gray PR. A 1.5-V 10-bit, 14.3-ms/s CMOS pipeline analog-to-digital converter. IEEE J Solid-State Circuits 1999;34:599–606. [5] Balachandran GK, Allen PE. Switched-current circuits in digital CMOS technology with low charge-injection errors. IEEE J Solid-State Circuits 2002;37:1271–80. [6] Hughes JB, Worapishet A, Toumazou C. Switched-capacitors versus switched-currents: a theoretical comparison. In: Proceedings of IEEE international symposium on circuits and systems, ISCAS, 2000. p. 409–12.

373

[7] Sedighi B, Sharif-Bakhtiar M. A 1.5 V 60 ms/s sampled-data filter in 0.18 m CMOS. In: Proceedings of IEEE European conference on circuit theory and design, ECCTD, 2005. p. 95–8. [8] Ishikawa M, Tsukahara T. An 8-bit 50-MHz CMOS subranging ADC with pipelined wide-band S/H. IEEE J Solid-State Circuits 1998;23:1309–15. [9] Mortezapour S, Lee EKF. A 1-V, 8-bit successive approximation ADC in standard CMOS process. IEEE J Solid-State Circuits 2000;35:642–7. [10] Hughes JB, Macbeth IC, Pattulla DM. Second generation switched current signal processing. In: Proceedings of IEEE international symposium on circuits systems, ISCAS, 1990. p. 2805–8. [11] Razavi B. Design of analog CMOS integrated circuits. New York: McGraw-Hill; 2001. [12] Quinn PJ, Hartingsveldt KV, Van Roermund A. A 10.7 MHz CMOS SC radio if filter using orthogonal hardware modulation. IEEE J Solid-State Circuits 2000;35:1865–76. [13] Adut J, Silva-Martinez J, Rocha-Perez M. A 10.7-MHz sixthorder SC ladder filter in 035 m CMOS technology. IEEE Trans Circuits Syst I 2006;53:1625–35. [14] Ng KWH, Luong HC. A 28 MHz wideband switched capacitor bandpass filter with transmission zeros for high attenuation. IEEE J Solid-State Circuits 2005;40:785–90. [15] Zheng H, Luong HC. A 36/44 MHz switched-capacitor bandpass filter for cable-tv tuner application. In: Proceedings of IEEE Asian solid-state circuits conference, ASSCC, 2005. p. 235–8. [16] Hsu CC, Wu JT. A highly linear 125-MHz CMOS switchedresistor programmable-gain amplifier. IEEE J Solid-State Circuits 2003;38:1663–70. [17] Geiger R, Allen PE, Ngo DT. Switched-resistor filters – a continuous time approach to monolithic mos filter. IEEE Trans Circuits Syst 1982;29:306–15. [18] Kurahashi P, Hanumolu PK, Temes G, Moon UK. A 0.6 V highly linear switched-r-mosfet-c filter. In: Proceedings of IEEE custom integrated circuits conference CICC, 2006. p. 833–6. Behnam Sedighi received his B.S. and M.S. degrees from Sharif University of Technology, Tehran, Iran in 1999 and 2002, respectively. He is currently a Ph.D. candidate at Sharif University of Technology. Mehrdad Sharif Bakhtiar received his Ph.D. degree from the University of California, Los Angeles. He is an Associate Professor of electrical engineering at Sharif University of Technology.