Systematic evaluation of thermal interface materials—a case study in high power amplifier design

Microelectronics Reliability 45 (2005) 711–725 www.elsevier.com/locate/microrel

Systematic evaluation of thermal interface materials—a case study in high power amplifier design Luke Maguire 1, Masud Behnia *, Graham Morrison

2

School of Mechanical and Manufacturing Engineering, University of New South Wales, Sydney, New South Wales 2052, Australia Received 27 April 2004; received in revised form 7 September 2004 Available online 25 December 2004

Abstract A comprehensive study has been undertaken to better understand the thermal conditions within high power, radio frequency (r.f.) signal amplifiers. Here, the results of two aspects of this study are presented in detail. First, laboratory and field experiments were conducted to determine the junction temperatures of the main heat dissipating components in the amplifier circuit. With individual devices dissipating up to 130W each, under normal operating conditions, junction temperatures were shown to approach their maximum rating of 200
C when ambient temperatures reach 60
C. Under these conditions the interface thermal resistance between the components and the heat sink currently accounts for over 20% of the total temperature rise from the ambient air to the device junction. Experiments were subsequently conducted to determine the interface thermal resistance of a number of candidate materials allowing comparison of application specific data obtained here with the manufacturer published data. The experimental data from this study was also used to compare the performance of the current thermal grease compound with a range of commercially available alternatives. At maximum power dissipation, junction temperatures were reduced by up to 20
C through the use of a high conductivity thermal grease in conjunction with careful preparation of the contact surfaces to ensure consistent flatness.  2004 Elsevier Ltd. All rights reserved.

1. Introduction As CPU power densities continue to increase so does the level of interest in the performance of Thermal Interface Materials (TIMs) in minimising temperature drop across the heat sink/device interface. The current de* Corresponding author. Tel.: +61 2 9036 9518/9385 4253; fax: +61 2 9036 9519/9663 1222. E-mail addresses: [email protected] (L. Maguire), [email protected] (M. Behnia), g.morrison@ unsw.edu.au (G. Morrison). 1 Tel.: +61 2 9385 5127; fax: +61 2 9663 1222. 2 Tel.: +61 2 9385 4127; fax: +61 2 9663 1222.

mand for commercial packaging solutions which further reduce interface thermal resistance has been identified by both the International Technology Roadmap for Semiconductors [1] and National Electronics Manufacturing Initiative [2] as one of the key factors in the continuing push by the electronics industry for system miniaturisation and performance gains. A similar situation exists in high power amplifiers where junction temperatures of the main high power transistors must be maintained at or below 200
C [3] in order to maximise component reliability. In such an application the thermal resistance across the transistor/heat sink interface accounts for over 20% of the total temperature rise between the ambient air and the component temperature and therefore

0026-2714/$ - see front matter  2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.10.030

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represents a significant opportunity for device temperature reduction. Numerous researchers have identified the need to better understand the effects of parameters such as surface roughness, surface flatness and clamping pressure, on thermal interface resistance. Various studies have noted that as a result of surface irregularities, dry contact surfaces can have as little as between 1% and 5% actual contact [4,5]. The remaining area is separated by an insulating air gap (kair = 0.0242 W/m K) of varying thickness. Therefore, in order to reduce the thermal resistance across the interface, steps must be taken to either increase the amount of actual contact area (e.g. by increasing contact pressure or grinding and polishing of the surfaces to improve flatness and roughness values) or to fill the remaining air gaps with a suitable TIM. In [5], Nakayama and Bergles noted that a considerable amount of research has already been conducted on applications involving high contact pressures (above 500 kPa). In these instances, surface roughness and the ability of the TIM to fill the resulting microscopic interstices on each contact surface contributes heavily to total interface resistance. They also recommended that future work needs to concentrate more on low pressure interfaces (i.e. suitable for personal computing and micro-electronics) where irregularities in surface flatness (i.e. waviness, corrugation) begin to have a greater impact on interface resistance. Since it is often not possible to increase contact pressure without damaging components, and surface flatness tends to be dictated by the upstream manufacturing process, the use of a TIM is generally required in the final packaging of most micro-electronics applications. Blazej [6] and Gwinn and Webb [4] provide detailed reviews of the various types of TIM currently available including thermal greases and gels, elastomeric pads, thermal tapes, phase change materials, thermally conductive adhesives and soft metals. While thermal greases are sometimes considered to be messy or difficult to apply in reproducible quantities, they are often recommended by microprocessor manufacturers [4,6] with the best performing products having published values of interface resistance of around 0.2 K cm2/W and below. They typically also only require low contact pressure of around 300 kPa to achieve optimal performance [6]. Phase Change Materials (PCMs) overcome some of the drawbacks of greases in assembly processes as they can be supplied as pre-cut gaskets that are entirely solid at room temperature. Typical published performance data also compares well with greases (0.15–0.65 K cm2/W) with similar levels of contact pressure, making them seem an attractive alternative. However, one drawback is the adhesive nature of the PCM once it has completed its first reflow cycle (i.e. exceeded the melting temperature), which may cause damage to sensitive components during subsequent rework procedures.

Similarly, each of the other types of TIM listed above has advantages and disadvantages which must be assessed based on the requirements of the intended application. For example, elastomeric pads have relatively high thermal conductivities and can be supplied in pre-cut forms to simplify assembly processes but they typically require high contact pressures to optimise the interface. They also have a minimum thickness through which heat flow from the component to heat sink must pass, and they cannot easily flow in to fill microscopic interstices on the mating surfaces. As such they tend to be used in medium power applications where ease of assembly is required [6]. Thermal tapes provide similar thermal performance to elastomeric pads but are coated with pressure sensitive adhesive and provide significant packaging advantages where the use of bulky clamping equipment is not possible. In [4], Gwinn and Webb collected the published thermal data for a range of TIMs including thermal greases, PCMs and a thermal elastomer. Values of interface resistance, Rint, for all products ranged from 0.018 to 0.645 K cm2/W. However, comparison of products is made difficult since the contact pressure used during testing ranged from 21 to 345 kPa. Direct comparison of the relative performance of each TIM is further complicated by the fact that contact pressure data was not available for three of the thermal greases and the performance of the elastomeric pad was quoted in terms of bulk thermal conductivity as opposed to a total interface resistance. Thermal designers must also be cautious when using published thermal data for system design calculations since the total interface resistance is a strong function of not only the TIM properties but also of the mating surfaces [4]. The test apparatus used by TIM manufacturers generally conforms to the requirements of ASTM D5470 which describes a method of determining Rint, based on the temperature drop, DT, and heat flux, Q, across the interface between two copper blocks of cross sectional area, A. The TIM under test is sandwiched between the two blocks while one is heated and the other is cooled to provide a temperature drop across the TIM. Thermocouples placed within the two copper blocks are used to determine the temperature gradient within each block and hence the temperature of each contact surface. As such, the published value of Rint (=DT Æ A/ Q) is specific to the exact surface finish, surface flatness and loading conditions on the copper blocks in each individual test rig. However, TIMs are used in a wide range of applications involving various materials at each of the mating surfaces and various clamping techniques that do not generally match those of the TIM manufacturers test rig. Many researchers have recognised the deficiencies in the existing test method and have proposed improvements. Gwinn and Webb [4] proposed changes to better

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simulate computer CPU installation methods and surface materials. Lasance [7] identified both customer and vendor related problems with the current test methods based on ASTM D5470 and recommended a number of changes including the certification of in-house test equipment to standardised reference TIMs and the use of contact pressures that better reflect those experienced in the electronics industry. Shih and Bash [8] devised an automated system for testing thermal resistance of TIMs at various clamping pressures or TIM thickness. The automated process removed variation associated with continual operator involvement in the test process and allowed accurate back-to-back evaluation of TIMs without bias. Gektin et al. [9] proposed a similar application specific test apparatus and conducted experiments to determine the contributions of the bulk thermal resistance of the TIM and the interface contact resistance to the overall interface resistance. This study extends the existing work by developing a test method for evaluating total thermal interface resistance of various TIMs used in a high power, r.f. signal amplifier shown in Fig. 1. The main heat dissipating components on the printed circuit board (PCB) are mounted directly to an extruded aluminium heat sink situated in airflows of approximately 75 l/s. The amplifier provides up to 440 W of output power and contains four high power output transistors (Philips BLW96) each dissipating 130 W to the heat sink through a package footprint of 1.96 cm2 [10]. Due to the remote location of the transmitter sites in outback Australia, amplifiers operate in ambient air temperatures of up to 50
C with the pre-heated cooling air at the inlet to some heat sinks reaching 60
C. The operational junction temperature of the high power transistors, and the thermal resistance at the interface between the copper mounting flange of the devices and the aluminium heat sink are each investigated in detail here. Thermal interface resistance is evaluated when standard field assembly procedures are followed and also when careful preparation

Fig. 1. High power amplifier on extruded aluminium heat sink.

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of the mating surfaces is carried out to ensure consistent flatness and surface roughness. Comparisons are also made between the data obtained here and published values to assess the effects of application specific parameters such as clamping method and surface finish.

2. Junction temperature measurements 2.1. Experimental modeling under laboratory conditions A thermal map of the PCB on an operational amplifier running at maximum power, taken using an infrared camera (see Fig. 2), shows the highly localised nature of some of the heat sources (i.e. the four output transistors and the four blocks of resistors directly below them). Here the output transistors are mounted directly to the heat sink which accounts for over 98% of the heat removal from these devices. The remaining heat losses are via direct convection from the transistor ceramic case to the air flow over the top of the PCB and via conduction from the transistor solder tabs to the PCB. The resistors are much lower power devices and, as such, are not mounted directly on the heat sink. All heat from the resistors is therefore removed either via convection to the airflow over the PCB or via conduction to the PCB. Due to the varying surface emissivities of the components and PCB, reliable absolute component temperatures cannot be obtained from this initial infra red image. In order to more accurately determine junction temperature the temperature of the copper flange must be known. Using measured flange temperatures the junction temperatures can be calculated by using the manufacturer determined value for thermal resistance from the junction to the flange, Rth junct-fl, and the power dissipation from the transistor, Q. In line with this

Fig. 2. Infrared image of transistors and resistor on circuit board at full output power.

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methodology, laboratory experiments using a simplified d.c. circuit to power individual transistors were conducted to obtain an initial estimate of junction temperatures in the field. A dedicated wind tunnel and data acquisition system was designed and built to allow detailed thermal and airflow measurements to be made on a high power amplifier module (see Fig. 3). A 1.6 kW heater situated near the inlet allowed the ambient cooling air to be heated to simulate the range of climatic conditions in the field. A variable speed fan upstream of the heat sink provided up to 120 l/s airflow. The wind tunnel walls were constructed from Perspex, to facilitate flow visualisation at a later stage, and the duct area over the length of the test section was made 120 mm high · 220 mm wide to match the airflow space surrounding the amplifiers in the field. The bulk airflow through the system was measured using a conical inlet attached to the fan intake. Manufactured according to BS848:Part 1:1980, the conical inlet allowed measurement of the total mass flow rate via the following equation: qm ¼ ae

pd 2 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2  qu  Dp 4

ð1Þ

where qm equals mass flow rate [kg/s], a and e are the flow coefficient and expansibility factor respectively, d is the throat diameter of the conical inlet [m], qu equals the air density upstream of the inlet [kg/m3] and Dp is the atmospheric minus static pressure at the inlet [Pa]. In order to simplify the electrical circuit and allow greater control over the power dissipation levels in each transistor, a d.c. power supply circuit was built to take the place of the amplifier PCB. The use of a d.c. power supply also negated the effects of r.f. signal interference on the thermocouple readings which had been observed during preliminary testing of an operational amplifier

and will be discussed further in Section 2.2. The collector tabs on each transistor were connected in parallel to a supply of 36 V and the bases were connected to a 12 V supply. A variable resistor in each of the base circuits allowed the current to be adjusted independently for each transistor. The total power dissipated by each transistor was calculated by multiplying the current by the voltage drop. Logged values of voltage drop and current were calibrated against readings taken using a Fluke 867 multimeter. The maximum error in final power readings was estimated as ±5%. The data acquisition system for this phase of laboratory experiments was comprised of nine (9) K-type thermocouples, a voltage divider to measure the voltage drop across the transistors and four standard resistors used to measure the total current through each transistor circuit. A simple program was written to monitor and log temperature, voltage and current readings via a dataTaker DT500, general purpose, data acquisition module. Eight (8) of the thermocouples were used to measure temperatures at various places through the cross section of the transistors and heat sink. Holes of 0.9 mm diameter were drilled halfway into the flange of each transistor (see Fig. 4) to allow thermocouples (nos. 1–4) to be embedded. Care was taken to locate the thermocouple junction in the middle of the flange so that it was placed within a 45
cone projecting vertically downwards from the junction. This is where the majority of the heat flow from the junction occurs and hence where the maximum flange temperature is measured [11]. Thermocouples (nos. 5–8) were embedded in the heat sink mounting pedestals directly adjacent to the interface with each transistor flange. For the transistor junction temperature predictions discussed here the pedestal temperatures were not required. However, they were used during sub-

Fig. 3. Schematic diagram of wind tunnel and electrical supply.

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T junct ¼ T fl þ ðRth junctfl ÞQ

Fig. 4. Detail of mounted transistor with PCB removed.

sequent experiments to determine the interface thermal resistance, which will be discussed in Sections 3 and 4. The holes in the transistor flanges and heat sink mounting pedestals were refilled with epoxy mixed with aluminium powder to hold the thermocouples in place and maintain the thermal conductivity of the solids as much as possible. The final thermocouple (no. 9) was placed in the wind tunnel, 100 mm upstream of the heat sink to measure inlet air temperature. All thermocouple readings were calibrated against a Fluke 2180A RTD (resistance temperature detector) with maximum error in the final values estimated as ±0.5
C. A series of experiments were conducted to estimate the junction temperatures experienced by the high power, output transistors in the field. Even though power to the transistors was supplied independently of the amplifier circuit, the PCB was set in place on the heat sink for these experiments to ensure flow conditions inside the wind tunnel and through the heat sink fins replicated field conditions as closely as possible. The power dissipation within each transistor was set to 130 W since this was the maximum power level determined by the authors in previous experiments [10]. The inlet air temperature was varied by adjusting the heater setting and the bulk airflow rate was set to 75 l/s to replicate conditions in the field. For each heater setting thermal equilibrium was considered to be reached when the change in transistor flange temperature was less than 0.1
C over a 90 s interval. Once equilibrium conditions were reached the transistor junction temperatures, inlet air temperature and transistor voltage drop and currents were recorded. Since it is not possible to directly measure junction temperature using conventional thermocouple techniques the manufacturers specified value for thermal resistance from the transistor flange to transistor junction, Rth junct-fl, was used. For r.f. power dissipation the Philips Semiconductors data sheet for BLW96 transistors specifies a value of 0.45 K/W [3]. As such the junction temperature is calculated as follows:

715

ð2Þ

where Tjunct is the transistor junction temperature [K], Tfl equals the transistor flange temperature [K] and Q equals the power dissipated by each transistor [W]. The relationship between transistor junction temperature and inlet cooling air temperature for a power dissipation level of 130 W per transistor and a bulk airflow rate of 75 l/s is shown in Fig. 4. Here, the four output transistors are labelled TR13 through the TR16 to match their designation on the PCB. The dotted lines represent the upper and lower limits of the data obtained for the four discrete transistors and the bold filled line through the middle represents average data values. The gradient of the maximum temperature data plot is 1.04. Using this value the data can be extrapolated to estimate that junction temperatures will begin to exceed 200
C when the ambient air temperature reaches 60.9
C. 2.2. Junction temperatures in the field To test the accuracy of the laboratory estimates and confirm the existing thermal conditions four amplifier modules was instrumented and prepared for field trials. In the field the 440 W amplifier shown in Fig. 1 provides one quarter of the output of a 1.6 kW amplifier assembly (see Fig. 5). Cooling air is pumped into the base of the

Fig. 5. 1.6 kW amplifier assembly.

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assembly and exits from the top. Due to the positioning of a power combiner unit, with incorporated heat sink, between the amplifiers in location a and b and the fact that air is heated as it passes upwards through the whole assembly the amplifier in location a was expected to experience the worst thermal conditions. The data acquisition system described in Section 2.1 was modified to allow eighteen (18) K-type thermocouples to be fitted to the 1.6 kW amplifier to monitor transistor temperatures over a range of field operating conditions. Since it was not possible to drill into the flange of transistors on operational amplifiers in the field, a single thermocouple was instead attached to one of the mounting screws on each of the sixteen output transistors in the 1.6 kW assembly (four transistors per 440 W amplifier · 4 amplifiers in 1.6 kW assembly). Separate experiments were conducted under laboratory conditions to determine the relationship between the temperature rise from the mounting screw to the centre of the copper flange, DTsc-fl, and the power dissipated by the transistors, Q. Experiments were conducted at 70 W, 100 W and 130 W dissipation and the ratio of DTsc-fl to Q was found to be 0.209. A single thermocouple mounted at the base of the assembly monitored ambient air temperature and a final thermocouple mounted at the top was used to monitor exhaust air temperature (not used here). Data was collected at a remote transmitter site in regional Australia over the course of a week. During testing, ambient air temperatures varied between 21 and 35
C. A total of 26 separate thermal tests were conducted with transistor temperatures, ambient and exhaust temperatures and the main electrical parameters, including r.f. signal frequency, transmitter output power and power reflection from the antennae back to the amplifiers, being recorded. The effects of the various electrical parameters on the transistor power dissipation levels will be discussed in more detail later in this section. Due to the high power, r.f. transmission environment, interference issues were initially encountered with some of the thermocouple readings. The problems worsened when transmitting in the higher frequency bands (i.e. above 20 MHz across a possible range of 5– 40 MHz), however a small degree of interference was noted even at lower frequencies. To partially combat this the thermocouple leads extending outside the 1.6 kW casing were wrapped through a ferrite in an effort to eliminate current being induced in the leads due to r.f. signal interference. This modification provided an improvement however four thermocouples (one per amplifier) still provided erratic results at some frequencies and had to be disregarded for these trials. The inlet and outlet air temperature results were not affected by this problem. Since the ambient air temperature varied from test to test, to allow comparisons to be made it was necessary to

extrapolate the results of each of the 26 trials to determine the maximum junction temperatures within the 1.6 kW amplifier when the ambient air reached a preselected level. An ambient temperature of 60.9
C was chosen as this was the level determined earlier during bench tests for the transistor junction temperatures to begin to exceed 200
C. The output transistor junction temperatures within the 1.6 kW amplifier assembly when the ambient air temperature reached 60.9
C were calculated using the following two equations: T junctðambÞ ¼ T sc þ ð0:209 þ Rth junctfl ÞQ

ð3Þ

T junctð60  CÞ ¼ T junctðambÞ þ 1:04ð60:9  T amb Þ

ð4Þ

where Tjunct(amb) is the junction temperature at actual ambient [K], Tsc equals the mounting screw temperature [K], 0.209 is the ratio of DTsc-fl to Q, Tjunct(60
C) is the junction temperature extrapolated to 60.9
C ambient [K], 1.04 equals the gradient of junction temperature versus inlet air temperature curve (see Fig. 6), and Tamb equals the ambient air temperature during each test [K]. As expected, transistor temperatures in amplifier location a were consistently the highest within the 1.6 kW assembly. The average maximum junction temperatures at amplifier locations a and b have been extrapolated for ambient conditions of 60.9
C and are plotted in Fig. 7. The significant variation in maximum junction temperatures can primarily be explained by two phenomena caused by the constantly changing electrical operating parameters of the transmitter. The first of these is variation in r.f. signal frequency which effects transistor efficiency and hence power dissipation levels. The second is the steer angle of the signal being transmitted which also changes continuously to force the transmitter signal to sweep back and forth across the sky. This in turn affects the power reflected from the antennae back to the

Fig. 6. Transistor junction temperature vs. ambient air temperature.

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Fig. 7. Average maximum junction temperatures measured at transmitter location (extrapolated to 60.9
C ambient air temperature).

amplifier. The higher the reflected power, the greater the amount of work the amplifier needs to do in order to maintain a constant output power level. The data in Fig. 7 shows reasonable agreement between the bench test estimates obtained in the laboratory and the field measurements for amplifier a with junction temperatures during test 80410 actually equal to 200.1
C when extrapolated to an ambient temperature of 60.9
C. Based on the results reported here it is reasonable to assume that some of the high power transistors may begin to operate above the rated maximum junction temperature of 200
C under the harsh ambient and power dissipation conditions specified for this equipment. As such, it is of great importance to the ongoing reliability of the amplifiers that methods to reduce transistor device temperatures be investigated.

One such method is the reduction of thermal resistance at the interface between the transistor flange and heat sink.

3. Thermal resistance Fig. 8 shows the interface between the transistor flange and heat sink. The total interface resistance, Rint, can be written as follows: Rint ¼ Rcont 1 þ Rbulk þ Rcont 2

ð5Þ

Here, Rcont 1 and Rcont 2 are the thermal resistances at the interface between the TIM and each of the interface surfaces and Rbulk is the bulk resistance of the TIM. When discussing interface resistance the average thickness of

Fig. 8. Photo of transistor mounted on aluminium heat sink (inset shows thermal path across interface).

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the TIM is generally referred to as the bond line thickness. While the linear temperature drop through the TIM material is a function only of bulk thermal conductivity and heat flux, the temperature drop at each of the contact surfaces depends strongly on surface geometry, contact pressure and the ability of the TIM to flow in and fill the microscopic surface interstices. As such Rcont 1 and Rcont 2 can differ across the same interface and are not a function of the TIM only. The gradient of the temperature drop at each of the contact surfaces is also generally much larger than that across the TIM due to real world imperfections in the wetting of the contact surfaces by the TIM [12]. In this study no effort is made to separate the contributions of Rcont 1, Rbulk and Rcont 2 to the total resistance. Only the total thermal resistance, Rint, has been considered and was determined experimentally as follows: Rint ¼

T fl  T hs Q

ð6Þ

Here, Tfl is the transistor flange temperature, Ths is the temperature of the heat sink and Q is the power dissipation across the interface.

4. Thermal interface materials 4.1. Experimental setup Fig. 9 provides additional detail of the thermocouple placement used for the laboratory experiments described in this paper. During experiments to determine interface resistance, the PCB was removed from the heat sink and

replaced by a 22 mm thick fibre glass insulation layer. This was done to minimise convection losses from the ceramic case of the transistors (previously estimated at less than 2% with the PCB in place) and ensure the majority of the dissipated power passed through the interface area. For each test the heat sink and transistors were allowed to reach steady state temperatures before the values of Tfl, Ths and Q for each of the four transistors were recorded. Average values of Tfl and Ths and Q were then used in Eq. (6) to calculate interface resistance. The method described here for calculating Rint effectively uses the maximum flange and pedestal temperatures to determine the temperature drop across the interface. However, since the area of the transistor die is smaller than the total flange area, a non-uniform temperature profile will be created at each of the contact surfaces. A numerical model of the heat sink and transistors, developed by the authors in [10] was used to estimate the error in the calculated interface resistance due to this. Using numerical data obtained through computational fluid dynamics simulations, the actual temperature deviation across the flange was found to be 0.6 and 4.4
C across the pedestal contact surface. Rint was then calculated, first using point temperature measurements and subsequently using average contact surface temperatures. The difference in results was found to be less than 7%. This introduces a source of error when comparing data obtained here with that obtained on test rigs designed to ASTM D5470 where uniform temperature profile of each contact surface is maintained. However, the back-to-back comparison of the relative performance of various interface materials, which forms a significant part of this study, will not be affected. The high power transistors are currently attached to the heat sink using two screws with a proprietary thermal grease applied at the interface (k = 0.6 W/m K). This thermal conductivity is well in excess of the value of 0.0242 W/m K for air but much lower than the typical values of 350 and 150 W/m K for the copper flange and heat sink aluminium respectively. As such, like most thermal interface compounds, the current grease exhibits a considerably high thermal resistance. A series of experiments were conducted to determine the effectiveness of a range of thermal TIMs in minimising Rint. Two separate sets of experiments were conducted to measure Rint when the TIMs were applied under the following conditions: 1. as per the standard field assembly procedure, and 2. after careful preparation of the interface surfaces.

Fig. 9. Schematic view of experimental setup (side view).

4.1.1. Standard field assembly In between tests the transistor flange and heat sink pedestal surfaces were cleaned with isopropanol to re-

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move any existing heat sink compound residue. In the case of thermal greases the compounds were applied thinly to both the flange and pedestal surfaces and the excess was removed using a straight edge. Gap pad and phase change materials were trimmed to cover the footprint of the transistor flange with two holes punched out to allow for the mounting screws. The two mounting screws were then tightened to approximately 1.25 N m. For the lower viscosity thermal grease compounds this tightening was noted to help remove excess compound from the interface, thus reducing thermal resistance. No extra surface preparation was carried out for these trials. An airflow of 100 l/s was forced across the heat sink fins to provide adequate cooling. It is important to note here that in this study no attempt has been made to estimate the average clamping pressure across the transistor flange area based on the mounting screw torque of 1.25 N m mentioned previously. This is due to the non uniformity in pressure distribution that has been shown to exist at bolted flange joints such as the interface considered here [13]. As a result of this phenomenon, a large percentage of the flange directly below the heat source exhibits a much lower contact pressure than in the area directly adjacent to the mounting screws. The non-uniform pressure distribution in this application is significantly different to the uniform pressure distribution achieved in tests based on ASTM D5470 and reinforces the need to obtain application specific thermal resistance data. 4.1.2. Careful surface preparation A second set of trials was then run to address the specific issues of surface cleanliness, roughness and flatness. The purpose of these trials was to compare published data with measured data for the subject TIMs. Whereas

719

Gwinn and Webb [4] proposed a cleaning process involving a boiling bath to remove TIM residue from the microscopic interstices, here the surfaces were cleaned with 1200 grit emery paper placed over a known flat surface between each test. This not only removed previous TIM contamination but also ensured consistent flatness and roughness of the flange and pedestal surfaces. Average surface roughness, Ra, of the copper flanges was measured using a stylus profilometer both before and after polishing with emery paper. After initial surface cleaning with isopropanol only, the flange roughness was measured at between 0.4 and 0.9 lm. This value dropped to 0.2 lm after polishing with emery paper. Cleaning with emery paper also greatly improved the surface flatness of the transistor flanges, as will be discussed in the following section. 4.2. Transistor flatness Inspection of 20 failed transistors from the field showed that surface flatness is a major variable in this application with just over 50% of the transistors exhibiting a gap in excess of 0.025 mm between the middle of the flange mounting face (i.e. the area directly below the junction) and a known flat surface (see Fig. 10). During the experimental program, polishing of surfaces with emery paper placed over a flat surface was used to reduce this air gap to a nominal value of 0.0 mm in all cases where careful surface preparation is mentioned. New transistors showed no signs of the flange warping witnessed on failed devices indicating that warping occurs over the life of the device. In this application, transistor efficiency is strongly dependant on r.f. signal frequency and the steer angle of the transmitted signal. Both of these parameters constantly fluctuate under

Fig. 10. Typical air gap dimensions on failed transistors taken from the field.

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normal operating conditions causing thermal cycling of the transistors. Fig. 11 shows that under regular operation, transistors are subjected to significant cycling at elevated temperatures. Here, the graph shows flange temperatures for three of the four transistors (TR14, TR15 and TR16) in the high power amplifier in location a of the 1.6 kW amplifier assembly. Due to r.f. signal interference the thermocouple attached to transistor TR13 provided erratic results and was not considered. Note that under maximum power dissipation and higher ambient temperatures the maximum flange temperatures have been shown to rise even further than those in Fig. 11 (up to 110
C). The data shows that rapid rises and falls in junction temperature cause flange temperatures to consistently change by up to 20
C in as little as 10 s. These fluctuations cause large transient thermal gradients within the transistor and are considered likely to contribute to the warping of the copper flange, and subsequent increase in interface thermal resistance, over time. Since only a limited supply of working transistors could be obtained from the field for the purpose of the tests described here, it was not possible to ensure that each of the four transistors exhibited the same degree of warping of the flange. However, the transistors selected were representative of those currently in operation in the field and were retained throughout the test program to ensure that measured values of Rint could be fairly compared. 4.3. Thermal interface materials considered Table 1 lists selected published data for the range of thermal greases, gap pad materials and phase change materials selected for the trials. Since one of the main purposes of this study is to evaluate the relative performance of various types of TIM in a high power amplifier

Fig. 11. Typical transistor flange temperature fluctuations in the field (28.5
C ambient).

application, and not to promote individual manufacturers, generic labels have been used in place of product trade names. For further comparison, three home-made TIM compounds made by mixing silicone oil and grease with varying weight fractions of aluminium powder filler were also tested. Table 1 also shows the relative ranking (in parentheses) of each TIM based on both published data and data obtained independently here when surface flatness and roughness were maintained at a consistent level. The label ‘‘Compound D’’ refers to the thermal grease that is currently applied at the transistor/heat sink interface. It consists of a silicon oil medium with zinc oxide filler and has a relatively low specified thermal conductivity of 0.6 W/m K. Compound A is a silicon based oil containing silver particles to maximise bulk thermal conductivity while Compound B is a compound containing carbon and silicone oxide filler. Compound C is a gel like elastomer supplied in two parts that cure when mixed together. The curing process is intended to provide the advantage of low viscosity during application while not pumping out or bleeding from the interface during operation. Compounds A and B were selected as having values of thermal conductivity much higher than that of the current compound, Compound D, while Compound C was selected as having a mid range value. Gap pad A contains a central aluminium foil layer coated with rubber on each side while Gap pad B is a silicon based elastomer. Each of the gap pad materials chosen has a published thermal conductivity well above that of the current grease. However, the disadvantages of this type of TIM are the finite minimum thickness over which the heat must pass and the inability of the gap pad to flow in and fill the microscopic surface roughness interstices thus leaving small air gaps of very high thermal resistance. The phase change material selected for trials here consisted of an aluminium substrate coated with a dry compound which is designed to melt and flow into the remaining air gaps when the temperature at the interface exceeds 60
C. The material is supplied in varying thickness to match the surface finish of the intended application. For applications where surface waviness is large a thicker coating of compound is recommended. The best thermal performance is achieved with the thinnest coating used on contact surfaces of minimal waviness and roughness. Here two thicknesses of the same phase change material (Phase Change Material A @ 0.064 mm thick and Phase Change Material B @ 0.074 mm thick) were tested to determine the effects of compound initial thickness on thermal resistance. When phase change materials are first applied they exhibit relatively high thermal resistance until the materials exceeds its melting point and flows in to fill the remaining air gaps. After this first reflow stage the thermal resistance drops and

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Table 1 Thermal resistance of interface materials selected for trials Manufacturers specification Surface contact condition

Thermal grease Compound A

Measured data 2

Rint K cm /W (ranking)

Conductivity (W/m K)

Rinta

Rintb

Thickness (mm)

K/W

K cm /W

K/W

K cm2/Wd (ranking)

2

c

0.0254 mm (0.00100 ) thick layer 50 psi clamping pressure 0.076 mm (0.00300 ) thick layer NP

0.032 (1)

>9.0

N/A

–

–

0.145

0.284 (2)

0.226 (4) 0.379 (5)

>7.5 2

N/A N/A

0.121 0.240

0.237 0.470

0.091 –

0.178 (1) –

NP (6d)

0.6

N/A

0.252

0.494

0.149

0.292 (3)

50 psi clamping pressure 50 psi clamping pressure

1.419 (7) 2.065 (8)

2.5 3.5

0.165 0.279

0.480 0.668

0.941 1.309

0.487 –

0.951 (9) –

Phase change material Phase change A 50 psi clamping pressure Phase change B 50 psi clamping pressure

0.058 (2) 0.077 (3)

0.064 0.074

– –

– –

0.192 0.209

0.376 (4) 0.410 (5)

– – –

– – –

0.254 0.256 0.305

0.498 (6) 0.501 (7) 0.597 (8)

Compound B Compound C Compound D (current) Gap pad material Gap pad A Gap pad B

Homemade compounds Silicone oil A N/A Silicone oil B N/A Silicone grease A N/A

N/A N/A N/A

N/A N/A N/A N/A N/A

N/A N/A N/A

NP: not published, N/A: not applicable. a Flange and pedestal surfaces cleaned with isopropanol only. b Flange and pedestal surfaces prepared with emery paper to ensure flatness and consistent roughness. c Calculated from measured K/W value using an actual transistor flange footprint area of 1.96 cm2. d Estimate based on thermal conductivity value.

should stay relatively constant across all operating temperatures. To ensure that phase change materials experienced melting in all experiments the flange and heat sink temperatures were monitored to ensure that phase change of the compound occurred prior to determining the final thermal resistance of the product. Since the exact composition of commercially available TIMs is generally not published, in order to protect intellectual property rights, it was decided to test three additional home made interface materials. The home made materials were composed of either a silicone grease or silicone oil medium with aluminium powder added to increase bulk thermal conductivity. To test the effects of the weight fraction of filler on thermal resistance Silicone Oil A contained a 3:1 ratio by weight of aluminium to oil while Silicone Oil B contained a 2:1 ratio by weight. A final compound, Silicone Grease A, was prepared to test the effects of the viscosity of the medium on thermal resistance. The silicone grease compound also contained a 2:1 ratio by weight of aluminium to silicone to allow direct comparison with Silicone Oil B. During preparation the grease compound was noted to exhibit a much higher viscosity than either of the oil compounds.

4.4. Interface resistance results and discussion The final four columns of Table 1 show the values of thermal interface resistance determined through experiments in this study. The columns labeled RA int refer to results obtained when the transistors were assembled as per the current field assembly procedures with no surface preparation apart from cleaning with isopropanol to remove any previous TIM residue. The columns labeled RBint refer to results obtained when the surfaces were further prepared by cleaning with 1200 grit emery paper stretched across a known flat surface. All experimental values from this study are shown in comparison to the manufacturers published data on the left hand side. By first considering the results under the heading RA int it can be seen that on the whole, the thermal grease compounds outperformed the elastomeric pad materials in this application. The current grease exhibited a resistance of 0.494 K cm2/W. At maximum power dissipation of 130 W across the transistor footprint of 1.96 cm2 this equates to a temperature rise of 32.8
C and represents a considerable contribution (23.4%) to the overall temperature rise of 140
C from the ambient air temperature to the transistor junction temperature. The use of

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Compound B in this instance provided a significant drop in thermal resistance at the interface with a measured value of 0.237 K cm2/W. This value of Rint corresponds to a temperature rise at the interface of only 15.7
C at maximum power dissipation (i.e. 17.1
C drop in transistor junction temperature against Compound D). Apart from having a high published bulk conductivity of >7.5 W/m K, Compound B also exhibited fairly low viscosity which allowed a very thin bond line thickness of TIM between the transistor flange and heat sink pedestal when the mounting screws were tightened. Compound C provided only a modest improvement over Compound D even though it has a published bulk thermal conductivity over three times that of Compound D. This may be partially due to the fairly high viscosity noted for this product compared to both Compounds B and D. As a result the tightening of the mounting screws did not displace as much of the compound during assembly as it did for Compounds B and D. This was further confirmed when the transistors were removed and the cured TIM was peeled away from the interface to show a relatively thick layer of compound directly below the transistor junction area of the flange and a thinner layer near the mounting screws. This is attributed here to both the typical warping of the flanges discussed in Section 4.2 and the fact that the bolted flange type mounting method does not apply an even pressure distribution across the entire interface. In their work on interface pressure distribution in a bolt-flange assembly subjected to heat flux, Itoh et al. [14] showed that under shock like thermal loading (shown in Section 4.2, Fig. 11, to exist in this application) the pressure distribution varies significantly as distance increases from the centerline of the bolt due to concave like thermal deformation of the flange (i.e. transistor) to the mounting surface (i.e. heat sink). As suggested in [4,6] elastomeric pad materials require very high interface pressures to fill the interstitial air gaps due to surface roughness. In this application these materials (Gap pads A and B) did not perform as well as the current thermal grease compound. This suggests that the interface pressure in this application was insufficient to achieve full displacement of all the air from the interface. Also both materials have relatively large initial thickness which prevents any metal to metal contact in the assembled interface. This is a distinct disadvantage when compared to low viscosity grease compounds where low bond line thickness and surface-to-surface contact at the interface are possible. The uneven pressure distribution outside of the area directly below the head of the mounting screws was also evident when examining Gap pad B samples after testing. In the area directly surrounding the mounting screw holes the elastomer showed signs of being compressed to zero thickness by the pressure between the screw head and the heat sink. However the indentation from the

transistor flange across the rest of the area was not noticeable indicating much lower interface contact pressure in the main area of the flange directly below the junction (i.e. heat source). This is in contrast to most industry test rigs designed around ASTM D5740 test procedures, which incorporate a load device to ensure even pressure distribution across the entire interface area and goes some way to explain the differences between results obtained in this study and those published by the manufacturer. Inspection of the data in the final two columns of Table 1 gives an insight into TIM performance improvements based on effective control of interface surface flatness. For the thermal grease compounds, thermal interface resistance was reduced in each case due to improvements in both surface flatness and surface roughness brought about by the additional surface preparation with emery paper. In effect, this improvement of the contact surfaces significantly reduced the total volume of the air pockets between the mating surface needing to be filled with relatively low conductivity thermal grease. Tests in this round were extended to include an additional thermal grease, Compound A, which has a published thermal resistance of 0.032 W cm2/K, two samples of varying thicknesses of a proprietary phase change material and three home made silicone/aluminium compounds. Compound C was not tested again as its performance was similar to Compound D in previous testing and Gap Pad B was not tested due to poor results in earlier tests. Once again, the thermal greases outperformed the other candidate materials. When compared to the baseline results where surfaces were cleaned with isopropanol only, the thermal resistance of the current material, Compound D, fell by 40% from 0.494 to 0.292 K cm2/W. This represents a drop in transistor junction temperature of 13.4
C at maximum power levels. The thermal resistance of Compound B also fell by 25% from 0.237 to 0.178 K cm2/W through careful preparation of the contact surfaces to improve flatness. This difference in percentage improvement is thought to be due to the higher viscosity of Compound D versus Compound B. When Compound D was applied to flanges exhibiting warping, very little of the excess grease was squeezed from the interface during tightening of the mounting screws, leaving a considerable amount of the compound retained within the interface. This was confirmed through visual inspection when transistors were removed from the heat sink at the completion of testing. When Compound B was applied to warped flanges, the compounds lower viscosity made it not only easier to apply a very thin coating, but also more of the excess grease seemed to be displaced during screw tightening. Again this was confirmed when transistors were removed at the conclusion of testing. In each case, the amount of excess grease being retained at the interface

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was reduced when the copper flanges were prepared to ensure flatness. However, the extremely non-uniform nature of the pressure distribution across the flange area is thought to exacerbate the problem of excess grease being retained when a higher viscosity compound is used. Overall, the results indicate that by using Compound B on flat contact surfaces in this application (Rint = 0.178 K cm2/W) the transistor junction temperatures can be reduced by up to 21.0
C compared to when Compound D is used on contact surfaces that have warped over time (Rint = 0.494 K cm2/W). This is a considerable improvement and in itself would ensure that the transistor junction temperatures did not exceed their maximum rated temperature of 200
C under normal field conditions. An interesting observation here is that in this application Compound A performed only marginally better than the current Compound D. When compared to the published data, the results for Compound A were somewhat disappointing. The published data in Table 1 also highlights the current difficulty in determining relative performance of various interface materials based purely on standard test results. While the published values of thermal conductivity for Compounds A and B are of the same order of magnitude (i.e. >9.0 and >7.5 W/ m K respectively) the values of Rint differ by a factor of 10. While the reason for the large disparity between published and test data obtained here for Compound A is unknown, the results illustrate the importance of obtaining application specific data for use in detailed design of thermal paths in electronics cooling. The results for Gap Pad A suggest that its performance is not greatly affected by the improvement in surface flatness brought about by the additional preparation of the contact surfaces. This seems reasonable when considering that the typical thickness of the pad material is 0.165 mm and the maximum air gap on 75% (i.e. 15 out of 20 transistors, see Fig. 10) of warped transistors was measured at less than 0.04 mm or 25% of the original TIM thickness. The material selection and thickness of gap pad materials is such that they are effective in filling surface waviness imperfections but less effective in filling the microscopic interstices. These results suggest that although overall thermal performance is poor here, when compared to each of the other types of interface material tested, Gap Pad A effectively performs the task of filling the air gaps caused by the surface waviness of warped transistor flanges originally noted in this application. Based on published data the phase change materials tested here ranked 2nd and 3rd behind only Compound A. One of the intended deign benefits of PCMs is the ability of the material to flow in and fill the air gaps after it reaches its melting (phase change) temperature for the first time. The intention here is to eliminate contact resis-

723

tance between the PCM and each contact surface and provide an interface where thermal resistance is based solely on the bulk thermal conductivity of the compound and the bond line thickness. However, as with thermal greases the ability of the material to achieve this goal is governed by the properties of the medium and thermal filler and how well they flow in to fill the microscopic air gaps in the end application. This phenomenon will be discussed further later in this section. Fig. 12 shows the thermal resistance data obtained for Phase Change Materials A and B during testing. The graph shows that during the first reflow the interface resistance is initially relatively high but continues to fall as the temperature of the heat sink approaches the melting temperature of the phase change material. Melting was ensured by a running a series of tests where power dissipation was stepped up in each case until melting temperature of the PCM was reached. The onset of this phase change was confirmed by a flattening of the gradient of the interface resistance versus heat sink temperature curve. At the melting point the compound flows in to improve contact with each of the mating surfaces and the thermal interface resistance reaches a minimum level as heat sink temperature continues to rise. In the data obtained here interface resistance was shown to drop slightly during subsequent test sequences at lower values of heat sink temperatures but rose again as heat sink temperatures exceeded the PCM melting temperature. As such the quoted value of Rint in Table 1 was taken as the value where the curve flattens off when the melting temperature is reached. As expected, Phase Change Material A produced a lower final value of Rint due to its lower initial thickness. The rankings in the final column of Table 1 show that while the PCMs tested here were outperformed by only the thermal grease compounds, the absolute results for thermal resistance were much higher than those quoted by the manufacturer. There are several causes that contribute to the discrepancy in results. One of these is interface pressure distribution. In test rigs working to ASTM D5740 test procedures the pressure is applied

Fig. 12. Phase change material performance curves.

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uniformly across the interface. In this application it has already been noted that the two-screw flange assembly method will lead to non-uniform pressure across the flange with maximum load occurring near the periphery of the transistor flange where heat flux drops off. The thermocouple placement described in tests here will also lead to differences since the thermocouple junctions are positioned up to 1 mm from the contact surface in the transistor flange. Therefore, Rint here is based on the temperature at the middle of the flange as opposed to at the contact surface. In contrast, the contact surface temperatures tend to be accurately calculated using temperature gradients in the test blocks, in ASTM D5740 rigs. As previously mentioned, the thermocouple readings in experiments conducted here also do not account for the non-uniform temperature distribution across the two interface surfaces caused by the difference in area of the transistor die and the copper flange. This problem is avoided in most standard test rigs by ensuring a uniform temperature distribution across the interface area. By necessity, the test block contact surfaces in manufacturers test rigs will also be much better than the range of surface flatness/surface roughness combinations in the field since it is not feasible for manufacturers to test every possible combination. As such manufacturers in-house test rigs will tend to be manufactured with ground or polished surfaces of well controlled flatness. One final source of error is the value chosen for contact area, A. In this application this value has been defined to include the area of the two mounting holes in the copper flange. However this area is actually filled by the mounting screws which are made from a different materials to either the transistor flange or heat sink pedestal. The range of home made silicone/aluminium compounds provided medium to poor performance, outperforming only the elastomeric gap pad materials tested here. Prasher et al. [15] investigated the performance of particle laden interface materials and discussed the trade off between increasing bulk thermal conductivity of grease type compounds (by increasing the amount of filler particles in the compound) and the associated increase in bond line thickness of the TIM for a given contact pressure. This is based on the fact that while increasing the weight or volume fraction of the filler will increase bulk thermal conductivity it will also increasingly prevent the mating surfaces from coming in direct contact. Through experiments they demonstrated that a minimum value of thermal interface resistance could be achieved based on the optimum filler particle volume fraction. While the results here do not provide an extensive enough database to determine the optimum weight ratio of aluminium to silicone they do show that in the case of Silicone Oils A and B, the increase of aluminium filler does not significantly effect thermal interface resistance and in fact marginally increases it. The viscosity of

the medium has a marked effect on thermal resistance as shown by the comparison between Silicone Oil B and Silicone Grease A, each of which have the same aluminium to silicone weight ratio. The higher viscosity grease is less effectual in flowing in to fill the microscopic air gaps which results in an increase in thermal resistance of approximately 20%.

5. Conclusions Experiments under laboratory and field conditions have shown that the junction temperatures of the high power output transistors in r.f. signal amplifiers can begin to exceed their maximum rated temperature of 200
C under the harsh operating conditions that exist at transmitter locations in outback Australia. Measurements also revealed the significant thermal cycling at elevated temperatures that the transistors are subjected to in the field. Warping of the transistor flange has been shown to have a significant effect on the thermal interface resistance between the high power components and the heat sink. Experiments conducted using a range of commercially available and home made thermal interface materials under various transistor assembly procedures lead to the following conclusions in relation to this application; 1. Using the current thermal grease compound under maximum power conditions, the temperature rise across the device/heat sink interface is 32.8
C or 23.4% of the total temperature rise from ambient to transistor junction temperature. 2. Careful preparation of the transistor flange and heat sink pedestal surfaces to improve flatness and roughness lead to a device temperature reduction of 13.4
C when using the current thermal grease at maximum transistor power dissipation. 3. When a high performance thermal grease was used in conjunction with careful surface preparation a device temperature reduction of 21.0
C was achieved against the current thermal grease used on warped surfaces. 4. In this application commercially available thermal grease compounds outperformed elastomeric pad materials, phase change materials and home made silicone/aluminium compounds. 5. Measured values of interface resistance varied significantly from published data, highlighting the importance of obtaining accurate, application specific thermal data for predicting device junction temperatures. 6. The relative performance (ranking) of various types of interface materials varied between the application specific data from this study and published

L. Maguire et al. / Microelectronics Reliability 45 (2005) 711–725

data (e.g. phase change materials dropped several positions here) indicating that test rigs and/or specific applications may be biased towards different types of TIM.

Acknowledgements This work has been partially funded by the Australian Research Councils Linkage program and BAE Systems Australia Limited.

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