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Test generation for circuits described in procedural hardware description languages (HDLs)
North-Holland Microprocessing and Microprogramming 18 (1986) 371-380
371
TEST G E N E R A T I O N FOR C I R C U I T S D E S C R I B E D H A R D W A R E D E S C R I P T I O N L A N G U A G E S (HDLs)
K.Sapiecha,T.Czichon, Institute W a r s a w U n i v e r s i t y of Technology,
IN P R O C E D U R A L
of C o m p u t e r Science, 00-665 WARSAW, P O L A N D
In the paper a n e w m e t h o d for g e n e r a t i n g tests f r o m p r o c e d u r a l HDL description of a c i r c u i t is given. A processor for executing a procedure is used as a test model of the circuit considered. The p r o c e s s o r ' s functions are d e s c r i b e d by means of the s o - c a l l e d b i n a r y lists. Binary lists are of regular s t r u c t u r e w h i c h makes their s y m b o l i c m a n i p u l a t i o n easy. Test g e n e r a t i o n c o n s i s t s in d e r i v a t i o n of the s o - c a l l e d fault sensit i z a t i o n f u n c t i o n and fault p r o p a g a t i o n function from b i n a r y lists c o r r e s p o n d i n g to all bits of the variables. All the above m a n i p u l a tions could be e a s i l y i m p l e m e n t e d with the help of such languages as PROLOG.
i.
INTRODUCTION
HDLs are useful as input media of h ardw a r e compilers and simulators, as a concise high level n o t a t i o n tool for d e s i g n i n g , teaching, and other forms of c o m m u n i c a t i o n . It seems to be d e s i r e d that HDL c i r c u i t description should also be convenient as input data for test p a t t e r n generation systems. Two kinds of Hardware Description Languages are distinguished: nonp r o c e d u r a l and p r o c e d u r a l ones. Nonprocedural languages make possible s t r u c t u r a l d e s c r i p t i o n of digital circuits. Procedural languages make possi b l e their functional description, particularly of microprocessors and m i c r o p r o g r a m m e d circuits. For a c i r c u i t d e s c r i p t i o n g i v e n in a non-procedural language, test generation m e t h o d s have already been developed [LEV'82 and '83, HAR'85]. A few a p p r o a c h e s to test generation based on a p r o c e d u r a l HDL description have also been developed. The first one, p r e s e n t e d in [SU'82], is based on Data Graph and extended D-algebra. Test generation for a given fault consists in propagating D-cube along a path (selected by means of Data Graph) from command point to observation point. The second approach, presented in [SHEN'84], is based on critical path tracing. It is assumed here, that HDL i n s t r u c t i o n s describe combinational modules, for which c r i t i c a l cubes (C-cubes) can
be calculated. A HDL p r o g r a m determines the paths between these modules. Test generation consists in c a l c u l a t i n g the c r i t i c a l path from the last module (the last HDL instruction) to the first one. In the area of test g e n e r a t i o n from procedural circuit description there are two e s s e n t i a l problems that have not found s a t i s f a c t o r y solutions, so far. The first one concerns control v a r i a b l e testing. Test generation for control variable faults is complex. Control variables are not observable after assignments. T h e y cannot be inserted as part of the o p e r a t i o n a l module in c r i t i c a l path tracing. Therefore, it is a s s u m e d in methods which have been d e v e l o p e d so far, that control v a r i a b l e s and control paths are fault-free. Control variable faults in m o d e r n VLSI circuits cannot be neglected. A function of a circuit is more and more complicated, and every "data variable" can be used as a control v a r i a b l e in some HDL instructions. The other p r o b l e m is a s s o c i a t e d with analysis of actual HDL programs. The recent methods are useful for HDL programs, in w h i c h conditions for obtaining a required instruction s e q u e n c e are easy to formulate. There are no s o l u t i o n s for c o n d i t i o nal jumps and loops with c o n d i t i o n a l exits. A test g e n e r a t i o n m e t h o d which s o l v e s these problems is necessary. Each HDL program, w h a t e v e r its structure,
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K. Sapiecha, T. Czichon / Test Generation for Circuits in Procedural HDLs
should be a l g o r i t h m i c a l l y transformed into a shape, which is convenient for TPG system. Moreover, th~ method should work for c o m p l e x HDL descriptions, and for both data and control v a r i a b l e faults. In the paper such a test pattern generation method is presented. In s e c t i o n 2 a n e w n o t a t i o n for functional c i r c u i t d e s c r i p t i o n is given. It is called B i n a r y List N o t a t i o n (BLN). A new method of generating tests whi c h make use of this notation is p r e s e n t e d in s e c t i o n 3. The method is based on the c o n c e p t of b o o l e a n difference and is a d o p t e d for implementation with the help of a symbol m a n i p u l a t i o n technique.
2.
2.1.
CIRCUIT DESCRIPTION F A U L T MODEL Circuit
binational back lines.
feed-
AND C I R C U I T
description Fig.l.
It is assumed, that all data concerning a circuit is given in the form of a p r o c e d u r a l d e s c r i p t i o n . The d e s c r i p t i o n is a p r o c e d u r e with a head and a body. The former describes memory elements and inputoutput pins of the circuit. The latter describes connections between the elements, data operations performed in the circuit and sequencing of HDL instructions. As an example we shall consider a 2-bit m u l t i p l y i n g circuit. Using R T L - l i k e language its function may be described as follows (SU'82): INPUT: X ( X 2 : X I ) , Y ( Y 2 : Y I ) , X S , Y S , S T OUTPUT: A ( A 2 : A I ) , Q ( Q 2 : Q I ) , A S REGISTER: M,SC, B ( B 2 : B I ) , B S , Q S , E /0/ M=ST /I/ if M=0 then goto 0, else goto 2 /2/ B = X , B S = X S , Q = Y , Q S = Y S /3/ AS=QS • BS A=00, E=0, SC=0 /4/ if QI=0 then goto 6, else goto 5 /5/ E . A = A + B /6/ E . A . Q = s h r ( E . A . Q ) SC=not(SC) /7/ if SC=0 then goto 8, else goto 4 /8/ M=0, goto i. Based on this d e s c r i p t i o n a processor is p r o p o s e d as a test model of the circuit considered. 2.2.
block and external
Processor
The p r o c e s s o r c o n s i s t s of two units (fig.l): a control unit and an operational unit. Each c o n s i s t s of a com-
Processor.
To d e s c r i b e a function of the control unit, an extra n-bit variable, c a l l e d the phase v a r i a b l e (F), is introduced. It is assumed here, that HDL instructions as well as bits of the phase v a r i a b l e are n u m b e r e d by c o n s e cutive integers: 0,1,...,n. Fi is equal to 1 if and only if HDL number instruction being currently executed is equal to i. Phase v a r i a b l e can be u n d e r s t o o d as a m i c r o p r o g r a m m counter in a microprogrammed circuit. The processor is c o n t r o l l e d by a dual-step clock. Step one involves c a l c u l a t i o n s of the next value of the phase variable. Step two involves calculations of data and control variables. A processor for p e r f o r m i n g the 2-bit m u l t i p l i c a t i o n procedure is shown in fig.2. Actually in test g e n e r a t i o n there is no need to create a particular processor. It is used here m a i n l y to explain the c o n c e p t of iterative function which is going to be introduced later on and which is e s s e n t i a l for the test g e n e r a t i o n method which we deal with. 2.3.
Iterative
Function
Control unit functions and operational unit functions can be described by a set of nested if-clause structures. For e x a m p l e , l e t us c o n s i d e r the second bit of variable A (A2) of the
K. Sapiecha, T. Czichon / Test Generation for Circuits in Procedural HDLs
373
a) M,SC,QI
===>I
Control
I I====> I
i f=(f0,...,fS)=======>]
unit I
F=(F0,FI,...,FS)
I
b) F=(F0,...,FS) ===>I ] bs,qs,as i i OperationalJ a,b,e,q } . . . . . . . >I J.... m, sc i i unit I ST, X S , Y S , X , Y .... >I I
BS,QS,AS
=>A,B,E,Q M,SC
Fig.2. C o n t r o l unit a) a n d o p e r a t i o n a l unit b) of a p r o c e s s o r for performing of the 2 - b i t m u l t i p l i c a t i o n procedure (non-capital letters denote previous state variables]. examples BLN.
The above sequence of conditional assignments c a n be d e s c r i b e d b y the following if-clause structure:
B e l o w the b i n a r y list of A2 the ranges of "then" and "else" p a r t s for v a r i a b l e s F 3 , F 5 and F6 are m a r k e d .
A2
2.Let us c o n s i d e r bit F4 of the phase variable. Its n e x t s t a t e func t i o n is d e t e r m i n e d as f o l l o w s : - if p r e v i o u s i n s t r u c t i o n had n u m b e r 3, t h e n F4=I, else: if p r e v i o u s i n s t r u c t i o n had n u m b e r 7, then if SC was not e q u a l to 0 t h e n F4=I, else:
= if F3 t h e n 0, e l s e if F5 t h e n if a 2 O b 2 0 C Y else
if F6
then else
then else if ql then else if a2 t h e n else
i, 0; I, 0; i, 0.
It will be c a l l e d the I T E R A T I V E RULE of calculation of the next state f u n c t i o n of v a r i a b l e A2. Non-capital letters denote previous state variables, and e x t r a v a r i a b l e CY denotes a carry coming from the less s i g n i f i c a n t bit w h i l e addition of A a n d B is p e r f o r m e d .
explain
the m a i n
circuit discussed. The next state function of A2 is d e t e r m i n e d as follows: - if p r e s e n t i n s t r u c t i o n has number 3, t h e n A2 is e q u a l to 0, else: - if p r e s e n t i n s t r u c t i o n has n u m b e r 5 then the v a l u e of A2 is e q u a l to the s e c o n d bit of the s u m of A+B, else: - if p r e s e n t i n s t r u c t i o n has number 6, t h e n A2 is e q u a l to the previous v a l u e of E, else: - the v a l u e of A2 r e m a i n s u n c h a n g e d .
of
l.ln BLN the a b o v e iterative rule for variable A2 is expressed as follows: A2 =
=F3,0,F5,a20b20CY, IjO,F6,e,I,O,a2,1,O . . . . . . . . . . . . else . . . . . . . . . . . . . . . . . the~ .... t h e n . . . . . . . . . else . . . . . . -then- -else-
-
F4=0.
The if-clause follows: F4
structure
= if f3 t h e n i, else if f7 t h e n else
Iterative rules as g i v e n a b o v e are not convenient for processing. Of course, t h e y c a n be t r a n s f o r m e d into boolean expresions [LEV'82]. H o w e v e r , expresions are e q u a l l y inconvenient for processing, no m a t t e r w h i c h w a y of p r o c e s s i n g , n u m e r i c or symbolic, is c h o s e n . T h e r e f o r e , a n e w n o t a t i o n , called Binary List Notation is applied. A formal d e s c r i p t i o n of BLN calculus is g i v e n in [SAP'86]. The f o l l o w i n g
idea
The a b o v e in BLN as F4
iterative follows:
rule
for F4
is as
if sc then else 0.
I, 0;
is e x p r e s s e d
= f3,l,fT,sc,l,0,0 t h e n . . . . else .... -then- -else
In this tional cribed (BLs).
w a y f u n c t i o n s of b o t h operaand c o n t r o l u n i t s can b e d e s by a set of binary lists
374
K. Sapiecha, T. Czichon / Test Generation for Circuits in Procedural HDLs
It s h o u l d be e m p h a s i z e d that all can be derived directly from description. An algorithm of d e r i v a t i o n is as follows:
BLs HDL the
A.For every phase v a r i a b l e bit Fi: l. If (i-l)th i n s t r u c t i o n is a jump instruction or i=0 t h e n generate an initial list: L = 0 else g e n e r a t e an initial list: L = fi-l,l,0 2.For e v e r y u n c o n d i t i o n a l Jump: /j/ g o t o i g e n e r a t e a list: L = fj,l,L 3.For e v e r y c o n d i t i o n a l jump: /j/ if C O N D I T I O N then g o t o i else ... g e n e r a t e a list: L=fj,(CONDITION),I,0,L 4.For e v e r y c o n d i t i o n a l jump: /J/ if C O N D I T I O N then g o t o ... else goto i g e n e r a t e a list: L=fj,(CONDITION),0,I,L 5 . I n s e r t all BLs for C O N D I T I O N S into list L. B.For e v e r y d a t a v a r i a b l e bit Vi: l.Generate the initial list: L = vi,l,0 2.For e v e r y a s s i g n m e n t : /j/ Vi = EXPRESSION g e n e r a t e a list: L = Fj,(EXPRESSION),I,0,L 3.Insert all BLs for EXPRESSIONS into list L. Remarks: l.The insertion of CONDITIONs and E X P R E S S I O N s is p e r f o r m e d a c c o r d i n g to the s i m p l e a l g o r i t h m here introduced with the help of an example.As an example let us c o n s i d e r expression (m=0) (see tab.l), w h i c h is inserted into i t e r a t i v e rule for F0. After execution of steps A . I - A . 4 of the algorithm the f o l l o w i n g BL is obtained: F0=fl,(m=0),l,0,0. Inserting e x p r e s s i o n (m=0), its zeros in s o u r c e BL are r e p l a s e d by the "else" part of (m=0) in d e s t i n a t i o n BL (just as ones in s o u r c e BL are r e p l a c e d by the "then" part). Hence the r e s u l t is as follows: F0=fl,m, 0,1,0 2.All c o n d i t i o n a l i n s t r u c t i o n s in a p r o c e d u r a l d e s c r i p t i o n are a s s u m e d to have the form: if ... then ... else or can be transformed into such a form. 3.EXPRESSION denotes a BL, which describes a specified variable bit. Therefore, variable-oriented operations f r o m HDL d e s c r i p t i o n must be transformed into BL notation for every variable bit. For example: a d d i t i o n of v a r i a b l e s A and B, where the result is a s s i g n e d to A, is e q u i v a l e n t to a set of BLs:
A1 = a l , b l , 0 , l , b l , l , 0 CY = a l , b l , l , 0 , 0 A2 = a 2 , b 2 , C Y , I , 0 , C Y , 0 , I , b 2 , C Y , 0 , 1 , CY,I,0 BLN for all multiplying tab.l.
i t e r a t i v e rules for circuit are given
the in
A set of v a l u e s of all v a r i a b l e s will be c a l l e d the state of the p r o c e s s o r . A set of all i t e r a t i v e rules will be called the I t e r a t i v e F u n c t i o n (ITF) of the p r o c e s s o r . The I t e r a t i v e Function d e s c r i b e s the f u n c t i o n s of the p r o c e s s o r ' s c o m b i n a t i o n a l and c o n t r o l units. The I t e r a t i v e F u n c t i o n can be d e f i n e d as follows: ITF: S(t-l) X IN(t) -> S(t) where S(t) denotes the processor state at time t and IN(t) d e n o t e s the input v a r i a b l e v e c t o r at time t. This means that HDL d e s c r i p t i o n can be m o d e l l e d by a s e q u e n t i a l circuit as g i v e n in Fig.3.
d~nts
Fig.3.Sequential circuit m e n t a t i o n of ITF. 2.4.
Calculation
for
imple-
of a c i r c u i t state
The state of a c i r c u i t at a n y m o m e n t of a p r o c e d u r e e x e c u t i o n can be calculated, by using ITF, till time t=0 is a c h i e v e d . It is a s s u m e d here that the instruction #0 is the first executed i n s t r u c t i o n of the p r o c e d u r e , but a n y other a s s u m p t i o n can be made. The initial state (at time t=0) is assumed as the following: - all output and internal variable bits have the u n d e f i n e d value " U '! •
all phase v a r i a b l e bits are equal to 0, but o n e : F 0 w h i c h is equal to I, - input v a r i a b l e s have v a l u e s a c c o r d i n g to the g i v e n input pattern. N e x t s t a t e s are basis of ITF.
determined
on
the
K. Sapiecha, T. Czichon / Test Generation for Circuits in Procedural HDLs
375
Table i. ...................................................................
Phase variable:
CONDITIONS:
F0=fl,m, 0,1,0 Fl=f8,l,f0,1,0 F2=fl,m,l,0,0 F3=f2,1,0 F4=fT,sc,l,0,f3,1,0 F5=f4,gl,l,0,0 F6=f4,ql,0,l,f5,1,0 FT=f6,1,0 F8=fT,sc,0,1,0
(m=O)=m,O,1 (sc=0)=sc,0,1 (ql=0)=ql,0,1 EXPRESSIONS: (qsObs)=qs,bs,0,l,bs,l,0
(a+b)l=al,bl,O,l,bl,l,O (a+b)2=a2,b2,CY,l,O,CY,O,l,b2, CY,0,I,CY,I,0
(a+b)3=a2,b2,l,CY, l,O,b2,CY, 1,0,0 CY=al,bl,l,0,0 SHR(e,a,g)l=q2,1,0 SHR(e,a,q)2=al,l,0 SHR(e,a,q)3=a2,1,0 SHR(e,a,q)4=e,l,0 SHR(e,a,q)5=0 (sc-l)=sc,0,1 Data variables:
Ai=F3,0,F5,(a+b)i,l,O,F6,SHR(e,a,q)(2+i),l,O,ai,l,O Qi=F2,yi,l,0,F6,SHR(e,a,q)i,l,0,gi,l,0 Bi=F2,xi,l,0,bi,l,0 AS=F3,(qsObs),l,0,as,l,0 M =F0,ST,I,0,FS,0,m,I,0
,i=1,2 ,i=i,2 ,i=1,2
SC=F3,0,F6,(sc-l),l,O,sc,l,O BS=F2,xs,l,0,bs,l,0 QS=F2,ys,l,0,qs,l,0 E =F3,0,F5,(a+b)3,1,0,F6,SHR(e,a,g)5,1,0,e,l,0
Table 2. B2(2)=F2(2),X2,1,0,B2(1),l,0 F2(2)=FI(1),M(1),I,0,0 FI(1)=F0(0),I,FS(0),I,0 F0(0)=I FI(1)=I
(iterative rule) (iterative rule) (iterative rule) (initial state) (after insertion) M(1)=FO(1),ST,I,O,F8(1),O,M(O),I,O (iterative rule) F0(1)=FI(0),M(0),0,1,0 (iterative rule) FI(0)=0 (initial s t a t e ) F0(1)=0 (after insertion) F8(1)=FT(0),SC,0,1,0 (iterative rule) FT(0)=0 (initial state) FS(1)=0 (after insertion)i M(0)=F0(0),ST, I,0,FS(0),0,M(-I),I,0 (iter.rule) F0(0)=I (initial state) I M(0)=ST,I,0 (after insertion) M(1)=ST,I,0 (after insertion)l F2(2)=ST,I,0 (after insertion) B2(1)=F2(1),X2,1,0,B2(0),I,0 (Iterative rule) I F2(1)=FI(0),M(0),I,0,0 (iterative rule) FI(0)=0 (initial state) i F2(1)=0 (after insertion) B2(0)=u (initial state) I B2(1)=u (after insertion) B2(2)=ST,X2,1,0,u (after insertion)l
K. Sapiecha, 7". Czichon / Test Generation for Circuits in Procedural HDLs
376
To illustrate h o w a state bit function is d e r i v e d from ITF, let us c o n s i d e r function B2(2) (i.e. bit B2 at time t=2). In table 2 all steps of B2(2) d e r i v a t i o n are given. In each step an a p p r o p r i a t e BL is s c a n n e d so that variables with u n k n o w n values are discovered. Then BLs for these v a r i a b l e s are s c a n n e d and so on. This p r o c e d u r e is called upon recursively until all wanted v a r i a b l e states are known. Let us remark that the c i r c u i t state for a n y time t is e v a l u a t e d r e c u r s i vely and d e p e n d s on input variable states at times 0,1,...,t-i which m a y v a r y d u r i n g the p r o c e d u r e execution. For simplicity we have assumed that input v a r i a b l e s r e m a i n c o n s t a n t during procedure execution. This corresponds to the model given in fig.4. However, it is not an obligatory a s s u m p t i o n .
Fig.4.
Iterative
TEST
GENERATION
3.
3.1.
Fault
model
of
sequential
Test
circuit
from Fig.3.
2.determination function w h i c h zation function
of fault p r o p a g a t i o n matches the s e n s i t i p r e v i o u s l y derived.
model
Faults d e s c r i b e d at the HDL level, such as a v a r i a b l e single bit stuckat-0 or s t u c k - a t - l , are c o n s i d e r e d . E i t h e r the HDL v a r i a b l e or the phase variable can be faulty. We do not take into a c c o u n t b i t - b r i d g i n g faults but it is p o s s i b l e to extend our considerations to a w i d e r class of faults. The o n l y r e q u i r e m e n t to be met is that the logical values of faulty variables are different in faulty and fault-free circuits. Each v a r i a b l e bit fault is e q u i v a l e n t to a single fault on the external lines of the circuit from fig.2. 3.2.
thods show disadvantages especially visible in c o m p l e x HDL d e s c r i p t i o n s . Each d i f f e r e n t HDL e x p r e s s i o n corresponds to a unique module. Hence, a great v a r i e t y of "cubes" m i g h t have to be created and stored. Both forward and b a c k w a r d t r a c i n g need a lot of h e u r i s t i c s and are time and m e m o r y consuming. On the other hand the nature of BLs s u g g e s t s the a p p l i c a t i o n of a symbol m a n i p u l a t i o n o r i e n t e d test g e n e r a t i o n method. Taking, additionaly, into account the c o n s i d e r e d fault model the choice of the b o o l e a n difference as a tool for test g e n e r a t i o n seems to be the most proper s o l u t i o n in the case discussed. Moreover, d e r i v a t i o n of boolean difference from BLs is very simple [SAP'86]. The m e t h o d which is g o i n g to be presented here consits of two steps: l.determination of fault s e n s i t i z a tion function, and then
generation
principle
It is r e a d i l y seen that a n y modulelevel test g e n a r a t i o n m e t h o d [BRE'76] can be a p p l i e d for a s e q u e n t i a l circuit from Fig.4. However, these me-
In both steps BLs are used for all computations. These are algorithmic. Fault propagation function is obtained by c h a i n i n g fault sensitization function and partial boolean differences along the path from a fault seat to a n y o b s e r v a b l e output. No j u s t i f i c a t i o n step is needed. 3.3.
Fault
sensitization
function
Iteratlve function makes it possible to determine a bit v a r i a b l e as a function of input pattern at any m o m e n t t of p r o c e d u r e execution. It enables fault s e n s i t i z a t i o n f u n c t i o n to be determined. Let us c o n s i d e r variable B2. Using ITF and table 3, w h i c h c o n t a i n s prec a l c u l a t e d intermediate results, we get what follows=
K. Sapiecha, T. Czichon / Test Generation for Circuits in Procedural HDLs
B2(0)=u B2(1)=F2
(initial state) (1),X2,1,0,B2(0),I,0= (iterative rule) =B2(0),I,0= (inserting F2(1)) =u (inserting B2(0)) B2(2)=F2(2),X2,1,0,B2(1),I,0= (iterative rule)
same
377
way as above.
Let us c o n s i d e r fault SC/0. Fault s e n s i t i z a t i o n function is d e r i v e d by calculating v a r i a b l e SC function at consecutive time moments. Results are as follows:
=ST,X2,1,O,B2(1),I,O= (inserting (inserting
=ST,X2,1,0,u
F2(2)) B2(1))
Functions B2(0) and B2(1) are constant and equal to u. This means that no fault of B2 can be s e n s i t i z e d in t=0 and t=l. On the c o n t r a r y B2(2) is a f u n c t i o n of input pattern. Hence fault s e n s i t i z a t i o n could be possible in t=2. Table .
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SSSC/0=ST,YI,0,1,0 3.4.
Let v/c denote a bit variable v s t u c k - a t - c fault. Fault s e n s i t i z a t i o n function Stv/c is d e r i v e d from bit variable f u n c t i o n v(t) a c c o r d i n g to the f o l l o w i n g algorithm: A.If c=l then: l.change each 0 in BL for v(t) onto i, and 2.change each 1 and u in BL for v(t) onto 0. B.If c=0 then: l. c h a n g e each u in BL for v(t) onto 0. for B2/1
S2B2/I=ST,X2,0,1,O for time m o m e n t
t=2.
It is r e a d i l y seen that fault v/c is sensitized in m o m e n t t for given input pattern A if and only if Stv/c(A)=l. Fault s e n s i t i z a t i o n f u n c t i o n can be d e r i v e d for a n y time m o m e n t but usualy the first p o s s i b i l i t y of fault s e n s i t i z a t i o n is tried. Fault sensitization functions control variables and bits of phase variable are d e r i v e d in
1,0=u SC(3)=F3(3),0,F6(3),SC(2),0,I,SC(2), 1,0=ST,0,u SC(4)=F3(4),0,F6(4),SC(3),0,I,SC(3), 1,0=ST,0,u SC(5)=F3(5),0,F6(5),SC(4),0,I,SC(4), 1,0=ST,YI,0,I,u It is seen that fault SC/0 can be s e n s i t i z e d not earlier than at moment t=5. Only at this m o m e n t can input pattern (ST=I,YI=0) occur, which makes SC equal to i. Hence fault s e n s i t i z a t i o n function for SC/0 is as follows:
F2(2)=ST,I,0 F3(1)=F3(2)=F3(4)=F3(5)=F3(6)= =F3(8)=0 F3(3)=ST, I,0 F5(3)=FS(4)=0 F5(5)=ST,YI,I,0,0 F6(1)=F6(2)=F6(3)=F6(4)=0 F6(5)=ST,YI,0,1,0 F6(8)=ST,YI,0,Y2,0,1,0 QI(7)=ST,Y2,1,0,u AI(7)=ST,YI,X2,1,0,0,u A2(7)=ST,0,u BI(7)=ST,XI,I,0,u
function
SC(2)=F3(2),O,F6(2),SC(1),O,I,SC(1),
3.
.
F2(1)=F2(3)=F2(4)=O
Fault s e n s i t i z a t i o n equals:
SC(0)=u SC(1)=F3(1),0,F6(1),SC(0),0,I,SC(0), 1,0=u
for the the
Fault
propagation
function
Fault s e n s i t i z e d has to be p r o p a g a t e d to a n y output variable. It has to be done while the p r o c e d u r e is executed. The principle of p r o p a g a t i o n results from the p r o c e d u r e test model given in Fig.4. S t a r t i n g from the moment when fault v/c is sensitized, the fault p r o p a g a t i o n f u n c t i o n Ptv/c is derived. An algorithm of fault propagation function d e r i v a t i o n w h i c h going to be presented here uses the so-called C a u s e - E f f e c t Table (CET). It enables one to select branches while p r o p a g a tion function is being computed. CET is c r e a t e d c o n c u r r e n t l y with the d e r i v a t i o n of the iterative function and deals with the i n f o r m a t i o n contained in the iterative function only. CET c o n s i s t s of two columns. The left c o l u m n c o n t a i n s all HDL v a r i a b l e s and phase v a r i a b l e - each v a r i a b l e bit in one row. For e v e r y v a r i a b l e v in the left column, variables vl,...,vi, ...,vr in the right column are placed, if an iterative rule for each vi in which v a r i a b l e v is an element holds. With each variable v a so-called o b s e r v a b i l i t y index Ov is associated. The o b s e r v a b i l i t y index is d e f i n e d as follows: l.Ov=0 if v is an output variable, 2.Ov=min(Ovl,...,Ovi,...,Ovr)+l, otherwise.
378
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CET for the m u l t i p l y i n g circuit is shown in tab.4. Output v a r i a b l e s are marked by b o l d - f a c e letters. If a v ar i a b l e is taken in the same clock period in which the resultant is evaluated, it is underlined. Table .
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ICause .
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ST:5 M :4 SC:5
M
F0:5 FI:4 F2:3 F3:3 F4:4 F5:3 F6:3 F7:5 F8:5
FI,M F0,F2 F3,B1.B2.QI.Q2.BS.QSI F4,SC,AStAI,A2,E F5,F6 F6,AIaA21E F7,SC,A1.A2.QI,Q2.E F4,F8 F1,M
XS:2 YS:2 Xi:2 YI:2 QS:I BI:I B2:I CY:I E :i AS:0
BS QS Bi (i=1,2) Qi (1=1,2) BS,AS QS,B8 BI,CY,AI B2,E,A2 E,A2 E,A2 AS
AI:0 A2:0 QI:0
AI,Q2,CY A2,AI,E Q1,FS,F6
M,F0,F2 SC,F4,F8
O2:0 .
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Effect
BS:I
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A so-called Transition Function (TF) is r e l a t e d to each pair c a u s e - e f f e c t (vl-v2) in CET. It is d e f i n e d as b o o l e a n d i f f e r e n c e dv2/dvl. Thus, it d e t e r m i n e s r e q u i r e m e n t s to be met so that the t r a n s i t i o n can occur. Let us c o n s i d e r ct i o n related iterative rule as follows:
the t r a n s i t i o n funto pair B2-A2. The for v a r i a b l e A2 is
A2=F3,0,F5,a2,b2,CY,I,0,CY,0,1, b2,CY,0,I,CY,I,0,F6,e,I,0,a2,1,0 The b o o l e a n d i f f e r e n c e in relation to variable B2 can be derived directly from BL. The result is the following:
dA2/dB2(t)= =F3,0,F5,a2,CY, I , 0 , C Y , 0 , I , F 6 , e , I , 0 , a2,1,0 (sublist for B2=I) OF3,0,FS,a2,CY,0,I,CY,I,0,F6,etl,0, a2,1,0 (sublist for B2=0)
=F3,0,F5,a2,CYsI,I,CY,I,I,F6,e,O,O, a2,0,0 =F3,0,F5,1,0
(mod.2 s u m of values in each column)
A rough of the a l g o r i t h m of fault propagation function derivation is the following: l . D e t e r m i n e lenght im of the longest admissible sensitized path in the procedure. 2.Set t as equal to the moment of fault v/c sensitization. Assume Ptv/c=Stv/c. 3.Put in order a c c o r d i n g to growing observability indexes of all variables vi from the r o w of v in CET. 4.Take next v a r i a b l e vi from the ordered row of v in CET. 5.Set t'=t+D(v,vi), where 0, if vi=vi(v(t)), D(v,vi)= i, if vi=vi(v(t-l)) If t'>im then try next admissible path in the procedure, otherwise determine r e q u i r e m e n t s TF to be met so that the b r a n c h v-vi is chosen in t': TF=dvi/dv(t'). 6.If TF=0 then return to step 4, o t h e r w i s e compute P t ' v / c = P t v / c ^ TF. 7.If Pt'v/c=0 then r e t u r n to step 4, o t h e r w i s e set t=t'. 8.If vi is an output variable (Ovi=0) then Pt'v/c d e t e r m i n e s tests of v/c, otherwise repeat from 3 taking vi as v.
I
To illustrate the a p p l i c a t i o n of CET and t r a n s i t i o n functions in the algorithm given above let us consider fault B2/I. The a l g o r i t h m is e x e c u t e d as follows: l.Set Im=6. 2.Set t=2 and P 2 B 2 / I = S T , X 2 , 0 , 1 , 0 on the basis of fault sensitization function $2B2/I. Take B2 as v. 3 . D e t e r m i n the s e q u e n c e of vi in the row for B2 as f o l l o w s : A 2 , E , B 2 . 4.Take A2 as vi. 5.Set t'=2+i=3. Compute T F = d A 2 / d B 2 ( 3 ) . 6.Since TF=0 then return to step 4. 4.Take E as vi. 5.Set t'=3. Compute T F = d E / d B 2 ( 3 ) . 6.Since TF=0 then return to 4. 4.Take B2 as vi. 5.Set ~ ' = 3 . Compute T F = d B 2 / d b 2 ( 3 ) = =F2(3),0,I=I 6.Since TF<>0 then compute
P3v/c=ST,X2,0,1,O. 7.Since P 3 v / c < > 0 then set t=3. 8.Since OB2<>0 then repeat from 3 taking B2 as v.
K. Sapiecha, 7". Czichon / Test Generation for Circuits in Procedural HDLs
REFERENCES Transitions to t = 4 , t h e n
B2->B2
are
followed
up
4.Take A2 as vi. 5.Set t'=5. C o m p u t e TF=dA2/dB2(5)= =F3(5),0,F5(5),I,0= =ST,Y1,1,0,0. 6.Since TF<>0 then compute P5v/c=ST,X2,0,YI,I,0. 7.Since P 5 v / c < > 0 then set t=5. 8.Since OA2=0 then PSB2/I determines tests of B2/I. In the case c o n s i d e r e d there is only one test: ST=I, X2=0, YI=I. Fault B2/I is d e t e c t e d at v a r i a b l e A2 while t=5. For control and phase v a r i a b l e s the same p r o c e d u r e applies.
4.
CONCLUSIONS
In the paper a n e w m e t h o d for generating tests from p r o c e d u r a l HDL description of a c i r c u i t is given. A processor for e x e c u t i n g a procedure is used as a test model of the circuit c o n s i d e r e d . The p r o c e s s o r ' s functions are d e s c r i b e d by m e a n s of the s o - c a l l e d b i n a r y lists. A b i n a r y list is a c o m p a c t o n e - d i m e n s i o n a l n o t a t i o n to d e s c r i b e "if-clause" structures. B i n a r y lists are of regular s t r u c t u r e w hich makes their s y m b o l i c manipulation easy. The fault model a s s u m e d is a v a r i a b l e bit s t u c k - a t - 0 or stack-at-l. Test generation c o n s i s t s in d e r i v a t i o n of the so-called: - fault s e n s i t i z a t i o n function, and - fault p r o p a g a t i o n function, from b i n a r y lists corresponding to all bits of the variables. All the above m a n i p u l a t i o n s are a l g o r i t h m i c a lly rather simple and c o m p u t a t i o n a l l y not c o m p l e x because of the p r o p e r t i e s of b i n a r y lists. Moreover, they could be e a s i l y i m p l e m e n t e d with the help of such languages as PROLOG. In fault p r o p a g a t i o n f u n c t i o n derivation some k n o w l e d g e of the subject that is the s i g n i f i c a n c e of the procedure and requirements for fault propagation is desired. Necessary data on a p a r t i c u l a r procedure are collected in the so-called CauseEffect Table and used a c c o r d i n g to the knowledge.
BRE'76 - Breuer M . A . , F r i e d m a n A.D. "Diagnosis and Reliable Design of Digital Systems", Computer Science Press,Inc., C a l i f o r n i a 1976. C H U ' 6 5 - Chu Y. "An A l g o l - l i k e Computer Design Language", Comm. ACM-8, pp 607-615, October 1965. HAR'77 - H a r t e n s t e i n R.W. " F u n d a m e n tals of S t r u c t u r e d H a r d w a r e Design. A Design Language Approach at RTL.", N o r t h Holland Publ. Company, Amsterdam 1977. H A R ' 8 5 - H a r t e n s t e i n R.W., W o d t k o A. "Automatic G e n e r a t i o n of Functional Test Patterns from RT Language Source.", Proc.of Intern.Conf E U R O M I C R O 85,Brussels. LEV'82 - Levendel Y.H.,Menon P.R. "Test Generation Algorithms for Computer Hardware Description L a n g u a g e s " , IEEE TC vol C-31, pp 577588, J u l y 1982. L E V ' 8 3 - L e v e n d e l Y . , M e n o n P.R. "The *-algorithm: C r i t i c a l Traces for Functions and CHDL constructs", Proc. 13th ISFTC, pp 90-97, June 1983. MEN'78 M e n o n P.R., Chappel S.G. "Deductive Fault S i m u l a t i o n with Functional Blocks", IEEE TC, vol C-27, pp 689-695, Aug 1978 PIL'75 - Piloty R. "Segmentation C o n s t r u c t s for RTS III, a Computer Hardware Description Language based on CDL", Techn. H o c h s c h u l e Darmstadt, RO 75/4, Marz 1975. SAP'82 - Sapiecha K.,Walczak K. "Deductive Fault S i m u l a t i o n from F u n c t i o n a l D e s c r i p t i o n of Logic Circuits", Proc. 5th Conf. FTSD, pp 6774, K a t o w i c e 82. SAP'84 - Sapiecha K.,Czichon T. "Microprocessor Test Method", Proc. of I n t e r n . C o n f . M I C R O S Y S T E M 84, Bratislava,1984, pp.187-194. SAP'86 - Sapiecha K.,Czichon T. "Binary List Calculus", I n t . R e p o r t of II PW, Warsaw, 1986. SEL'68 - Sellers F.F. et al "Analysing Errors with the B o o l e a n D i f f e r e nce", IEEE TC, J u l y 1968. SHEN'84 - Shen L.,Su S.Y.H. "VLSI Functional Testing Using Critical Path Traces at a H a r d w a r e D e s c r i p t i o n Language Level", Proc. Fehlertoleriende Rechnensysteme, pp 364379, Bonn, S e p t e m b e r 1984. SU'82 - Su S.Y.H.,Hsieh Y. "Testing Functional Faults in Digital S y s t e m D e s c r i b e d by R e g i s t e r T r a n s f e r Language", Jour. of Digital Systems, vol VI, Nr 2/3, 1982.
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TEST G E N E R A T I O N FOR C I R C U I T S D E S C R I B E D H A R D W A R E D E S C R I P T I O N L A N G U A G E S (HDLs)
K.Sapiecha,T.Czichon, Institute W a r s a w U n i v e r s i t y of Technology,
IN P R O C E D U R A L
of C o m p u t e r Science, 00-665 WARSAW, P O L A N D
In the paper a n e w m e t h o d for g e n e r a t i n g tests f r o m p r o c e d u r a l HDL description of a c i r c u i t is given. A processor for executing a procedure is used as a test model of the circuit considered. The p r o c e s s o r ' s functions are d e s c r i b e d by means of the s o - c a l l e d b i n a r y lists. Binary lists are of regular s t r u c t u r e w h i c h makes their s y m b o l i c m a n i p u l a t i o n easy. Test g e n e r a t i o n c o n s i s t s in d e r i v a t i o n of the s o - c a l l e d fault sensit i z a t i o n f u n c t i o n and fault p r o p a g a t i o n function from b i n a r y lists c o r r e s p o n d i n g to all bits of the variables. All the above m a n i p u l a tions could be e a s i l y i m p l e m e n t e d with the help of such languages as PROLOG.
i.
INTRODUCTION
HDLs are useful as input media of h ardw a r e compilers and simulators, as a concise high level n o t a t i o n tool for d e s i g n i n g , teaching, and other forms of c o m m u n i c a t i o n . It seems to be d e s i r e d that HDL c i r c u i t description should also be convenient as input data for test p a t t e r n generation systems. Two kinds of Hardware Description Languages are distinguished: nonp r o c e d u r a l and p r o c e d u r a l ones. Nonprocedural languages make possible s t r u c t u r a l d e s c r i p t i o n of digital circuits. Procedural languages make possi b l e their functional description, particularly of microprocessors and m i c r o p r o g r a m m e d circuits. For a c i r c u i t d e s c r i p t i o n g i v e n in a non-procedural language, test generation m e t h o d s have already been developed [LEV'82 and '83, HAR'85]. A few a p p r o a c h e s to test generation based on a p r o c e d u r a l HDL description have also been developed. The first one, p r e s e n t e d in [SU'82], is based on Data Graph and extended D-algebra. Test generation for a given fault consists in propagating D-cube along a path (selected by means of Data Graph) from command point to observation point. The second approach, presented in [SHEN'84], is based on critical path tracing. It is assumed here, that HDL i n s t r u c t i o n s describe combinational modules, for which c r i t i c a l cubes (C-cubes) can
be calculated. A HDL p r o g r a m determines the paths between these modules. Test generation consists in c a l c u l a t i n g the c r i t i c a l path from the last module (the last HDL instruction) to the first one. In the area of test g e n e r a t i o n from procedural circuit description there are two e s s e n t i a l problems that have not found s a t i s f a c t o r y solutions, so far. The first one concerns control v a r i a b l e testing. Test generation for control variable faults is complex. Control variables are not observable after assignments. T h e y cannot be inserted as part of the o p e r a t i o n a l module in c r i t i c a l path tracing. Therefore, it is a s s u m e d in methods which have been d e v e l o p e d so far, that control v a r i a b l e s and control paths are fault-free. Control variable faults in m o d e r n VLSI circuits cannot be neglected. A function of a circuit is more and more complicated, and every "data variable" can be used as a control v a r i a b l e in some HDL instructions. The other p r o b l e m is a s s o c i a t e d with analysis of actual HDL programs. The recent methods are useful for HDL programs, in w h i c h conditions for obtaining a required instruction s e q u e n c e are easy to formulate. There are no s o l u t i o n s for c o n d i t i o nal jumps and loops with c o n d i t i o n a l exits. A test g e n e r a t i o n m e t h o d which s o l v e s these problems is necessary. Each HDL program, w h a t e v e r its structure,
372
K. Sapiecha, T. Czichon / Test Generation for Circuits in Procedural HDLs
should be a l g o r i t h m i c a l l y transformed into a shape, which is convenient for TPG system. Moreover, th~ method should work for c o m p l e x HDL descriptions, and for both data and control v a r i a b l e faults. In the paper such a test pattern generation method is presented. In s e c t i o n 2 a n e w n o t a t i o n for functional c i r c u i t d e s c r i p t i o n is given. It is called B i n a r y List N o t a t i o n (BLN). A new method of generating tests whi c h make use of this notation is p r e s e n t e d in s e c t i o n 3. The method is based on the c o n c e p t of b o o l e a n difference and is a d o p t e d for implementation with the help of a symbol m a n i p u l a t i o n technique.
2.
2.1.
CIRCUIT DESCRIPTION F A U L T MODEL Circuit
binational back lines.
feed-
AND C I R C U I T
description Fig.l.
It is assumed, that all data concerning a circuit is given in the form of a p r o c e d u r a l d e s c r i p t i o n . The d e s c r i p t i o n is a p r o c e d u r e with a head and a body. The former describes memory elements and inputoutput pins of the circuit. The latter describes connections between the elements, data operations performed in the circuit and sequencing of HDL instructions. As an example we shall consider a 2-bit m u l t i p l y i n g circuit. Using R T L - l i k e language its function may be described as follows (SU'82): INPUT: X ( X 2 : X I ) , Y ( Y 2 : Y I ) , X S , Y S , S T OUTPUT: A ( A 2 : A I ) , Q ( Q 2 : Q I ) , A S REGISTER: M,SC, B ( B 2 : B I ) , B S , Q S , E /0/ M=ST /I/ if M=0 then goto 0, else goto 2 /2/ B = X , B S = X S , Q = Y , Q S = Y S /3/ AS=QS • BS A=00, E=0, SC=0 /4/ if QI=0 then goto 6, else goto 5 /5/ E . A = A + B /6/ E . A . Q = s h r ( E . A . Q ) SC=not(SC) /7/ if SC=0 then goto 8, else goto 4 /8/ M=0, goto i. Based on this d e s c r i p t i o n a processor is p r o p o s e d as a test model of the circuit considered. 2.2.
block and external
Processor
The p r o c e s s o r c o n s i s t s of two units (fig.l): a control unit and an operational unit. Each c o n s i s t s of a com-
Processor.
To d e s c r i b e a function of the control unit, an extra n-bit variable, c a l l e d the phase v a r i a b l e (F), is introduced. It is assumed here, that HDL instructions as well as bits of the phase v a r i a b l e are n u m b e r e d by c o n s e cutive integers: 0,1,...,n. Fi is equal to 1 if and only if HDL number instruction being currently executed is equal to i. Phase v a r i a b l e can be u n d e r s t o o d as a m i c r o p r o g r a m m counter in a microprogrammed circuit. The processor is c o n t r o l l e d by a dual-step clock. Step one involves c a l c u l a t i o n s of the next value of the phase variable. Step two involves calculations of data and control variables. A processor for p e r f o r m i n g the 2-bit m u l t i p l i c a t i o n procedure is shown in fig.2. Actually in test g e n e r a t i o n there is no need to create a particular processor. It is used here m a i n l y to explain the c o n c e p t of iterative function which is going to be introduced later on and which is e s s e n t i a l for the test g e n e r a t i o n method which we deal with. 2.3.
Iterative
Function
Control unit functions and operational unit functions can be described by a set of nested if-clause structures. For e x a m p l e , l e t us c o n s i d e r the second bit of variable A (A2) of the
K. Sapiecha, T. Czichon / Test Generation for Circuits in Procedural HDLs
373
a) M,SC,QI
===>I
Control
I I====> I
i f=(f0,...,fS)=======>]
unit I
F=(F0,FI,...,FS)
I
b) F=(F0,...,FS) ===>I ] bs,qs,as i i OperationalJ a,b,e,q } . . . . . . . >I J.... m, sc i i unit I ST, X S , Y S , X , Y .... >I I
BS,QS,AS
=>A,B,E,Q M,SC
Fig.2. C o n t r o l unit a) a n d o p e r a t i o n a l unit b) of a p r o c e s s o r for performing of the 2 - b i t m u l t i p l i c a t i o n procedure (non-capital letters denote previous state variables]. examples BLN.
The above sequence of conditional assignments c a n be d e s c r i b e d b y the following if-clause structure:
B e l o w the b i n a r y list of A2 the ranges of "then" and "else" p a r t s for v a r i a b l e s F 3 , F 5 and F6 are m a r k e d .
A2
2.Let us c o n s i d e r bit F4 of the phase variable. Its n e x t s t a t e func t i o n is d e t e r m i n e d as f o l l o w s : - if p r e v i o u s i n s t r u c t i o n had n u m b e r 3, t h e n F4=I, else: if p r e v i o u s i n s t r u c t i o n had n u m b e r 7, then if SC was not e q u a l to 0 t h e n F4=I, else:
= if F3 t h e n 0, e l s e if F5 t h e n if a 2 O b 2 0 C Y else
if F6
then else
then else if ql then else if a2 t h e n else
i, 0; I, 0; i, 0.
It will be c a l l e d the I T E R A T I V E RULE of calculation of the next state f u n c t i o n of v a r i a b l e A2. Non-capital letters denote previous state variables, and e x t r a v a r i a b l e CY denotes a carry coming from the less s i g n i f i c a n t bit w h i l e addition of A a n d B is p e r f o r m e d .
explain
the m a i n
circuit discussed. The next state function of A2 is d e t e r m i n e d as follows: - if p r e s e n t i n s t r u c t i o n has number 3, t h e n A2 is e q u a l to 0, else: - if p r e s e n t i n s t r u c t i o n has n u m b e r 5 then the v a l u e of A2 is e q u a l to the s e c o n d bit of the s u m of A+B, else: - if p r e s e n t i n s t r u c t i o n has number 6, t h e n A2 is e q u a l to the previous v a l u e of E, else: - the v a l u e of A2 r e m a i n s u n c h a n g e d .
of
l.ln BLN the a b o v e iterative rule for variable A2 is expressed as follows: A2 =
=F3,0,F5,a20b20CY, IjO,F6,e,I,O,a2,1,O . . . . . . . . . . . . else . . . . . . . . . . . . . . . . . the~ .... t h e n . . . . . . . . . else . . . . . . -then- -else-
-
F4=0.
The if-clause follows: F4
structure
= if f3 t h e n i, else if f7 t h e n else
Iterative rules as g i v e n a b o v e are not convenient for processing. Of course, t h e y c a n be t r a n s f o r m e d into boolean expresions [LEV'82]. H o w e v e r , expresions are e q u a l l y inconvenient for processing, no m a t t e r w h i c h w a y of p r o c e s s i n g , n u m e r i c or symbolic, is c h o s e n . T h e r e f o r e , a n e w n o t a t i o n , called Binary List Notation is applied. A formal d e s c r i p t i o n of BLN calculus is g i v e n in [SAP'86]. The f o l l o w i n g
idea
The a b o v e in BLN as F4
iterative follows:
rule
for F4
is as
if sc then else 0.
I, 0;
is e x p r e s s e d
= f3,l,fT,sc,l,0,0 t h e n . . . . else .... -then- -else
In this tional cribed (BLs).
w a y f u n c t i o n s of b o t h operaand c o n t r o l u n i t s can b e d e s by a set of binary lists
374
K. Sapiecha, T. Czichon / Test Generation for Circuits in Procedural HDLs
It s h o u l d be e m p h a s i z e d that all can be derived directly from description. An algorithm of d e r i v a t i o n is as follows:
BLs HDL the
A.For every phase v a r i a b l e bit Fi: l. If (i-l)th i n s t r u c t i o n is a jump instruction or i=0 t h e n generate an initial list: L = 0 else g e n e r a t e an initial list: L = fi-l,l,0 2.For e v e r y u n c o n d i t i o n a l Jump: /j/ g o t o i g e n e r a t e a list: L = fj,l,L 3.For e v e r y c o n d i t i o n a l jump: /j/ if C O N D I T I O N then g o t o i else ... g e n e r a t e a list: L=fj,(CONDITION),I,0,L 4.For e v e r y c o n d i t i o n a l jump: /J/ if C O N D I T I O N then g o t o ... else goto i g e n e r a t e a list: L=fj,(CONDITION),0,I,L 5 . I n s e r t all BLs for C O N D I T I O N S into list L. B.For e v e r y d a t a v a r i a b l e bit Vi: l.Generate the initial list: L = vi,l,0 2.For e v e r y a s s i g n m e n t : /j/ Vi = EXPRESSION g e n e r a t e a list: L = Fj,(EXPRESSION),I,0,L 3.Insert all BLs for EXPRESSIONS into list L. Remarks: l.The insertion of CONDITIONs and E X P R E S S I O N s is p e r f o r m e d a c c o r d i n g to the s i m p l e a l g o r i t h m here introduced with the help of an example.As an example let us c o n s i d e r expression (m=0) (see tab.l), w h i c h is inserted into i t e r a t i v e rule for F0. After execution of steps A . I - A . 4 of the algorithm the f o l l o w i n g BL is obtained: F0=fl,(m=0),l,0,0. Inserting e x p r e s s i o n (m=0), its zeros in s o u r c e BL are r e p l a s e d by the "else" part of (m=0) in d e s t i n a t i o n BL (just as ones in s o u r c e BL are r e p l a c e d by the "then" part). Hence the r e s u l t is as follows: F0=fl,m, 0,1,0 2.All c o n d i t i o n a l i n s t r u c t i o n s in a p r o c e d u r a l d e s c r i p t i o n are a s s u m e d to have the form: if ... then ... else or can be transformed into such a form. 3.EXPRESSION denotes a BL, which describes a specified variable bit. Therefore, variable-oriented operations f r o m HDL d e s c r i p t i o n must be transformed into BL notation for every variable bit. For example: a d d i t i o n of v a r i a b l e s A and B, where the result is a s s i g n e d to A, is e q u i v a l e n t to a set of BLs:
A1 = a l , b l , 0 , l , b l , l , 0 CY = a l , b l , l , 0 , 0 A2 = a 2 , b 2 , C Y , I , 0 , C Y , 0 , I , b 2 , C Y , 0 , 1 , CY,I,0 BLN for all multiplying tab.l.
i t e r a t i v e rules for circuit are given
the in
A set of v a l u e s of all v a r i a b l e s will be c a l l e d the state of the p r o c e s s o r . A set of all i t e r a t i v e rules will be called the I t e r a t i v e F u n c t i o n (ITF) of the p r o c e s s o r . The I t e r a t i v e Function d e s c r i b e s the f u n c t i o n s of the p r o c e s s o r ' s c o m b i n a t i o n a l and c o n t r o l units. The I t e r a t i v e F u n c t i o n can be d e f i n e d as follows: ITF: S(t-l) X IN(t) -> S(t) where S(t) denotes the processor state at time t and IN(t) d e n o t e s the input v a r i a b l e v e c t o r at time t. This means that HDL d e s c r i p t i o n can be m o d e l l e d by a s e q u e n t i a l circuit as g i v e n in Fig.3.
d~nts
Fig.3.Sequential circuit m e n t a t i o n of ITF. 2.4.
Calculation
for
imple-
of a c i r c u i t state
The state of a c i r c u i t at a n y m o m e n t of a p r o c e d u r e e x e c u t i o n can be calculated, by using ITF, till time t=0 is a c h i e v e d . It is a s s u m e d here that the instruction #0 is the first executed i n s t r u c t i o n of the p r o c e d u r e , but a n y other a s s u m p t i o n can be made. The initial state (at time t=0) is assumed as the following: - all output and internal variable bits have the u n d e f i n e d value " U '! •
all phase v a r i a b l e bits are equal to 0, but o n e : F 0 w h i c h is equal to I, - input v a r i a b l e s have v a l u e s a c c o r d i n g to the g i v e n input pattern. N e x t s t a t e s are basis of ITF.
determined
on
the
K. Sapiecha, T. Czichon / Test Generation for Circuits in Procedural HDLs
375
Table i. ...................................................................
Phase variable:
CONDITIONS:
F0=fl,m, 0,1,0 Fl=f8,l,f0,1,0 F2=fl,m,l,0,0 F3=f2,1,0 F4=fT,sc,l,0,f3,1,0 F5=f4,gl,l,0,0 F6=f4,ql,0,l,f5,1,0 FT=f6,1,0 F8=fT,sc,0,1,0
(m=O)=m,O,1 (sc=0)=sc,0,1 (ql=0)=ql,0,1 EXPRESSIONS: (qsObs)=qs,bs,0,l,bs,l,0
(a+b)l=al,bl,O,l,bl,l,O (a+b)2=a2,b2,CY,l,O,CY,O,l,b2, CY,0,I,CY,I,0
(a+b)3=a2,b2,l,CY, l,O,b2,CY, 1,0,0 CY=al,bl,l,0,0 SHR(e,a,g)l=q2,1,0 SHR(e,a,q)2=al,l,0 SHR(e,a,q)3=a2,1,0 SHR(e,a,q)4=e,l,0 SHR(e,a,q)5=0 (sc-l)=sc,0,1 Data variables:
Ai=F3,0,F5,(a+b)i,l,O,F6,SHR(e,a,q)(2+i),l,O,ai,l,O Qi=F2,yi,l,0,F6,SHR(e,a,q)i,l,0,gi,l,0 Bi=F2,xi,l,0,bi,l,0 AS=F3,(qsObs),l,0,as,l,0 M =F0,ST,I,0,FS,0,m,I,0
,i=1,2 ,i=i,2 ,i=1,2
SC=F3,0,F6,(sc-l),l,O,sc,l,O BS=F2,xs,l,0,bs,l,0 QS=F2,ys,l,0,qs,l,0 E =F3,0,F5,(a+b)3,1,0,F6,SHR(e,a,g)5,1,0,e,l,0
Table 2. B2(2)=F2(2),X2,1,0,B2(1),l,0 F2(2)=FI(1),M(1),I,0,0 FI(1)=F0(0),I,FS(0),I,0 F0(0)=I FI(1)=I
(iterative rule) (iterative rule) (iterative rule) (initial state) (after insertion) M(1)=FO(1),ST,I,O,F8(1),O,M(O),I,O (iterative rule) F0(1)=FI(0),M(0),0,1,0 (iterative rule) FI(0)=0 (initial s t a t e ) F0(1)=0 (after insertion) F8(1)=FT(0),SC,0,1,0 (iterative rule) FT(0)=0 (initial state) FS(1)=0 (after insertion)i M(0)=F0(0),ST, I,0,FS(0),0,M(-I),I,0 (iter.rule) F0(0)=I (initial state) I M(0)=ST,I,0 (after insertion) M(1)=ST,I,0 (after insertion)l F2(2)=ST,I,0 (after insertion) B2(1)=F2(1),X2,1,0,B2(0),I,0 (Iterative rule) I F2(1)=FI(0),M(0),I,0,0 (iterative rule) FI(0)=0 (initial state) i F2(1)=0 (after insertion) B2(0)=u (initial state) I B2(1)=u (after insertion) B2(2)=ST,X2,1,0,u (after insertion)l
K. Sapiecha, 7". Czichon / Test Generation for Circuits in Procedural HDLs
376
To illustrate h o w a state bit function is d e r i v e d from ITF, let us c o n s i d e r function B2(2) (i.e. bit B2 at time t=2). In table 2 all steps of B2(2) d e r i v a t i o n are given. In each step an a p p r o p r i a t e BL is s c a n n e d so that variables with u n k n o w n values are discovered. Then BLs for these v a r i a b l e s are s c a n n e d and so on. This p r o c e d u r e is called upon recursively until all wanted v a r i a b l e states are known. Let us remark that the c i r c u i t state for a n y time t is e v a l u a t e d r e c u r s i vely and d e p e n d s on input variable states at times 0,1,...,t-i which m a y v a r y d u r i n g the p r o c e d u r e execution. For simplicity we have assumed that input v a r i a b l e s r e m a i n c o n s t a n t during procedure execution. This corresponds to the model given in fig.4. However, it is not an obligatory a s s u m p t i o n .
Fig.4.
Iterative
TEST
GENERATION
3.
3.1.
Fault
model
of
sequential
Test
circuit
from Fig.3.
2.determination function w h i c h zation function
of fault p r o p a g a t i o n matches the s e n s i t i p r e v i o u s l y derived.
model
Faults d e s c r i b e d at the HDL level, such as a v a r i a b l e single bit stuckat-0 or s t u c k - a t - l , are c o n s i d e r e d . E i t h e r the HDL v a r i a b l e or the phase variable can be faulty. We do not take into a c c o u n t b i t - b r i d g i n g faults but it is p o s s i b l e to extend our considerations to a w i d e r class of faults. The o n l y r e q u i r e m e n t to be met is that the logical values of faulty variables are different in faulty and fault-free circuits. Each v a r i a b l e bit fault is e q u i v a l e n t to a single fault on the external lines of the circuit from fig.2. 3.2.
thods show disadvantages especially visible in c o m p l e x HDL d e s c r i p t i o n s . Each d i f f e r e n t HDL e x p r e s s i o n corresponds to a unique module. Hence, a great v a r i e t y of "cubes" m i g h t have to be created and stored. Both forward and b a c k w a r d t r a c i n g need a lot of h e u r i s t i c s and are time and m e m o r y consuming. On the other hand the nature of BLs s u g g e s t s the a p p l i c a t i o n of a symbol m a n i p u l a t i o n o r i e n t e d test g e n e r a t i o n method. Taking, additionaly, into account the c o n s i d e r e d fault model the choice of the b o o l e a n difference as a tool for test g e n e r a t i o n seems to be the most proper s o l u t i o n in the case discussed. Moreover, d e r i v a t i o n of boolean difference from BLs is very simple [SAP'86]. The m e t h o d which is g o i n g to be presented here consits of two steps: l.determination of fault s e n s i t i z a tion function, and then
generation
principle
It is r e a d i l y seen that a n y modulelevel test g e n a r a t i o n m e t h o d [BRE'76] can be a p p l i e d for a s e q u e n t i a l circuit from Fig.4. However, these me-
In both steps BLs are used for all computations. These are algorithmic. Fault propagation function is obtained by c h a i n i n g fault sensitization function and partial boolean differences along the path from a fault seat to a n y o b s e r v a b l e output. No j u s t i f i c a t i o n step is needed. 3.3.
Fault
sensitization
function
Iteratlve function makes it possible to determine a bit v a r i a b l e as a function of input pattern at any m o m e n t t of p r o c e d u r e execution. It enables fault s e n s i t i z a t i o n f u n c t i o n to be determined. Let us c o n s i d e r variable B2. Using ITF and table 3, w h i c h c o n t a i n s prec a l c u l a t e d intermediate results, we get what follows=
K. Sapiecha, T. Czichon / Test Generation for Circuits in Procedural HDLs
B2(0)=u B2(1)=F2
(initial state) (1),X2,1,0,B2(0),I,0= (iterative rule) =B2(0),I,0= (inserting F2(1)) =u (inserting B2(0)) B2(2)=F2(2),X2,1,0,B2(1),I,0= (iterative rule)
same
377
way as above.
Let us c o n s i d e r fault SC/0. Fault s e n s i t i z a t i o n function is d e r i v e d by calculating v a r i a b l e SC function at consecutive time moments. Results are as follows:
=ST,X2,1,O,B2(1),I,O= (inserting (inserting
=ST,X2,1,0,u
F2(2)) B2(1))
Functions B2(0) and B2(1) are constant and equal to u. This means that no fault of B2 can be s e n s i t i z e d in t=0 and t=l. On the c o n t r a r y B2(2) is a f u n c t i o n of input pattern. Hence fault s e n s i t i z a t i o n could be possible in t=2. Table .
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SSSC/0=ST,YI,0,1,0 3.4.
Let v/c denote a bit variable v s t u c k - a t - c fault. Fault s e n s i t i z a t i o n function Stv/c is d e r i v e d from bit variable f u n c t i o n v(t) a c c o r d i n g to the f o l l o w i n g algorithm: A.If c=l then: l.change each 0 in BL for v(t) onto i, and 2.change each 1 and u in BL for v(t) onto 0. B.If c=0 then: l. c h a n g e each u in BL for v(t) onto 0. for B2/1
S2B2/I=ST,X2,0,1,O for time m o m e n t
t=2.
It is r e a d i l y seen that fault v/c is sensitized in m o m e n t t for given input pattern A if and only if Stv/c(A)=l. Fault s e n s i t i z a t i o n f u n c t i o n can be d e r i v e d for a n y time m o m e n t but usualy the first p o s s i b i l i t y of fault s e n s i t i z a t i o n is tried. Fault sensitization functions control variables and bits of phase variable are d e r i v e d in
1,0=u SC(3)=F3(3),0,F6(3),SC(2),0,I,SC(2), 1,0=ST,0,u SC(4)=F3(4),0,F6(4),SC(3),0,I,SC(3), 1,0=ST,0,u SC(5)=F3(5),0,F6(5),SC(4),0,I,SC(4), 1,0=ST,YI,0,I,u It is seen that fault SC/0 can be s e n s i t i z e d not earlier than at moment t=5. Only at this m o m e n t can input pattern (ST=I,YI=0) occur, which makes SC equal to i. Hence fault s e n s i t i z a t i o n function for SC/0 is as follows:
F2(2)=ST,I,0 F3(1)=F3(2)=F3(4)=F3(5)=F3(6)= =F3(8)=0 F3(3)=ST, I,0 F5(3)=FS(4)=0 F5(5)=ST,YI,I,0,0 F6(1)=F6(2)=F6(3)=F6(4)=0 F6(5)=ST,YI,0,1,0 F6(8)=ST,YI,0,Y2,0,1,0 QI(7)=ST,Y2,1,0,u AI(7)=ST,YI,X2,1,0,0,u A2(7)=ST,0,u BI(7)=ST,XI,I,0,u
function
SC(2)=F3(2),O,F6(2),SC(1),O,I,SC(1),
3.
.
F2(1)=F2(3)=F2(4)=O
Fault s e n s i t i z a t i o n equals:
SC(0)=u SC(1)=F3(1),0,F6(1),SC(0),0,I,SC(0), 1,0=u
for the the
Fault
propagation
function
Fault s e n s i t i z e d has to be p r o p a g a t e d to a n y output variable. It has to be done while the p r o c e d u r e is executed. The principle of p r o p a g a t i o n results from the p r o c e d u r e test model given in Fig.4. S t a r t i n g from the moment when fault v/c is sensitized, the fault p r o p a g a t i o n f u n c t i o n Ptv/c is derived. An algorithm of fault propagation function d e r i v a t i o n w h i c h going to be presented here uses the so-called C a u s e - E f f e c t Table (CET). It enables one to select branches while p r o p a g a tion function is being computed. CET is c r e a t e d c o n c u r r e n t l y with the d e r i v a t i o n of the iterative function and deals with the i n f o r m a t i o n contained in the iterative function only. CET c o n s i s t s of two columns. The left c o l u m n c o n t a i n s all HDL v a r i a b l e s and phase v a r i a b l e - each v a r i a b l e bit in one row. For e v e r y v a r i a b l e v in the left column, variables vl,...,vi, ...,vr in the right column are placed, if an iterative rule for each vi in which v a r i a b l e v is an element holds. With each variable v a so-called o b s e r v a b i l i t y index Ov is associated. The o b s e r v a b i l i t y index is d e f i n e d as follows: l.Ov=0 if v is an output variable, 2.Ov=min(Ovl,...,Ovi,...,Ovr)+l, otherwise.
378
K. Sapiecha, T. Czichon / Test Generation for Circuits in Procedural HDLs
CET for the m u l t i p l y i n g circuit is shown in tab.4. Output v a r i a b l e s are marked by b o l d - f a c e letters. If a v ar i a b l e is taken in the same clock period in which the resultant is evaluated, it is underlined. Table .
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I
ICause .
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i
ST:5 M :4 SC:5
M
F0:5 FI:4 F2:3 F3:3 F4:4 F5:3 F6:3 F7:5 F8:5
FI,M F0,F2 F3,B1.B2.QI.Q2.BS.QSI F4,SC,AStAI,A2,E F5,F6 F6,AIaA21E F7,SC,A1.A2.QI,Q2.E F4,F8 F1,M
XS:2 YS:2 Xi:2 YI:2 QS:I BI:I B2:I CY:I E :i AS:0
BS QS Bi (i=1,2) Qi (1=1,2) BS,AS QS,B8 BI,CY,AI B2,E,A2 E,A2 E,A2 AS
AI:0 A2:0 QI:0
AI,Q2,CY A2,AI,E Q1,FS,F6
M,F0,F2 SC,F4,F8
O2:0 .
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Effect
BS:I
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02,01 .
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A so-called Transition Function (TF) is r e l a t e d to each pair c a u s e - e f f e c t (vl-v2) in CET. It is d e f i n e d as b o o l e a n d i f f e r e n c e dv2/dvl. Thus, it d e t e r m i n e s r e q u i r e m e n t s to be met so that the t r a n s i t i o n can occur. Let us c o n s i d e r ct i o n related iterative rule as follows:
the t r a n s i t i o n funto pair B2-A2. The for v a r i a b l e A2 is
A2=F3,0,F5,a2,b2,CY,I,0,CY,0,1, b2,CY,0,I,CY,I,0,F6,e,I,0,a2,1,0 The b o o l e a n d i f f e r e n c e in relation to variable B2 can be derived directly from BL. The result is the following:
dA2/dB2(t)= =F3,0,F5,a2,CY, I , 0 , C Y , 0 , I , F 6 , e , I , 0 , a2,1,0 (sublist for B2=I) OF3,0,FS,a2,CY,0,I,CY,I,0,F6,etl,0, a2,1,0 (sublist for B2=0)
=F3,0,F5,a2,CYsI,I,CY,I,I,F6,e,O,O, a2,0,0 =F3,0,F5,1,0
(mod.2 s u m of values in each column)
A rough of the a l g o r i t h m of fault propagation function derivation is the following: l . D e t e r m i n e lenght im of the longest admissible sensitized path in the procedure. 2.Set t as equal to the moment of fault v/c sensitization. Assume Ptv/c=Stv/c. 3.Put in order a c c o r d i n g to growing observability indexes of all variables vi from the r o w of v in CET. 4.Take next v a r i a b l e vi from the ordered row of v in CET. 5.Set t'=t+D(v,vi), where 0, if vi=vi(v(t)), D(v,vi)= i, if vi=vi(v(t-l)) If t'>im then try next admissible path in the procedure, otherwise determine r e q u i r e m e n t s TF to be met so that the b r a n c h v-vi is chosen in t': TF=dvi/dv(t'). 6.If TF=0 then return to step 4, o t h e r w i s e compute P t ' v / c = P t v / c ^ TF. 7.If Pt'v/c=0 then r e t u r n to step 4, o t h e r w i s e set t=t'. 8.If vi is an output variable (Ovi=0) then Pt'v/c d e t e r m i n e s tests of v/c, otherwise repeat from 3 taking vi as v.
I
To illustrate the a p p l i c a t i o n of CET and t r a n s i t i o n functions in the algorithm given above let us consider fault B2/I. The a l g o r i t h m is e x e c u t e d as follows: l.Set Im=6. 2.Set t=2 and P 2 B 2 / I = S T , X 2 , 0 , 1 , 0 on the basis of fault sensitization function $2B2/I. Take B2 as v. 3 . D e t e r m i n the s e q u e n c e of vi in the row for B2 as f o l l o w s : A 2 , E , B 2 . 4.Take A2 as vi. 5.Set t'=2+i=3. Compute T F = d A 2 / d B 2 ( 3 ) . 6.Since TF=0 then return to step 4. 4.Take E as vi. 5.Set t'=3. Compute T F = d E / d B 2 ( 3 ) . 6.Since TF=0 then return to 4. 4.Take B2 as vi. 5.Set ~ ' = 3 . Compute T F = d B 2 / d b 2 ( 3 ) = =F2(3),0,I=I 6.Since TF<>0 then compute
P3v/c=ST,X2,0,1,O. 7.Since P 3 v / c < > 0 then set t=3. 8.Since OB2<>0 then repeat from 3 taking B2 as v.
K. Sapiecha, 7". Czichon / Test Generation for Circuits in Procedural HDLs
REFERENCES Transitions to t = 4 , t h e n
B2->B2
are
followed
up
4.Take A2 as vi. 5.Set t'=5. C o m p u t e TF=dA2/dB2(5)= =F3(5),0,F5(5),I,0= =ST,Y1,1,0,0. 6.Since TF<>0 then compute P5v/c=ST,X2,0,YI,I,0. 7.Since P 5 v / c < > 0 then set t=5. 8.Since OA2=0 then PSB2/I determines tests of B2/I. In the case c o n s i d e r e d there is only one test: ST=I, X2=0, YI=I. Fault B2/I is d e t e c t e d at v a r i a b l e A2 while t=5. For control and phase v a r i a b l e s the same p r o c e d u r e applies.
4.
CONCLUSIONS
In the paper a n e w m e t h o d for generating tests from p r o c e d u r a l HDL description of a c i r c u i t is given. A processor for e x e c u t i n g a procedure is used as a test model of the circuit c o n s i d e r e d . The p r o c e s s o r ' s functions are d e s c r i b e d by m e a n s of the s o - c a l l e d b i n a r y lists. A b i n a r y list is a c o m p a c t o n e - d i m e n s i o n a l n o t a t i o n to d e s c r i b e "if-clause" structures. B i n a r y lists are of regular s t r u c t u r e w hich makes their s y m b o l i c manipulation easy. The fault model a s s u m e d is a v a r i a b l e bit s t u c k - a t - 0 or stack-at-l. Test generation c o n s i s t s in d e r i v a t i o n of the so-called: - fault s e n s i t i z a t i o n function, and - fault p r o p a g a t i o n function, from b i n a r y lists corresponding to all bits of the variables. All the above m a n i p u l a t i o n s are a l g o r i t h m i c a lly rather simple and c o m p u t a t i o n a l l y not c o m p l e x because of the p r o p e r t i e s of b i n a r y lists. Moreover, they could be e a s i l y i m p l e m e n t e d with the help of such languages as PROLOG. In fault p r o p a g a t i o n f u n c t i o n derivation some k n o w l e d g e of the subject that is the s i g n i f i c a n c e of the procedure and requirements for fault propagation is desired. Necessary data on a p a r t i c u l a r procedure are collected in the so-called CauseEffect Table and used a c c o r d i n g to the knowledge.
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