The evolving role of defects and contamination in semiconductor manufacturing

Microelectronics Joumal, 24 (1993) 4

The Evolving Role of Defects and Contamination in Semiconductor Manufacturing Harold G. Parks, Associate Professor and Director of the Arizona Sematech Center of Excellence for Contamination/Defect Assessment and Control. John F. O'Hanlon, Associate Professor and Director of the Center for Microcontamination Control. Within theframework ofglobal definitions the role of defects and contamination in future submicron semiconductor manufacturing are investigated. A defect is defined as anything that causes a non-ideal result, and contamination is defined as anything that results in a defect. Contamination can be categorized as heterogeneous, homogeneous, behaviour altering, and non-uniformities. It is found that control of contamination and reduction of defects, central to high yield manufacturing of state-of-the-art technologies, will become even more important in ihe future due to the strong interdependencies of defects and contamination with all phases of processing, devices and technology, and IC manufacturability. This is cast in a quantitative light by using a simple yield model to examine the defect density requirements for volume production status of I Gb memory chips near the turn of the century. In view of increasing material and processing complexities this leads to the conclusion that the timing of defect reductions for future technology generations is the

single most important potential show stopper or technology limiter. The mandate this provides to the semiconductor industry is that defects and yield loss mechanisms must be considered an integral part of the process development, and in some cases part of the research phase. This can only be done if a coordinated effort focused on achieving defect-free manufacturing is established.

Introduction Contamination technology is a relatively new field, with an uneven historical development. In 1942, the 0.3 }xm HEPA filter was developed for the Atomic Energy Commission; environmental techniques such as glove and dry boxes for handling airborne *Author to whom all correspondence should be addressed: Department of Electrical and Computer Engineering, University of Arizona, Tucson,AZ 85721 USA. Tel: [1] (602) 621 2211. Fax: [1] (602)621 8881.

0026-2692/93156.00 © 1993, Elsevier Science Publishers Ltd.

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radioactive contamination were developed in 1950 [1] H o w e v e r , it was n o t u n t i l 1980 that contamination control technology was considered important by more than a few major semiconductor manufacturers [2] In the last five years, major resources have been allocated by the semiconductor industry for the study of contamination in gases, liquids and processes. As a result, the first contamination control engineers possessed strong backgrounds in cleanrooms and facilities. C o n t a m i n a t i o n in water, gases, or equipment was considered the purview of a specific process engineering function. In parallel with advances in cleanroom engineering, failure analysis engineers identified the causes of defect induced failures [3], while yield engineers used these data to [4] predict yields of current and future processes Process engineers focused on developing processes that would produce materials with desirable p r o p e r t i e s , o f t e n w i t h little c o n c e r n for defect-producing contamination. In the past, m i c r o c o n t a m i n a t i o n was most commonly organized either as a separate group or integrated into a production group. Isolation, and a priority slanted toward production, respectively, were pitfalls of these organizational styles. In today's successful facility, manufacturing, maintenance, process, failure analysis, and yield modelling personnel work as a team. In the future, contamination control and defect management will need to become more tightly coupled t h r o u g h o u t the entire research, development, and manufacturing process than in today's technology. The solution lies in making a

major corporate commitment (e.g., assigning a high level manager) to balance the effort between short term production issues and long term R&D issues [20]. The extremely important role of defects in the 1 Gb D R A M Fabricator (Fab) o f the year 2001 can be projected from the Fab characteristics described by Deininger [21] given in Table 1. In the following sections we examine the many facets of how defects will impact semiconductor manufacturing to the year 2001 and beyond.

Defects and Contamination Defining and describing the roles of contamination and defects now and in the future requires a general approach. Here, a defect is defined as anything that causes a non-ideal result, and contamination is defined as anything that results in a defect. Contamination can be categorized as heterogeneous (foreign particles in solids, liquids and gases); homogeneous (atomic or molecular impurities in gases, liquids, and solids); behaviour altering (photon, phonon, electrostatic, magnetic and radiation fluxes which can modify device properties locally or in bulk); and n o n - u n i f o r m i t i e s (for example, temperature or gas flux variations over a wafer surface, resulting in devices or materials with non-uniform properties). In s t a t e - o f - t h e - a r t technologies, control o f contamination and reduction of defects is central to t h e a c h i e v e m e n t o f low cost, h i g h y i e l d manufacturing. Current cleanroom technology allows construction of Class 1 facilities, with environmental control far exceeding that o f

Table 1. Characteristics of the Year 2000 Fab for I Gb DRAMs [21].

Full CIM Full Automation Automatic Process Control Throughput Parametric Control 6 Sigma Input Parameter SPC In-situ Metrology and Sensors Wafer Microenvironment at Class 0 Cluster Tools Throughout Full ESD Control Simplified Processes

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98%+ FAB Yield 80%+ Sort Yield 75%+ Equipment Utilization 1. lx Theoretical Cycle Time 2 0.05 Defect per cm 300 m m + Wafer Size New People P,.ole Concept Ultra Pure Chemicals and Materials Single Wafer Processing

Microelectronics Journal, Vol. 24, No. 4

processing equipment. Gases can be delivered to the equipment with less that one 0.1 micron diameter particle per scf, whereas Menon [5] cites an example of a gate oxidation furnace that uses such a "Class 1" s o u r c e gas and yet p r o d u c e s w a f e r s w i t h contamination ranging from 10-~to-50 times the maximum number that could result from the pure gas alone. Ultrapure water is also a major concern. Current systems can deliver water with 1 ppb TOC, while purities in the ppt range will be necessary for Gb chips. Bacteria levels to 1 per 100 ml can currently be achieved; however, we know little about the effects o f nucleic acid outside microbial material. Additionally, there are a number of organics which are difficult to remove. Traditional ultrapure water systems have been designed by building variations on previously built systems, and not by studying the system as a whole or the synergistic interaction of its components [6,7] Particle contamination is recognized as the primary yield detractor in ion implantation [8]. Selwyn [9] gives an example of particle contamination in a silicon dioxide sputtering system that was three times worse than leaving the wafer in a Class 10 000 cleanroom for the same time. Particle formation is also a major concern in plasma-enhanced chemical vapor deposition (PECVD) [10], in the rapid pumping of any chamber [11], and in reactive-ion

etching (RIE) [12].The rate at which 0.5 micron diameter particles deposit on a horizontal surface in a cleanroom per particle/cm 3 in t h e air is 0.08/cm2/min. I13]. From this we can show that adding one 0.5 micron diameter particle per 6-in diameter wafer in a 1 minute process, e.g., KIE, is equivalent to leaving the wafer in a Class 2000 room for the same time. We accept this level o f performance from our equipment, yet we would consider it unthinkable to leave a wafer lying uncovered in a Class 2000 room for one minute. In determining the overall magnitude of contamination resulting from a particular process step, we must take into account the number of times the step is used in fabricating the device. Photolithography, resist ashing, and implant are used frequently~14"].;however, cleaning is a major issue because of its extensive use throughout the fabrication process [15]. Cleaning technologies today utilize mainly wet chemistries, and unless there is a paradigm shift in technology, an increased number of wet cleaning steps will be required to process a 1 Gb D R A M . Suitable alternatives must be developed for removal of oxides as well as particles. Dry cleaning using anhydrous HF [16], as well as HF vapour etching techniques [17] have s h o w n some promise for replacing wet processes. However, to date none of the dry clean processes effectively remove heavy metals from wafer surfaces and as such are not replacements

Table 2. Published D R A M Trends.

Year

1978 1982 1983 1984 1986 1988 1989 1990 1992

Capacity bits 64K 64K 256K 256K 1M 4M 4M 16M 16M

Min Feature ktm ref [29] ref [30]

Die Size Mil/edge ref [29]

3.0 2.5

200 200

2.O 1.6 1.2 0.80

ref [301

1.3

9

250 250 300 400

0.80 0.70

300

10 12 14

350 550

0.50

Critical Level ref [30]

16 430

315

for the wet processes yet. More exotic dry particle removal techniques such as shock waves [18] and argon ice cleaning [19] also have shown promise in the research phase for removing many particulate impurities from wafers. In the future, contamination control and defect management will need to become more tightly c o u p l e d t h r o u g h o u t the e n t i r e r e s e a r c h , development, and manufacturing process than in today's technology. As an example of coupling defect engineering to research and development, consider a deposition process such as sihcon dioxide formed from plasma dissociation o f silane and oxygen. Typically one-tenth of the material deposits on the wafer, whereas the remainder deposits on the chamber walls and in the pumping system. Such a process traditionally has been promoted on the basis of its excellent material and topographical properties. However, if the process is intrinsically contaminating, perhaps it should not be moved to the manufacturing arena. To select and develop a process properly, R&D p e r s o n n e l m u s t be g i v e n c o n t a m i n a t i o n specifications 'up front" Particulate generation needs to be given equal weight with estabhshed criteria for process selection. A second example of coupling contamination engineering to manufacturing relates to the role of contamination monitoring metrology. Reliable in-situ metrology must be developed and coupled e f f e c t i v e l y to the c o m p u t e r i n t e g r a t e d manufacturing system so that corrective intervention is automatic, or else the advantages of the metrology will be lost. Currently, neither the metrology nor the coupling is available. The only commercial metrology available for vacuum environments operates downstream from the process, and measures particles in the exhaust and not those landing on the wafer. The work of Selwyn [9l on particle traps in sputtering and Zhao [11] on aerosol condensation are two examples that demonstrate a complete lack of correlation between particle measurements on the wafer and in the exhaust.

The Impact of Related IC Technologies In this section we consider the interdependencies of defects and c o n t a m i n a t i o n w i t h the o t h e r

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technology areas associated with the manufacture of integrated circuits. For this purpose we have grouped the technologies into three broad areas: processing, devices and technology, and manufacturability. Processing considers interactions of defects and contaminants in lithography - - optical and x-ray, etch, deposition, interconnects, material, and new processes. Devices and technology consider the relationship of defects to CAD technology, MOS devices, n o n - M O S devices, and circuit design. Finally, manufacturability considers the relationships of defects to mega facilities, micro facilities, tool control, metrology, and packaging. Processing is considered first because it embraces the technological areas that generally come to mind when we consider the impact of defects caused by particles and h o m o g e n e o u s c o n t a m i n a t i o n . Lithography is an area of major importance in processing in that it is clear that minimum feature size will be decreasing and chip area and number of lithography steps will be increasing with all future technology generations. The interaction of all of t h e s e w i t h p a r t i c l e s and h o m o g e n e o u s contamination results in an adverse affect on yield. This is accentuated further by the fact that lithography defects tend to track a 1/2 minimum feature rule [22], and with a defect number that is inversely proportional to the cube of the defect size down to the deep submicron [23]. This will be further exacerbated by the need to reduce contamination in new materials under development for deep UV and non-organic resists. X-ray lithography shows some potential for an increased tolerance to particulate type defects [24]. However, issues of economics and production line compatibility make its introduction questionable through the turn of the century in light of projected capabilities of phase shift masking and resist technology for 196 nm excimer lasers. Further strains on lithography yield emerge when the global definition of defects adopted in this paper is applied to resolution over large field sizes and to mask overlay accuracy. The relationship of defects and contaminants to plasma etch is closely related to lithography in that this is merely the pattern transfer phase of the operation. Hence, the same technology growth issues, which are important to lithography, are also

Microelectronics Journal, VoL 24, No. 4

important here. Some aspects, however, may be even more critical in that etch processes appear dirtier than lithography processes from a particle standpoint and the defect size distribution appears bimodal with an enhanced number of large defects [25].This is further compounded by the fact that the defect-to-minimum-feature-size follows a tighter rule of at least, and probably more than, 1/5 rather than 1/2. An ancillary yield loss mechanism that is coming under closer scrutiny, as feature size decreases, is the possible yield loss due to radiation damage. Next in importance are interconnects and their associated technologies o f via filling, interlevel dielectric planarization and materials, as processes tend to the 3- to 4-level metal variety. Reliable etching and cleaning will also be a concern in this area. New materials such as Ag, Cu, and advanced alloys of A1 with Pd or Ti for integrated circuit use will require development of deposition processes and equipment that meet rigid demands of cleanliness and purity. Blanket tungsten and selective tungsten on Si for via and contact filling will promote defect issues to be reconciled, as will planarization. With decreasing feature size, depth of focus issues at the various metal layers become paramount, placing increasing demands on planarization. Technologies such as chemical/mechanical frontlap, and in situ deposition and planarization, that are being developed, need much more attention to cleanliness. Other new materials and processes will be required for future technology generations. There is a current push to develop all dry processes, such as vapour

phase etching, and reduced thermal budget processes, such as rapid thermal processing (RTP) and rapid thermal annealing (RTA). These processes will come to the forefront and will bring their own equipment and process defect generation mechanisms with which we must deal. The levels o f particles, homogeneous contaminants, outgassing etc., in materials, and their impact on yield, have always been a point of controversy in the semiconductor industry. H o m o g e n e o u s and particulate contaminants become increasingly indistinguishable as horizontal and vertical integrated circuit dimensions decrease. This is compounded by the demand for new materials such as high permittivity, thin CVD dielectrics and ferroelectrics, and low permeability, easily planarized intermetallic insulators, possibly of the high temperature polymeric type. Many of these currently rely on inherently dirty processes, that will have to be cleaned significantly to pass acceptance standards. In the devices and technology area, MOS devices will remain the workhorse of memories. The decreasing minimum feature size will cause defect interactions through processing and the new materials for thin high permittivity dielectrics cited above. Non-MOS devices will also become more prevalent in future technology generations as innovations in devices and system configurations push designers and process engineers toward more flexible component selection and layout. These developments will increase process c o m p l e x i t y and m a n u f a c t u r e and h e n c e defect/contaminant interaction through various combinations of MOS, bipolar, floating gate, and

Table 3. DRAM Technology Projection. Year 1980 1983 1986 1989 1992 1995 1998 2001

Capacity bits 64K 256K 1M 4M 16M 64M 256M 1G

Min Feature [.tm 2.75 1.80 1.25 0.80 0.60 0.41 0.28 0.19

Die Size mm 2 25 40 60 90 155 245 385 610

Critical Level 9 10 12 14 16 18 20 22

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other on-chip components. An example of this is the p r o j e c t e d increase o f B i C M O S from some interaction at 4 Mb, to measurable amounts at 16 Mb, to possibly predominance at 256 Mb [22].The impact of particulates and homogeneous defects on these device combinations, with increased process complexity, are in many instances still undefined but will undoubtedly be of major proportion and at least an order o f m a g n i t u d e m o r e difficult than conventional MOS processes. CAD will be of importance in the layout methodology for immunity to defects, design for testability, and redundancy. Also of importance will be the need for robust processes, and circuit designs that operate at reduced voltages. Megafab m a n u f a c t u r i n g will b r i n g w i t h it equipment issues related to operating cluster tools and mini/micro environments at extremely low defect densities. Wafer flow, fab layout, and statistical process control all have direct ties to defects and contaminants in process yield [26-28]. Metrology of defects, for both particulate and homogeneous contaminants in the deep submicron regime, will present major issues for resolution, detectability and speed of response. Multi-chip modules and high density interconnects will cause new yield issues and mechanisms in packaging technology.

Extrapolating Capabilities to The Year 2000 and Beyond Since the LSI era of semiconductor manufacturing, MOS memory has been the vehicle that has provided the driving force for technology development. More recently, beginning with the VLSI era in 1975 with chips containing more than 100 000 devices, the MOS dynamic random access memory (DRAM) has been the technology driver. Recent reports of D R A M technology development taken from the literature [29,30] are summarized in Table 2. These data represent input from both Japanese and American viewpoints. Typically, the time frame for D R A M technology introduction has followed a schedule of first disclosure at the International Electron Devices Meeting in December or at the International Solid State Circuits Conference the following February. Sample prototypes follow in

318

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People Environment

'0i__/__ l__J • Year

Figure 1. Percent Defect Allocation by Source Type. about 1.5 years and limited production in about two years from first disclosure. Volume production is typically achieved within three years of initial disclosure. Based on the dates in this table and the technology disclosures at the cited conferences, these data represent the limited production era for technology introduction. We have combined these sources into a single trend by averaging the discrepancies in Table 2, as shown by the first five entries of Table 3. The trends shown by these entries indicate on average a new technology is introduced every three years. With every new generation of DRAM, minimum feature size decreases by approximately 70% and chip size increases by roughly a factor of 1.6. The process c o m p l e x i t y increases two critical levels per generation. Following these trends the projections for D R A M i n t r o d u c t i o n are shown in the subsequent entries of Table 3. The trends predict 1Gb DRAMs at the turn of the century fabricated with deep sub-micron technology, as predicted by others [3 !,32]. The actual timing, as indicated in Table 3, may be more widely spaced for volume production. We have already seen this, to some degree, with the transition from 1 Mb to 4 Mb, where ramp-up to volume production for the 4 Mb D R A M didn't actually happen until late 1990 [33]. This was due in part to the drastic change in process from planar to t r e n c h t e c h n o l o g i e s e x p e r i e n c e d by these generations. A similar timing glitch, also due to

Microelectronics Journal, VoL 24, No. 4

necessary process architecture changes, has been projected for the transition from 64 Mb to 256 Mb DILAMs [34]. t(egardless of the actual timing, the technology projections for each DR.AM generation agree with those anticipated by the industry, and result in 1 Gb D R A M s at or shortly after the turn of the century [35]. Similarly, the actual numbers for other parameters in Table 3 may be slightly in error. For example, these authors have heard o f minimum feature sizes as low as 0.12 micron [36] and chip sizes as large as 10 000 mm 2 [36] for the 1 Gb D R A M , Nevertheless, for the purpose of this paper, these trends are sufficiently accurate for the following discussion. In order to ascertain the relationship of defects to the technology trends presented in the previous paragraphs, the nature of yield loss mechanisms must be examined. Yield loss in integrated circuits is a result of defects which fall into one of the three classifications of point defects, line defects, and area defects. Point defects affect an area much smaller than

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the chip itself, whereas, in general, line and area defects affect an area much larger than the chip. D e f e c t density is associated with r a n d o m l y distributed point defects. Line and area defects are considered a gross yield loss mechanism, which would adversely affect the yield of a die of any practical size. Thus yield loss can be partitioned into a chip-area-independent gross loss component, and a chip-area-dependent random loss component. Typically, as a given process matures, gross defects are eliminated or minimized rapidly, whereas, the random defect sources are continually fought throughout the process life. For this discussion of yield loss mechanisms we will concentrate solely on random defects. Often these are referred to as particulate defects, which are indeed a major, if not the total source of random defects, provided one adopts a global meaning of particulate as 'the smallest possible portion or amount of something.' This allows definition of random defects as particulates down to the atomic level, as is truly the case. However, it must be realized, that below some fraction o f the minimum feature size, 1/5th, 1/10th, or 1/20th depending on the portion of the IC being affected, t h e s e p a r t i c u l a t e s m a y b e h a v e m o r e like homogeneous contaminants than conventional particles. There are many sources of random defects. For further discussion we have grouped them into the four general categories of people, environment, equipment, and processes. The evolutionary trend of these defects taken from our work and from the literature [38,39] with projections through the turn of the century is shown in Fig. 1. In the early days of integrated circuit manufacture, people and the manufacturing environment were the primary cause of yield loss. As we entered the VLSI era, these defect sources were recognized and major efforts were made to upgrade the class o f cleanrooms and cleanroom attire. By the mid-eighties it was recognized that this was by itself n o t e n o u g h , and the move toward automation to isolate the wafers from people and environment had begun. As the industry approached the nineties, this resulted in a decreasing trend in relative importance of these defects, and an increase in the relative importance o f equipment and

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Figure 3. DRAM Defect Density Rquirements by Source Type. p r o c e s s - r e l a t e d y i e l d loss m e c h a n i s m s . Process-related defects b e c a m e increasingly important, due to the need for complex structures such as trench capacitors in DRAMs. This was compounded by recognition that many defects believed to be equipment-related were actually associated with the processes carried out in the equipment [40,41]. As this decade progresses, defects associated with people and environment will level out at a constant contribution of approximately 5%. This is a result of the fact, that, in spite of automation and continual improvements in cleanroom clothing, there will always be some necessary wafer contact by these defect sources. Equipment and process related defects are expected to account for the majority of defects throughout the decade. Equipment defects will remain of importance, due to the longer residency time of wafers in cluster tool fabrication equipment. This will also be exacerbated by electrostatic particulate adhesion effects, which can be associated with equipment or process, and by handling effects required for the large wafer diameters of future technology generations. This last statement serves to introduce an area often overlooked in discussions of technology trends. As the minimum feature size decreases, and chip size increases, less chips can be placed on a wafer of a given size. As we shall see shortly, the combination of minimum feature reduction and area increase has an extremely negative impact on yield. This, coupled with a reduced number of chips per wafer, can rapidly reduce the number of good chips achievable, even at

320

reasonable process yields, to a number below or dangerously close to the profit margin. Thus, the technology trends mandate an increase in wafer size, just to provide e n o u g h chips per wafer for economical reasons. The requirements for increased wafer diameters, as dictated by the D R A M trend are illustrated in Fig. 2, which gives the number of chips per wafer, N, as a function of chip area, A, and wafer diameter, D, according to the empirical formula given by Cunningham andJaffe [42]. N = ~ (D/2 - ~A) 2 A

- - Eqn. 1

Eqn. 1 simply accounts for edge die loss by reducing the wafer radius by the linear chip edge. Basically, Fig. 2 shows that 300 mm wafers will be required by the turn of the century to maintain a reasonable chip count per wafer, e.g. -100. The major impact of wafer handling for large wafers will occur in the timeframe of the 256 Mb D R A M . In fact, if the wafer industry can produce 300 mm wafers early enough, Fig. 2 suggests that the 250 mm wafer should be omitted to minimize equipment upgrades. Process defects will also remain of paramount importance for large memories throughout the decade, and compete with equipment defects as the leading source. The impact of gaseous and liquid chemicals on electrical parameters, such as device leakage and dielectric breakdown, are expected to be

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large for both the 64 Mb and 1 Gb chips, and push process defects ahead of equipment defects in these timeframes. The advent of new process technologies for 256 Mb chips and beyond will also contribute to process-related defects in this timeframe, but will be equalled by defect sources related to the new equipment required to carry out these processes.

Defects and Contamination: Challenges and Alternatives The impact of the D R A M technology projections on defect density in light o f manufacturing requirements of the future can be investigated with a yield model. As a yield model we assume the simple Bose-Einstein model that accounts for process complexity [43] y =

- - Eqn. 2

+ In Eqn. 2, Y= yield, A = chip area, D = average defect density per critical level and n = the number of critical process levels. Traditionally, a yield of 50% has been assumed for process defect comparisons [1] Using this value and data from Table 3, Eqn. (2) can be inverted to solve for the required defect density to achieve 50% yield for the various generations of DRAMs. Note, however, that the defect density calculated in this manner assumes the minimum feature size of the technology in question. In order to compare the actual impact of defect densities we must make the comparison at a fixed defect size, since, in general, defects have an associated size distribution. This size distribution has been determined to be inverse cubic for particles well into the sub-micron regime [23,44]. Since defect density is the cumulative result o f all defects greater than some size (approximately 1/10 minimum feature), defect densities at different minimum feature sizes are related by the square of the minimum feature size. For lack of a better size distribution we assume the cubic law, as for particles, and refer defect densities to the 1 Mb D R A M for comparisons. Thus the referred defect density, D1.25Bm, is given by:

qn3 XG is the minimum feature size for the D R A M generation in question, and DG is the calculated defect density for that generation by inversion of Eqn. 2 at 50% yield. The results of these calculations for the D R A M projections of Table 3, with defects proportioned in accordance with Fig. 2, are shown in Fig. 3. Figure 3 shows that the defect reduction from 1 Mb technology to 1 Gb technology mus~be f o u r o r d e r s o f m a g n i t u d e for p e o p l e and environment, and three orders of magnitude for equipment and processes. By the turn of the century~ absolute defect denslues must be on the order of 10 per critical level for people and environment, and -4 .. 10 per crmcal level for equipment and processes. Achieving defect densities at these levels will present e x t r e m e challenges in all phases o f defect engineering, contamination control, and equipment design. It is interesting to examine the impact of the trend setting D R A M on other areas of integrated circuit technology. Wafer scale integration (WSI) provides a means for achieving high chip density and computational power. However, without some form of redundant architecture yield enhancement, the yield for WSI would be essentially zero. Nevertheless, an important parameter for this methodology is the so called 'kill area' where a defect cannot be tolerated. In some WSI implementations the 'kill area' can occupy a significant portion of the total area [45] Investigation of this 'kill area' also gives and indication of the impact of technology trends on single chip technologies. To evaluate the impact of future process and manufacturing technologies on the 'kill area'for WSI, we have calculated the maximum chip size assuming a minimum acceptable yield of one die per wafer. If an increased lot yield is required, then chip sizes will be somewhat smaller than these calculations indicate. If a reduced yield can be tolerated, then, of course, an increased number of error-free chips can be fabricated• The results of these calculations are shown in Fig. 4 for two levels of process complexity.

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Not all processes need be as complex as required by D R A M technology. We have considered this in our calculation by modelling the maximum error-free chip size for a process of reduced complexity, as well as for the DRAM. For the reduced complexity process we assume four fewer critical levels per generation than the DRAM. These calculations indicate 'kill areas' in excess of 5 cm per edge by the turn of the century, due to the advances in D R A M manufacturing capabilities. Perhaps the single most important potential show-stopper in the technology trend set by the D R A M is the criticality of timing. As we have just seen, every three years spawns a new generation of D R A M with a four-fold increase in storage sites, an attendant decrease in minimum feature size and an increase in die size. According to Larrabee and Chatterjee [36] the five years preceding volume production of any given D R A M generation consist of a two-year development phase, and a three-year productization phase. Prior to this is a research phase. D u r i n g the d e v e l o p m e n t phase, device and m a n u f a c t u r i n g t e c h n o l o g i e s are e x a m i n e d , evaluated, and refined. The development phase culminates in the fabrication of functional devices with proven designs in a manufacturing technology that is essentially frozen. In the following three year productization phase no major changes are made to the manufacturing technology, and the process becomes a manufacturing hardened process through fine tuning of the unit steps. Characteristically, it has been in this phase of product development that the first real attempts at yield enhancement have been initiated. In this three year period yield must be taken from essentially zero to the roughly 30% required at the onset of volume production. Fortunately, to date, we as an industry have been able to accomplish this successfully. During the productization phase, fine tuning of both device designs and process sequences has resulted in optimizations that have minimized parametric and hard defect yield loss mechanisms. This has been somewhat aided in that the materials and unit step equipment and processes have been relatively constant over the 1 Mb to 16 Mb era. For example, SiO2- and Si3N4-based dielectrics have been typically used throughout these generations.

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Although there have been improvements in resolution and changes in process methodology, e.g. the shi~ from planar to trench technologies, the characteristics of the equipment and unit process steps to produce the technology have stayed substantially constant. This has allowed time for development and perfection of the equipment itself, as well as the unit step processes. For the 64 Mb D R A M and beyond new dielectrics such as CVD Ta205, or BaTiO3 and ferroelectrics will emerge for the thin storage cell dielectric. N e w high conductance metallization schemes and alternate intermetal dielectrics, possibly of a high temperature polymeric type will also appear. The list goes on and on for potentially useful new materials and processes for semiconductor manufacturing [46] Characteristically, CVD processes have been known particle generators and have been cleaned sufficiently for less critical, thick, interlevel dielectrics. What problems in terms of particles and yield limiters await with the use of these as thin storage cell dielectrics, or for ferroelectrics for that matter, are not completely known. In fact, this can be said about all new unit step processes and their production equipment. We can no longer wait until the productization phase of the technology cycle to address these issues. Defects and yield loss mechanisms must be considered an integral part of the process development, and in some cases part of the research phase. This is a difticult mandate when one considers that in late 1992 it is projected that serious D R A M manufacturers will have the 1 Gb D R A M in research, the 256 Mb D R A M in development, the 64 Mb D R A M in productization, and the 16 Mb D R A M in volume ramp-up. Currently the best surface scanners can detect particles of 0.1 micron minimum size. This is not even close to the 1/10th defect to minimum feature rule often cited for the industry for technologies in the various phases of evolution. If particles cannot be easily, reliably, and rapidly detected it will be difficult to eliminate them in the unit step development. Thus, there will be ever greater challenges in defect detection and analysis through the turn of the century. Homogeneous defects present yet another problem. Currently, these defects and their impact on future

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device yields are not at all well understood.As a result, to date, the industry has handled potential problems from these sources by setting stringent limits on material specifications, e.g. metallic contaminants in process fluids. This, of course, has been accompanied by attendant increases in cost for these chemicals that will b e c o m e prohibitive for future DR, A M manufacture. This has led to the development of alternative process sequences such as dry cleaning for the case mentioned. However, this does not solve the problem, but merely avoids it with the possibility of introducing yet another problem. Thus, an increased level o f research must be d i r e c t e d t o w a r d u n d e r s t a n d i n g the nature and impact o f all homogeneous contaminants. It is expected that device operating voltage will drop from 3.3 V for the 64 Mb D R A M to 2.5 V for the 256 Mb D R A M to possibly 1.5 V for the 1 Gb D R A M . This introduces the possibility for a resurgence of importance of parametric yield losses and device sensitivities that will have to be dealt with in the design of devices and processes for future technology generations. Achieving 'FAB 2001' will require paradigm shifts in many areas, one of which is the manner in which efforts are coordinated and focused for achieving defect-free semiconductor manufacturing. A new structure is needed to coordinate these resources nationally. If these resources were to be coordinated appropriately, each resource would be able to plan, exchange technology, and collaborate, while retaining a degree of freedom to chart unexplored waters or even allow for some duplication. Current consortia have demonstrated advantages of joint research sponsorship. Hohon [47] has described how a consortium can coordinate and develop a research program, while conserving limited resources. It cannot be questioned that the need to create such a coordinated effort exists. The only questions are will it happen, and in what form? Traditionally, the US industry has relegated defects and contamination control as a sub-class of the manufacturing sector. Basically, if a technology was being 'snake bitten'by a yield problem, the resources, both funding and personnel, were provided to put the technology back on track. However, if the process

was running relatively smoothly, funds for capital equipment and personnel were not generally available above minimum requirements. This was somewhat compounded by the fact that a stigma of lesser class was associated with manufacturing engineering and science. Thus, the best engineering and scientific personnel sought positions in research, advanced development, and academia, where issues o f d e f e c t s c o n t a m i n a t i o n and hard c o r e manufacturing were not in vogue. In recent years this role has been changing due to lessons from Asian manufacturers, where manufacturing science is not only a recognized, but a highly rewarded activity. This trend must not only continue, but must accelerate to m e e t the c h a l l e n g e s o f f u t u r e s u b m i c r o n semiconductor manufacture. If the investment is not made in personnel, training, equipment and research and development to accelerate, rather than to just meet, the learning curve slope our industry will not succeed.

The Future Role of Defects and Contamination The role of defects in gigabit device production is clear. Killer defects must be reduced to the level of 0.0001 per cm 2 per critical level for equipment and processes. This in turn will drive research in metrology, processes chemicals and equipment. Metrology of all forms, including that which directly measures a contaminant as well as that which measures the effect of a contaminant, has a dominant role in manufacturing evolution, because defects must be measured before they can be eliminated. In almost every case advances in metrology or metrology applications come before identification and elimination of contaminants. In parallel, research on processes must identify which parameters must be controlled to eliminate contaminant formation. Not only will this mean new metrology instruments, but sophisticated instruments connected to production tools. The economics o f manufacturing large, multi-level wafers in single wafer tools is such that continuous monitoring will become an economic necessity. It is suggested here that such production metrology will be elegant and take the form of research instrumentation.

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T h e e f f e c t o f i n v e s t m e n t s on d e f e c t and contamination reduction is an integral part of the future of high end semiconductor manufacturing. Although contamination control is not the only issue, it plays a major role in shaping the environments, tools and manufacturing techniques of the fab of the future. It is imperative that these extremely expensive tools have performance far superior to today's tools. 75% equipment utilization with mean time to repair of the order of 2 hours is one goal for Fab 2001 I21]. All of these objectives significantly increase the cost of the facilities, equipment, gases, chemicals and water.

Currently, a new 4 Mb fab costs between $500 and $600 million to construct, and the cost is escalating at 30% per generation [2ll. There are over 30 new fabs recently constructed or under construction worldwide at the present time with a total investment of the order of $20 billion. It is estimated that it will cost $1-2 billion to build a 1 Gb D R A M fab in 10 years. This increased cost will be due to the cost of cluster tools, metrology, c o m p u t e r integrated manufacturing, and wafer environment. Added to this will be the increased cost of chemical waste disposal, and water. It is not difficult to predict that the number of companies able to afford investments of this magnitude will decrease. Furthermore, these investments will have to be operated and managed in the most cost-effective and innovative ways including the recycling of water and chemicals, and the subcontracting of point-of-use delivery of chemicals [49], gases and water [50[ High-end semiconductor manufacturing does not fit a classical business pattern. It is at the same time both labour and capital equipment intensive, and in the case of the D R A M , is both a high technology product and a commodity. The effect of yield loss becomes acute with increased competition in any business, and semiconductor manufacturing is no exception. Defect-induced yield losses have a profound effect on the profit in a sub-micron facility. To gain s o m e q u a n t i t a t i v e i n s i g h t into semiconductor manufacturing, a model has been constructed from which we can calculate the manufacturing cost of the high tech driver, the

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D R A M [511. From this model the ratio of profit loss to yield loss is calculated for a given margin. This model illuminates the need for reducing labour, increasing capital equipment utilization, increasing up-time and reducing maintenance. None of these can be accomplished without considerable attention to reduction of sub-micron defects. The model given in this example is used to calculate the cost of manufacturing 4 Mb DRAMs on 150 mm diameter wafers with a product life cycle of 40 months. The building, cleanroom and utilities were considered to have a 10 year life and were constructed for $150 million. The process equipment was installed at a cost of $400 million and was considered to have a 40 month life. This is typical of new sub-micron fabs constructed today [52[:Wafers typically cost $500 each after processing; the epi wafer costs $82, with the remainder split equally between labour and chemicals. This fab had a capability of 1500 wafer starts per day (50% equipment utilization, and 80% uptime). The fab yield was chosen to be 94%. The remainder of the line consisting of probe, ink, cut, sort, package, assembly burn-in and final test was modelled to operate at an overall yield of 95% and cost $0.95/good chip. Utilities and operations were included at the rate of $10 million/year. Interest charges were not considered. Although simple, this model yields basic insights about the major costs in manufacturing DRAMs. The total annual breakeven cost for this model is $427 million to produce 67.3 million chips at a cost of approximately $6.35 per chip. This compares with the sale price in early 1991 of approximately $16 per chip. The cost breakdown is: equipment 28%; labour 21.5%; chemicals 21.5%; probe, test and package 15%; wafers 8%; building 3.5%; and operations 2.5%. There are several conclusions we can draw from this model. First, equipment, labour, and chemicals are the major expenses, accounting together for over 70% of the manufacturing cost. Second, major savings can result from increased equipment utilization, automation, uptime, as well as reduced maintenance and direct labour. The average US fab has an equipment utilization of 40%, whereas the Japanese average is between 55% and 60% [21]. None

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of these savings can happen without critical advances in defect reduction. Third, the cost of yield loss and equipment downtime is high. In this model a reduction in yield from 94% to 93% gave a loss in profit of 4%, if the product were sold with a 30% margin. As competition increases and margins decrease, the leverage of yield on profit will increase correspondingly, therefore each component cost of production must be examined for possible cost reductions. Highly trained and motivated people are an intangible part of the system. It is becoming increasingly imperative that everyone involved understand the complexity of the process, and its myriad interdependencies. Trained and effective p e r s o n n e l are as i m p o r t a n t as high quality equipment.

Summary Perspective on Defects and Contamination In this paper we have looked at the role of defects and c o n t a m i n a t i o n in f u t u r e s u b m i c r o n semiconductor manufacturing. To do this we found it beneficial to institute global definitions of defects and contamination. A defect is defined as anything that causes a non-ideal result, and contamination is defined as anything that results in a defect. Contamination can be categorized as heterogeneous (foreign particles in solids, liquids and gases); homogeneous (atomic or molecular impurities in gases, liquids, and solids); behaviour altering (photon, phonon, electrostatic, magnetic and radiation fluxes which can modify device properties locally or in bulk); and n o n - u n i f o r m i t i e s (for example, temperature or gas flux variations over a wafer surface, resulting in devices or materials with non-uniform properties). Within these definitions we found that in state-of-the-art technologies control of contamination and reduction of defects is central to the achievement of low cost, high yield manufacturing. This fact will remain true, and become even more important in the foreseeable future, due to the strong interdependencies of defects and contamination with all phases of processing, devices and technology, and integrated circuit manufacturability.

The magnitude o f the impact o f defects and contamination for the integrated circuit industry was cast in a quantitative light by considering the industries trend setting D R A M technology. Using a simple yield model, defect densities required to achieve a modest 50% yield for future D R A M generations were calculated using the predicted trends in minimum feature size, chip size, and process complexity. Based on defect partitioning, the results showed that to achieve volume production status for the 1 Gb memory near the turn of the century, defect densities would have to be reduced by 3 to 4 orders of magnitude from I Mb D R A M production levels. In view of increasing material and processing complexities we are led to the conclusion that the timing of defect reductions for future technology generations is the single most important potential show stopper or technology limiter in this area. The mandate that this provides to the semiconductor industry is that defects and yield loss mechanisms must be considered an integral part of the process development, and in some cases part of the research phase. This we believe can only be done if a coordinated effort focused on achieving defect-free manufacturing is established.

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