- Email: [email protected]
The future of automation for high-volume wafer fabrication and ASIC manufacturing
940
World Abstracts on Microelectronics and Reliability
problems of insufficient current gain or low emitter-collector punchthrough voltage. It is clear that while progress will continue in scaling the familiar high-speed ECL logic and memory, the integration level of these very-high-speed chips is severely limited by the accompanied power dissipation. One seemingly promising and yet relatively unexplored direction is to increase the integration level by taking advantage of circuits with much lower power-delay product than ECL, such as NTL, TTL, CML, and MTL to improve the functional throughput. The technology challenges as well as the potential of submicrometer bipolar technology are also discussed. Three-dimensional IC trends. Yolcm AKASAKA.Proc. IEEE 74 (12), 1703 (1986). VLSI will be reaching to the limit of minimization in the 1990s, and after that, further increase of packing density or functions might depend on the vertical integration technology. Three-dimensional (3-D) integration is expected to provide several advantages, such as (1) parallel processing, (2) highspeed operation, (3) high packing density, and (4) multifunctional operation. Basic technologies of 3-D IC are to fabricate SOl layers and to stack them monolithically. Crystallinity of the recrystallized layer in SO1 has increasingly become better, and very recently crystal-axis controlled, defect-free singlecrystal area has been obtained in chip size level by laser recrystallization technology. Some basic functional medals showing the concept or image of a future 3-D IC were fabricated in two or three stacked active layers. Some other proposals of subsystems in the application of 3-D structure, and the technical issues for realizing practical 3-D IC, i.e. the technology for fabricating high-quality SO1 crystal on complicated surface topology, crosstalk of the signals between the stacked layers, total power consumption and cooling of the chip, will also be discussed in this paper. Trends in advanced process technology--submicrometer CMOS device design and process requirements. DALE M. BROWN, MARIOGaEZZO and JOSEPHM. PIMBLEY.Proc. 1EEE 74 (12), 1678 (1986). Some of the trends in integrated circuit process development are described. The motivations or technical reasons for this activity are discussed. This effort will continue to develop the downsizing that increases functional density and performance. Limiting factors are examined and new technical developments that could enable CMOS density to be comparable with NMOS density are explored. Various isolation techniques are described and the influence on performance of well profiles and doping concentrations are examined. These trends have a bearing on the choice of gate electrode materials. Reliability factors governing the gate dielectric thickness are discussed briefly. M O S F E T diode capacitance is shown to be the predominant limiting factor at the device level. Methodologies that could be used to reduce device parasitics are considered in detail. Device scaling below 1-p_mcalls for changes in contact metallization techniques. Trends in metallization technology and the various methods of fabricating multilevel interconnections when the via sizes become very small are described. The processing methods being investigated to overcome device limitations are examined and compared. In some cases, the present technical difficulties of these methods are discussed. The general conclusion of this work is that "'downsizing" will continue, but advances will be more dependent upon innovative processes and device research, whereas in the past, scaling rules were adequate and progress was evolutionary. Forecast '87. Wafer fabrication trends. JOHN M. SALZER. Semiconductor int., 44 (January 1987). Will the demands of a recovering economy blind us to the needs for major changes in processing, equipment and materials?
Forecast '87. CIM trends. JERRY SECREST.Semiconductor int., 68 (January 1987). Equipment is being computerized, fabs reorganized into work cells and network is just starting. Equipment reliability is paramount. Microprocessor technology trends. GLENFORD J. MYERS, ALBERT Y. C. Yu and DAVID L. HOUSE. Proc. IEEE 74 (12), 1605 (1986). The rapid pace of advancement of microprocessor technology has shown no sign of diminishing, and this pace is expected to continue in the future. Recent trends in such areas as silicon technology, processor architecture and implementation, system organization, buses, higher levels of integration, self-testing, caches, coprocessors, and fault tolerance are discussed, and expectations for further advances are highlighted. How these trends and expectations will drive the markets and applications, and vice versa, is also explored. The future of automation for high-volume wafer fabrication and ASIC manufacturing. RANDALLA. HUGHES and JOHN D. SHOTT. Proc. IEEE 74 (12), 1775 (1986). Faced with increasing technical and commercial challenges from the Far East, many U.S. semiconductor manufacturers have been directing their efforts toward the Application-Specific Integrated Circuit (ASIC) or custom integrated circuit marketplace. This market is flourishing because advances in technologies such as gate arrays and standard cells now make it significantly easier to obtain system cost and performance advantages by integrating non-standard functions on silicon. They are attractive to U.S. manufacturers because they place a premium on sophisticated design tools, familiarity with customer needs and applications, and fast turn-around fabrication. These are areas where U.S. manufacturers believe they have an advantage and, consequently, they believe they will not suffer from the severe price/manufacturing competition encountered in conventional high-volume semiconductor products. In the past, automation was often considered viable only for high-volume manufacturing, but automation becomes a necessity in the new ASIC environment. ASIC requirements for increased product variability, strict delivery schedules, and the need to guarantee acceptable yields at the individual wafer level (as opposed to yields averaged over large lots) are the areas which automation must address. These challenges, combined with the need for more efficient and contamination-free production environments, are certain to stress the resources of even the most competent companies. This paper explores some challenges which must be met before automated custom device manufacturing can be successful and outlines the role automation will play in helping to meet these challenges. Forecast '87. Final test. JIM MULADY. Semiconductor int., 60 (January 1987). Expect slow market growth and more competition in final test equipment markets. Semiconductor memory trends. SHOJIRO ASAI. Proc. IEEE 74 (12), 1623 (1986). In retrospect, over the past decade and a half, semiconductor memories have been in the stage of youthful growth. A thousand times increase in density and a ten times increase in speed have been recorded. Semiconductor memories have thus been a key element in the revolutionary development of digital electronics. Today, they are undoubtedly entering their age of maturity. Their density limit will be on the order of 100 Mbits per chip, roughly a hundred times the state of the art, and additional speed increase will he less than ten times. Nonetheless, the challenge is still there. Efforts to search for new technology which will actually bring out, in a cost-effective manner, the remaining density and speed potential of semiconductor memories are essential. A thorough investigation is needed to clarify and
World Abstracts on Microelectronics and Reliability
problems of insufficient current gain or low emitter-collector punchthrough voltage. It is clear that while progress will continue in scaling the familiar high-speed ECL logic and memory, the integration level of these very-high-speed chips is severely limited by the accompanied power dissipation. One seemingly promising and yet relatively unexplored direction is to increase the integration level by taking advantage of circuits with much lower power-delay product than ECL, such as NTL, TTL, CML, and MTL to improve the functional throughput. The technology challenges as well as the potential of submicrometer bipolar technology are also discussed. Three-dimensional IC trends. Yolcm AKASAKA.Proc. IEEE 74 (12), 1703 (1986). VLSI will be reaching to the limit of minimization in the 1990s, and after that, further increase of packing density or functions might depend on the vertical integration technology. Three-dimensional (3-D) integration is expected to provide several advantages, such as (1) parallel processing, (2) highspeed operation, (3) high packing density, and (4) multifunctional operation. Basic technologies of 3-D IC are to fabricate SOl layers and to stack them monolithically. Crystallinity of the recrystallized layer in SO1 has increasingly become better, and very recently crystal-axis controlled, defect-free singlecrystal area has been obtained in chip size level by laser recrystallization technology. Some basic functional medals showing the concept or image of a future 3-D IC were fabricated in two or three stacked active layers. Some other proposals of subsystems in the application of 3-D structure, and the technical issues for realizing practical 3-D IC, i.e. the technology for fabricating high-quality SO1 crystal on complicated surface topology, crosstalk of the signals between the stacked layers, total power consumption and cooling of the chip, will also be discussed in this paper. Trends in advanced process technology--submicrometer CMOS device design and process requirements. DALE M. BROWN, MARIOGaEZZO and JOSEPHM. PIMBLEY.Proc. 1EEE 74 (12), 1678 (1986). Some of the trends in integrated circuit process development are described. The motivations or technical reasons for this activity are discussed. This effort will continue to develop the downsizing that increases functional density and performance. Limiting factors are examined and new technical developments that could enable CMOS density to be comparable with NMOS density are explored. Various isolation techniques are described and the influence on performance of well profiles and doping concentrations are examined. These trends have a bearing on the choice of gate electrode materials. Reliability factors governing the gate dielectric thickness are discussed briefly. M O S F E T diode capacitance is shown to be the predominant limiting factor at the device level. Methodologies that could be used to reduce device parasitics are considered in detail. Device scaling below 1-p_mcalls for changes in contact metallization techniques. Trends in metallization technology and the various methods of fabricating multilevel interconnections when the via sizes become very small are described. The processing methods being investigated to overcome device limitations are examined and compared. In some cases, the present technical difficulties of these methods are discussed. The general conclusion of this work is that "'downsizing" will continue, but advances will be more dependent upon innovative processes and device research, whereas in the past, scaling rules were adequate and progress was evolutionary. Forecast '87. Wafer fabrication trends. JOHN M. SALZER. Semiconductor int., 44 (January 1987). Will the demands of a recovering economy blind us to the needs for major changes in processing, equipment and materials?
Forecast '87. CIM trends. JERRY SECREST.Semiconductor int., 68 (January 1987). Equipment is being computerized, fabs reorganized into work cells and network is just starting. Equipment reliability is paramount. Microprocessor technology trends. GLENFORD J. MYERS, ALBERT Y. C. Yu and DAVID L. HOUSE. Proc. IEEE 74 (12), 1605 (1986). The rapid pace of advancement of microprocessor technology has shown no sign of diminishing, and this pace is expected to continue in the future. Recent trends in such areas as silicon technology, processor architecture and implementation, system organization, buses, higher levels of integration, self-testing, caches, coprocessors, and fault tolerance are discussed, and expectations for further advances are highlighted. How these trends and expectations will drive the markets and applications, and vice versa, is also explored. The future of automation for high-volume wafer fabrication and ASIC manufacturing. RANDALLA. HUGHES and JOHN D. SHOTT. Proc. IEEE 74 (12), 1775 (1986). Faced with increasing technical and commercial challenges from the Far East, many U.S. semiconductor manufacturers have been directing their efforts toward the Application-Specific Integrated Circuit (ASIC) or custom integrated circuit marketplace. This market is flourishing because advances in technologies such as gate arrays and standard cells now make it significantly easier to obtain system cost and performance advantages by integrating non-standard functions on silicon. They are attractive to U.S. manufacturers because they place a premium on sophisticated design tools, familiarity with customer needs and applications, and fast turn-around fabrication. These are areas where U.S. manufacturers believe they have an advantage and, consequently, they believe they will not suffer from the severe price/manufacturing competition encountered in conventional high-volume semiconductor products. In the past, automation was often considered viable only for high-volume manufacturing, but automation becomes a necessity in the new ASIC environment. ASIC requirements for increased product variability, strict delivery schedules, and the need to guarantee acceptable yields at the individual wafer level (as opposed to yields averaged over large lots) are the areas which automation must address. These challenges, combined with the need for more efficient and contamination-free production environments, are certain to stress the resources of even the most competent companies. This paper explores some challenges which must be met before automated custom device manufacturing can be successful and outlines the role automation will play in helping to meet these challenges. Forecast '87. Final test. JIM MULADY. Semiconductor int., 60 (January 1987). Expect slow market growth and more competition in final test equipment markets. Semiconductor memory trends. SHOJIRO ASAI. Proc. IEEE 74 (12), 1623 (1986). In retrospect, over the past decade and a half, semiconductor memories have been in the stage of youthful growth. A thousand times increase in density and a ten times increase in speed have been recorded. Semiconductor memories have thus been a key element in the revolutionary development of digital electronics. Today, they are undoubtedly entering their age of maturity. Their density limit will be on the order of 100 Mbits per chip, roughly a hundred times the state of the art, and additional speed increase will he less than ten times. Nonetheless, the challenge is still there. Efforts to search for new technology which will actually bring out, in a cost-effective manner, the remaining density and speed potential of semiconductor memories are essential. A thorough investigation is needed to clarify and