The interface states analysis of the MIS structure as a function of frequency

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Microelectronic Engineering 85 (2008) 542–547 www.elsevier.com/locate/mee

The interface states analysis of the MIS structure as a function of frequency A. Tatarog˘lu *, S ß . Altındal Physics Department, Faculty of Arts and Sciences, Gazi University, 06500 Ankara, Turkey Received 17 July 2007; received in revised form 20 August 2007; accepted 22 September 2007 Available online 29 September 2007

Abstract The energy distribution of interface states (Nss) and their relaxation time (s) were of the fabricated the Al/SiO2/p-Si (MIS) structures were calculated using the forward bias current–voltage (I–V), capacitance–frequency (C–f) and conductance–frequency (G–f) measurements. Typical ln[I/(1  exp(qV/kT)] versus V characteristics of MIS structure under forward bias show one linear region. From this region, the slope and the intercept of this plot on the current axis allow to determine the ideality factor (n), the barrier height (Ub) and the saturation current (IS) evaluated to 1.32, 0.77 eV and 3.05 · 109 A, respectively. The diode shows non-ideal I–V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer at metal–semiconductor interface, the interface states and barrier inhomogeneity of the device. The energy distribution of interface states (Nss) and their relaxation time (s) have been determined in the energy range from (0.37  Ev) to (0.57  Ev) eV. It has been seen that the Nss has almost an exponential rise with bias from the mid gap toward the top of valance band. In contrary to the Nss, the relaxation time (s) shows a slow exponential rise with bias from the top of the Ev towards the mid gap energy of semiconductor. The values of Nss and s change from 6.91 · 1013 to 9.92 · 1013 eV1 cm2 and 6.31 · 104 to 0.63 · 104 s, respectively.  2007 Elsevier B.V. All rights reserved. Keywords: MIS structure; Ideality factor; Barrier height; Interface states; Relaxation time; Frequency dependence

1. Introduction The metal–insulator–semiconductor (MIS) structures become more and more important in a great variety of fields of modern electronics. The performance and reliability of these structures especially is depend on the formation of insulator layer between metal and semiconductor interface, the interface states distribution between semiconductor and insulator layer, series resistance and an inhomogeneous Schottky barrier contacts. Therefore, the insulator layer must be perfectly homogeneous be deprived of defects such as pin-holes with high dielectric breakdown and present very good Si/SiO2 interface. In particular, both the interface states density and the fixed charges density must be low. In addition, the reproducibility and the *

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0167-9317/$ - see front matter  2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.09.008

homogeneous of these properties are essential factors for the reliability and the reproducibility of device performances. Moreover, the thickness of insulator layer must be precisely controlled during the fabrication process. This insulator layer is required to prevent the reaction and the inter diffusion at the interface. There are currently a vast number of reports of experimental studies on Schottky barrier heights in a great variety of MS and MIS Schottky diodes [1–9]. During the elaboration of semiconductor devices of the MS and MIS types, defects appear which lead to electronic states with energies located in the forbidden band, the band gap. These states are known as surface states and alter the functioning of such devices. Surface states originate from defects such as dangling bounds at the insulator/substrate interface with energy states in the Si forbidden band gap and are dependent on the chemical composition of the interface [3,10]. The relationship between the admittance

A. Tatarog˘lu, S ß . Altındal / Microelectronic Engineering 85 (2008) 542–547

543

of the interface state charging process above and the capacitance and conductance of the MIS structure measured in the external circuit has been described and analyzed by Nicollian and Goetzberger [10]. They have observed that the capacitance decreases with increasing frequency. This effect is obtained at low and intermediate frequencies. The interface states can follow the ac signal and yield an excess capacitance, which depends on the relaxation time of the interface states and the frequency of the ac signal. This model can be applied to determine the interface state of a metal-interface layer-semiconductor Schottky diode. The interface states can affect the C–V characteristics of MIS Schottky diode, causing a bending of the C2–V plot as well as affecting the ideality factor. In general, a C–V plot shows an increase in capacitance with an increase in forward bias. However, in recent years, wide acceptance has been gained by the capacitance methods of semiconductor investigation, which allows one to obtain extensive information about the parameters of localized electronic states (or energy levels) [3,11–13]. The reason for their existence is the interruption of the periodic lattice structure at the surface [10,13,15], surface preparation, formation of insulating layer and impurity concentration of semiconductor [11]. These interface states usually cause a bias shift and frequency dispersion of the capacitance–voltage (C–V) curves [14]. Furthermore, the C–f and G–f measurements give the important information about the density of the interface states of the structure. This method is called the conductance method in which is accounted for the interfacial layer capacitance. In general, the C–f and G–f plots in the idealized case are frequency independent [3,4,10,16–19]. However, this idealized case is often disturbed due to the presence of an interfacial layer between the contact materials and interface states at the interfacial layer/semiconductor interface [3,10]. The purpose of this paper is determination of interface states density (Nss) and their relaxation time (s) in Al/ SiO2/p-Si (MIS) structure. The energy distribution of Nss and s are obtained from experimental the forward bias current–voltage (I–V) and C–V and G/x–V measurements.

orated from the tungsten filament onto the whole back surface of the wafer in the pressure of 2 · 106 Torr in oil vacuum pump system. To form ohmic contacts on the back surface of the wafer, we sintered the evaporated aluminum (Al). The oxidations are carried out in a resistance-heated furnace in dry oxygen with a flow rate of a 2 lt/min and the oxide layer thickness is grown at the temperatures of 650 C during 60 min. After, following oxidation, the whole back surface of the quarter wafer after etching away the silicon-insulator from the back in HF and then circular ˚ thick Al contacts are dots of 1 mm diameter and 2000 A deposited onto the oxidized surface of the wafer for through a metal shadow mask in a liquid nitrogen trapped vacuum system in a vacuum of 2 · 106 Torr. Thus, the Schottky contact is made onto the upper electrode on the insulator with the help of fine phosphor–bronze spring probe. The interfacial layer thickness was estimated to be ˚ from measurement of the interface capacitance about 53 A in the strong accumulation region for MIS Schottky diode [10]. The current–voltage (I–V) measurements were performed by the use of a Keithley 220 programmable constant current source, a Keithley 614 electrometer. The capacitance–voltage (C–V) measurements were performed at various frequencies by the use of HP 4192A LF impedance analyzer (5 Hz–13 MHz). For the C–V measurements, small sinusoidal signal of 50 mV peak to peak from the external pulse generator is applied to the sample in order to meet the requirement [13]. All measurements were carried out with the help of a microcomputer through an IEEE-488 ac/dc converter card.

2. Experimental procedure

where q and T are the magnitude of electron charge, the temperature in Kelvin, respectively, VG is the applied voltage, n is the ideality factor and Is is the saturation current expressed by:   qUB I s ¼ AA T 2 exp  ð2Þ kT

The Al/SiO2/p-Si (MIS) structure used in this study were fabricated using boron-doped single crystals silicon wafer with <1 0 0> surface orientation having thickness of 280 lm, 2 in. and 8 X cm resistivity. For the fabrication a process, Si wafer was decreased in organic solvent of CHCICCI2, CH3COCH3 and CH3OH consecutively and then etched in a sequence of H2SO4 an H2O2, 20% HF, a solution of 6 HNO3:1 HF:35 H2O, 20% HF and finally quenched in de-ionised water for a prolonged time. Preceding each cleaning step, the wafer was rinsed thoroughly in de-ionized water of resistivity of 18 MX cm. Immediately after surface cleaning, high purity Al metal ˚ was thermally evap(99.999%) with a thickness of 2000 A

3. Results and discussion 3.1. Current–voltage (I–V) characteristics The determination of the electric parameters was achieved by using the characteristics formula expressing the current passing through a Schottky diode [1,10,13]      qV qV I ¼ I s 1  exp  exp ð1Þ kT nkT

where A is the area of rectifying contact, A* is the effective Richardson constant and equals to 32 A cm2 K2 for ptype Si and UB is the barrier height. The measured of the forward current–voltage characteristics ln[I/(1  exp(qV/kT)] = f (V) of the MIS structure is shown in Fig. 1. The ln[I/(1  exp(qV/kT)] = f (V) curve consist of a linear region, from the slope and y-axis intercept of the linear region yields the ideality factor n

A. Tatarog˘lu, S ß . Altındal / Microelectronic Engineering 85 (2008) 542–547

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where x is the angular frequency, Nss is the density of interface states, A the contact area, q the magnitude of the electronic charge, and s is the interface state life time, referred also time constant, presents the characteristic time required to fill and empty the Nss at various energy levels [23]   1 qV d s¼ exp ð5Þ V th Rs N A kT

Ln [ I/(1-exp(-qVG/kT)) ](A)

-5 -7 -9 -11 -13 -15 -17 -19 0

1

2

3

4

V (V) Fig. 1. ln[I/(1  exp(qV/kT)] variations versus forward bias voltage characteristics of the MIS structure at room temperature.

and the reverse saturation current Is of the MIS structure at 3.05 · 109 A and 1.32, respectively. By substituting the values of Is into Eq. (2), we have deduced the barrier height UB which is about 0.77 eV. For MIS structure this value of ideality factor obtained from the forward bias I–V plot is greater than unity, indicating the presence of a thin interface insulator layer, between the Al layer and p-Si semiconductor. Also, such behaviour of ideality factor has been attributed to particular distribution of the interface states [20], the image-force effect, recombination-generation, and tunnelling may be other possible mechanisms that could lead to an ideality factor value greater than unity [1,4,10,21,22]. It should be noted that the effect of the series resistance in the linear region could be neglected in Fig. 1. 3.2. Capacitance–frequency (C–f) and conductance– frequency (G–f) characteristics The C–V and G–V characteristics at various frequencies can be used to characterize the interface state density (Nss) and their lifetime for MIS structure. In the equivalent circuit of MOS and MIS structure, the interface states are represented by a capacitance Css and conductance Gss in parallel with the semiconductor space-charge capacitance Csc and in series to interfacial insulator layer capacitance Ci. The interface state capacitance Css and conductance Gss of a MIS structure are related to the Nss, and the capture cross-section (rs) and they have been derived by Nicollian and Goetzberger [10,13,22] as AqN ss arctanðxsÞ xs AqN ss Gss ¼ lnð1 þ x2 s2 Þ 2s

C ss ¼

ð3Þ ð4Þ

In the above expression for s, rs represents the capture cross-section of the interface states, Vth is the thermal velocity of the carriers (Vth  107 cm s1), NA the doping concentration and Vd diffusion potential and T is the absolute temperature. The Gss/x versus log(f) curve usually shows a peak. At this peak ½oðGss =xÞ=oðxsÞ ¼ 0 and this maximum condition gives xs = 1.98. Substituting this va  ðGss =xÞmax 3:76 ¼ 0:4029A lue in Eq. (4) one gets N ss ¼ Gxss max qA lnð4:92Þ and interface state time constant s = 1.98/x. The measured conductance G and the junction capacitance C are related to the conductance and the capacitance due to interface states Css, Gss by [24] qI dc C i ðC r þ C ss Þ AkT ðC R þ C ss Þ2 þ ðGss =xÞ2 qI C i Gss =x2 C ¼ dc þ C HF AkT ðC R þ C ss Þ2 þ ðGss =xÞ2

G¼

ð6Þ ð7Þ

with C R ¼ C sc þ C i

ð8Þ

and 1 1 C 1 HF ¼ C sc þ C i

ð9Þ

where Ci is the interfacial-layer capacitance and it is obtained from the high-frequency (1 MHz) values of G and C and Idc is the measured current. Csc is the capacitance of the depletion region. The measured G and C in Eqs. (6) and (7) depend on frequency because Gss and Css depend on frequency and the latter two quantities contain information about the interface states Nss. It is therefore sufficient to extract and analyze Gss. Solving of Eqs. (6) and (7) for Gss yields Gss ¼

qI dc x2 C i ðC  C HF Þ AkT G2 þ x2 ðC  C HF Þ2

ð10Þ

Furthermore, in a p-type semiconductor, to evaluate the distribution of the interface states Nss(Ess  Ev) having energy of Nss, Ess with respect to top of the valance band at the surface of the semiconductor is given by [25,26] Ess  Ev ¼ qðUB  V Þ

ð11Þ

where Ess is the energy of interface states Nss and Ev is the valance bend edge. Fig. 2a and b shows the measured capacitance and conductance as a function of the frequency with bias as a parameter. As seen in Fig. 2a, the measured capacitance decreases with increasing frequency in the frequency range of 100 Hz–1 MHz. Fig. 2a reveals that, the measured

A. Tatarog˘lu, S ß . Altındal / Microelectronic Engineering 85 (2008) 542–547

3.5E-12

3.8E-09 0.20 V 0.25 V 0.30 V 0.35 V 0.40 V

3.0E-09

0.20 V 0.25 V 0.30 V 0.35 V 0.40 V

3.0E-12 2.5E-12

2.3E-09

Gss/ω (F)

C (F)

545

1.5E-09

2.0E-12 1.5E-12 0.2 V

1.0E-12

7.5E-10

0.4 V

5.0E-13

0.0E+00 2

3

4

5

6

log f (kHz)

2

3

4

5

6

log f (Hz)

3.1E-05 0.20 V 0.25 V 0.30 V 0.35 V 0.40 V

2.5E-05

G (S)

0.0E+00

Fig. 3. Measured Gss/x–frequency with bias voltage as a parameters.

1.8E-05

1.2E-05

5.0E-06 2

3

4

5

6

log f (kHz) Fig. 2. Capacitance–frequency and conductance–frequency characteristic with bias as a parameter.

capacitance remained almost constant up to a certain value of the frequency at low frequencies. The higher values of capacitance at low frequencies are due to excess capacitance resulting from the interface states in equilibrium with the p-Si that can follow the ac signal. As the frequency has increased further, the diode capacitance has first decreased sharply and then has decreased monotonically at high frequency as constant. Decreasing values of the capacitance in the intermediate frequency region mean that small part of the interface states can only follow the signal. Furthermore, as can be seen in Fig. 2b, the G–log(f) plot and intermediate frequencies is correlated with the interface states and is often used for the determination of the interface state density [27]. In order to determine interface state density (Nss) of the MIS structure, curves of Gss/x versus log(f) at different biases were plotted in Fig. 3. The quantity of Gss given in Fig. 3 was calculated from the using for forward bias current–voltage (I–V), forward bias capacitance–frequency (C–f) and conductance–frequency (G–f) measurements. As can be seen in Fig. 3, Gss/x versus log(f) gives a peak

for each bias due to the Nss contribution and shifts from high frequency to low with increasing bias. The Gss/x versus log(f) behaviour can be explained by the presence of an almost continuous distribution of interface state energy levels. At a given bias, the Fermi level fixes the occupancy of these interface traps levels, and a particular interface charge density will be at the Si surface which determines the time constant of the related interface states. When an ac signal corresponds to this time constant, the peak loss associated to the interface trap levels will occur. If the frequency is slightly different from the time constant, loses are reduced because trap levels either do not respond or the response occurs at a different frequency. Therefore, the loss peak is a function of frequency. Moreover, the peak value depends on the capture rate, i.e., on the interface state level occupancy determined by the applied bias [10,24,25-28]. As can be seen in Fig. 3, the curves go through maxima at xs = 1.98 with values of (Gss/x)max = 0.4029 qANss [10,22,24]. The ordinates and frequencies of the maxima in the Gss/x versus log(f) plot yield therefore density of the interface states and their relaxation times (s). Then, the dependence of Nss and t on the bias was converted to a function of Ess using Eq. (11) and is shown in Fig. 4. As can be seen from Fig. 4, the Gss/x versus log(f) for different depletion bias show a maximum and with increasing bias, and the peak amplitude, (Gss/x)max, decrease and the frequency (xp) at which the maxima occur moves towards lower value of frequency. This behaviour can be explained by using the interface trap model. The Nss shows a decrease with interface energy from the top of valance band towards the mid-gap, i.e., 9.92 · 1013 eV1 cm2 in (0.37  Ev) eV to 6.91 · 1013 eV1 cm2 in (0.57  Ev) eV. On the other hand, the relaxation time (s) of the interface states shows an increase with interface energy from the top of the valance band towards the mid-gap, i.e., 0.63 · 104 s in (0.37  Ev) eV to 6.31 · 104 s in (0.57  Ev) eV. Thus, it is seen that the s is bias-dependent. The values of interface

A. Tatarog˘lu, S ß . Altındal / Microelectronic Engineering 85 (2008) 542–547

In addition, the depletion layer width (WD) being deduced from the experimental C–V measurements at high frequency is given by [32] sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2es WD ¼ w ð15Þ qN A s

9.95E+13

4.5E-04

8.80E+13

3.0E-04

τ (s)

7.65E+13 1.5E-04

6.50E+13

0.0E+00 0.37

0.42

0.47

0.52

0.57

Ess -Ev (eV) Fig. 4. The energy distribution curves of the interface states and their relaxation times obtained from experimental Gss/x versus x characteristics for the MIS structure at room temperature.

states (Nss) are of order about 1014 eV1 cm2 which is high enough to pin Fermi level of the Si substrate surface [25,29]. The obtained values for Nss and s are the same order as these reported by some authors for MIS structures [22,24,26,30–32]. The energy distribution of interface states (Nss) and relaxation times (s) are shown in Table 1. In Schottky diodes with an interfacial layer, the depletion layer capacitance can be expressed as follows [32]: 1 2ðUB  c2 V  EF Þ ¼ 2 C qes c22 A2 N A

where ws is the surface potential and NA is the carrier concentration. Fig. 5 shows the forward bias C2–V curves of the MIS structure at different frequencies. Fig. 6 shows plots of NA versus frequency and the surface potential versus frequency from the forward bias C2–V curves. The capacitance (C) decreased as a function of frequency due to only small part of the interface states can only follow the signal. This decrease in capacitance of structure implies a widening in the semiconductor depletion layer width. As can be seen from Eq. (15), the increase in the WD results a decrease

5.E+21 4.E+21

2.E+21 1.E+21

ð12Þ 0.E+00 -1.0

2

3

where Nv = 1.38 · 10 cm is the state density in the valence band [33]. Therefore, UB can be given as follows: UB ¼ c2 V 0 þ EF

ð14Þ

-0.6

-0.2

0.2

0.6

1.0

V (V) 2

Fig. 5. The forward bias C –V characteristics of the MIS structure at different frequencies.

1.5E+14 0.95

1.4E+14

NA (cm-3)

Furthermore, as can be seen from this expression, the C – V plot is a straight line, the intercept of which with the Vaxis gives the value of V0. The parameter c2 is a parameter inverse of n. EF is the potential difference between the Fermi level and the top of the valence band in the neutral region of p-Si and can be calculated from the carrier concentration (NA); it is obtained from the following relation:   kT NV ln EF ¼ ð13Þ q NA 19

3.E+21

10 kHz 20 kHz 50 kHz 70 kHz 100 kHz 200 kHz 500 kHz 700 kHz 1 MHz

0.85

1.2E+14

ψs (eV)

Nss (eV-1cm-2)

6.0E-04

C-2 (F-2)

546

1.1E+14

0.75

9.0E+13 Table 1 The experimental parameters obtained of Al/SiO2/p-Si MIS structure VG (V)

Ess  Ev (eV)

Nss (eV1 cm2)

s (s)

0.20 0.25 0.30 0.35 0.40

0.57 0.52 0.47 0.42 0.37

6.91 · 1013 7.51 · 1013 8.26 · 1013 9.17 · 1013 9.92 · 1013

6.31 · 104 4.50 · 104 3.15 · 104 1.58 · 104 0.63 · 104

0.65

7.5E+13 6.0E+13

0.55 10

50

100

500

1000

f (kHz) Fig. 6. The values of NA and ws versus frequency curves obtained from the forward bias C2–V curves of MIS structure.

A. Tatarog˘lu, S ß . Altındal / Microelectronic Engineering 85 (2008) 542–547

in capacitance. As a result, the decrease in capacitance results an increase in frequency. Therefore, the surface potential (Ws) increases with increasing frequency as can be seen from Fig. 6. In addition, the broad peak in the Gss/x (Fig. 3) is attributed to the fluctuation of Ws which is due to non-uniformities in oxide charge and interface states. As can be seen from Figs. 5 and 6, the slope of C2–V curves, NA decrease with increasing frequency. This case can be explained by whether the interface state charges contribute to the diode capacitance or the charge at the interface states can follow an alternating-current signal. Usually, at the interfacial and layer semiconductor interface, there are various kinds of states with different lifetimes. At low frequencies, all the interface states affected by the applied signal are able to give up and accept charges in response to this signal. The interface state capacitance appears directly in parallel with the depletion capacitance, and these results in a higher total value of the capacitance for Schottky diodes than if no interface states were present. At intermediate frequencies, some, but not all, of the interface state charge will participate in small signal measurements, and values of the capacitance observed will be between the low and high frequency values. If the capacitance measurements are made at sufficiently high frequencies, the interface state charges do not contribute to the diode capacitance. This will occur when the time constant is too long to permit the charge to move in and out of the interface states in response to an applied signal [23,27,34,35]. 4. Conclusion In this study, the density of the interface states and their relaxation time were characterized using the C–V and G/x– V characteristics of Al/SiO2/p-Si (MIS) structure at different frequencies have been taking into account the forward bias I–V data. The values of ideality factor and barrier height have been calculated as 1.32 and 0.77 eV, respectively. The applied bias voltage drops partially across the interface layer causing the forward current to drop, thus producing a strong deviation from the ideal I–V characteristics. The interface state density (Nss) was found to vary from about 6.91 · 1013 eV1 cm2 in (0.57  Ev) eV to 9.92 · 1013 eV1 cm2 in (0.37  Ev) eV. Furthermore, the relaxation time changes from 6.31 · 104 s in (0.57  Ev) to 0.63 · 104 s in (0.37  Ev). In conclusion that, the Nss shows a decrease with interface energy from top of Ev towards the mid-gap of Eg, where as s rises from Ev towards the mid-gap of Eg. The higher values of capacitance at low frequencies were attributed to the excess capacitance resulting from the Nss, which are in equilibrium with the semiconductor that can follow the ac signal. We conclude that prepared MIS Schottky diodes have been controlled by the insulator layer and

547

interface states, which are responsible for the non-ideal behaviour of I–V and C–V characteristics. Acknowledgements This work is supported by Turkish of Prime Ministry State Planning Organization Project No. 2001K120590 and Gazi University Scientific Research Project (BAB) FEF-Research Project FEF.05/2007-17. References [1] E.H. Rhoderick, R.H. Williams, Metal–Semiconductor Contacts, second ed., Clarendon Press, Oxford, 1978. [2] A.M. Cowley, S.M. Sze, J. Appl. Phys. 36 (1965) 3212. [3] S.M. Sze, Physics of Semiconductor Devices, second ed., John Wiley & Sons, New York, 1981. [4] P. Chattopadhyay, A.N. Daw, Solid State Electron. 29 (5) (1986) 555. [5] A. Singh, K.C. Reinhardt, W.A. Anderson, J. Appl. Phys. 68 (7) (1990) 3478. [6] P. Cova, A. Singh, R.A. Masut, J. Appl. Phys. 82 (10) (1997) 5217. [7] H.C. Card, E.H. Rhoderick, J. Phys. D: Appl. Phys. 4 (1971) 1589. [8] Z. Quennoughı, Phys. Status Solidi A 160 (1997) 127. [9] A.S. Bhuiyan, A. Martinez, D. Esteve, Thin Solid Films 161 (1988) 93. [10] E.H. Nicollian, A. Goetzberger, Bell Syst. Tech. J. 46 (1967) 1055. [11] U. Kelberlau, R. Kassing, Solid State Electron. 22 (1) (1979) 37. [12] H. Deuling, E. Klausmann, A. Goetzberger, Solid State Electron. 15 (5) (1972) 559. [13] E.H. Nicollian, J.R. Brews, MOS Physics and Technology, John Wiley & Sons, New York, 1982. [14] S. Kar, W.E. Dahlke, Solid State Electron. 15 (1972) 221. [15] R. Castagne, A. Vapaille, Surf. Sci. 28 (1) (1971) 157. [16] S.R. Forrest, P.H. Schmidt, J. Appl. Phys. 59 (1986) 513. [17] J.H. Werner, K. Ploog, H.J. Queisser, Phys. Rev. Lett. 57 (1986) 1080. [18] N.D. Nguyen, M. Germain, M. Schmeits, B. Schineller, M. Heuken, J. Appl. Phys. 90 (2001) 985. [19] S. Kochowski, B. Paszkiewicz, R. Paszkiewicz, Vacuum 57 (2000) 157. [20] A. Tatarog˘lu, S ß . Altındal, Microelectron. Eng. 83 (2006) 582. [21] S. Aydog˘an, M. Sag˘lam, A. Tu¨ru¨t, Polymer 46 (2005) 10982. [22] B. Akkal, Z. Benamara, B. Gruzza, L. Bideux, Vacuum 57 (2000) 219. [23] P. Chattopadhyay, B. RayChaudhuri, Solid State Electron. 36 (1993) 605. [24] J. Werner, K. Ploog, H.J. Queisser, Phys. Rev. Lett. 57 (1986) 1080. [25] M. C ¸ akar, A. Tu¨ru¨t, Synth. Metals 138 (2003) 549. [26] M.K. Bera, S. Chakraborty, S. Saha, D. Paramanik, S. Varma, S. Bhattacharya, C.K. Maiti, Thin Solid Films 504 (1–2) (2006) 183. [27] L. Beji, T. Ben Jomaa, Z. Harrabi, A. Laribi, A. Missaoui, A. Bouazizi, Vacuum 80 (5) (2006) 480. [28] P.L. Hanselaer, W.H. Lafle´re, R.L. Van Meirhaeghe, F. Cardon, J. Appl. Phys. 56 (1984) 2309. [29] N. Konofaos, Microelectron. J. 35 (2004) 421. [30] M. C ¸ akar, A. Tu¨ru¨t, Y. Onganer, J. Solid State Chem. 168 (2002) 169. [31] A. Tatarog˘lu, S ß . Altındal, Microelectron. Eng., in press. [32] M. C ¸ akar, M. Biber, M. Sag˘lam, A. Tu¨ru¨t, J. Polym. Sci. B 41 (2003) 1334. [33] W. Mo¨nch, Semiconductor Surfaces and Interfaces, second ed., Springer-Verlag, Berlin, 1995. [34] R.T. Tung, Mater. Sci. Eng. R 35 (2001) 1. _ Do¨kme, Solar Energy Mater. Solar Cells [35] S ß . Altındal, A. Tatarog˘lu, I. 85 (2005) 345.