The PCB connector as a surface mounted device

World Abstracts on Microelectronics and Reliability analyze pieces of real product processes. Industry or university scientists simulate the production process closely by using sophisticated analytical tools appropriately instrumented. This results in fundamental understanding of the sequence of events occurring in each process step in the production line. Understanding leads to better definintion of process windows and better control of the process. Parts may be processed on the production line or on the laboratory equipment for direct comparison of particular production steps. Teamwork among researchers and an interdisciplinary group of development and manufacturing engineers is a key ingredient to success. High-accuracy die-bonding technology for LED array. HIROSHI TANABE, ISAO SHIBATA, KOHJI NIHEI and KIYOSHI Mr'Am. IEEE Trans. Compon. Hybrids mfg Technol. CHMT-8 (4), 500 (1985). A die-bonding technology was developed and includes (1) high-accuracy, full cutting of a light-emitting diode (LED) array on a GaAsP substratc with a dicing saw; (2) screen printing of a B-stage curing, Ag-filled epoxy resin on alumina ceramic substrate on which a thick-film gold conductor is formed; (3) loading and fixing of the aforementioned ceramic substrate onto the die-bonder heater stage; and (4) die bonding by maintaining the spatial position of the LED array with five tools if the die bonder until the epoxy resin is thermally cured. The highly accurate positioning and stable conductivity of the die bond is ensured by reducing the dispersion of positional error between the LED array and ceramic substrate to within + 10/~m and providing stable ohmic contact characteristics between the LED array and ceramic substrate. The PCB connector as a surface mounted device. WILLIAMJ. CLARK. IEEE Trans. Compon. Hybrids mr# Technol. CHMT8 (4), 530 (1985). The problems and solutions relative to the design of PCB connectors for surface mounting are explored. The systems approach is discussed because surface mount technology (SMT) for connectors is largely driven by the need for minimum labor, and automated production lines. Therefore, the design must consider the application of the connectors by robots. This in turn brings about the need to consider how to package the connectors for presentation to the robot, how to identify the connector, and how the connector can be picked up by the robot arm, consistently. Once on the board, the effect of large mating and unmating forces must be brought into the equation. The connector must be held down by some mechanical means, which must also be compatible with the capabilities of the robot. These problems are all explored. Answers to the design problems are put forth, the conclusion being that all technologies are presently available to make the SMT connector a viable product family. Packaging technology for the NEC SX supercomputer. TOSHI:41KO WATARI and HIROSHI MURANO. IEEE Trans. Compon. Hybrids mr# Technol. CHMT-8 (4), 462 (1985). Technological considerations in realizing high-speed supercomputers arc presented, focusing on large-scale integrated (LSI) chips, new circuit packaging technology, and a liquid cooling system. The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 mcgaflops processing speeds with a 6-us machine cycle. This new technology features a 1000-gate current mode logic (CML) LSI with 250 ps gate delay as a logic element, a 1 kbit bipolar memory with 3.5 ns access time for cache memory and vector registers, a 10cm 2 multilayer ceramic substrate with thin film lines (25/~m width, 75,um center-to-center), and a multichip package which contains up to 36,000 logic gates. A liquid cooling module is implemented for highdensity high-efficiency heat-conductive packaging for the arithmetic processor. In addition, high-density high-speed packaging of 64kbit static metal-oxide semiconductor (MOS) RAM's are used to implement large-capacity fast main memory. MR 27:2-M

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EPIC: a cost-effective plastic chip carrier for VLSI packaging. NIHAL SINNADURAL 1EEL Trans. Compon. Hybrids mfg Technol. CHMT-8 (3), 386 (1985). With the continuing growth in complexity of very large-scale integrated (VLSI) chips, there are increasing demands for high-performance high-pin-count micropackages capable of providing high reliability protection of the chips without being unduly costly. Studies have confirmed that plastic encapsulants, particularly silicones, can provide very high reliability protection indeed. These observations led to the concept of a new plastic chip carrier, named the "EPIC," fabricated by printed circuit board technologies, which has been developed to be suitable for automated bonding and encapsulation of chips into the package, and for subsequent automated surface-mounted assembly of the EPIC onto circuit boards. Reliability evaluations of the EPIC, in comparison with established commercial small outline (SO) plastic micropackages, have demonstrated that high reliability is attainable with EPIC chip carriers and also SO packages from a few sources. Performance measurements have revealed the outstandingly better electrical performance of the EPIC over ceramic equivalents, and versions of EPIC can achieve equivalent or better thermal resistances. Cost analyses show that the EPIC starts with an intrinsically low cost and can achieve very high terminal counts (exceeding 200) while maintaining the cost advantage. Thus high performance and reliability of VLSI packaging is achievable cost-effectively. Low-stress resin encapsulants for semiconductor devices. K. KUWATA, K. IKO and H. TABATA. IEEE Trans. Compon. Hybrids mfg Technol. CHMT-8 (4), 486 (1985). An innovative low-stress epoxy encapsulant was developed for large and stress-sensitive devices by the utilization of silicone modification technology. The characteristics can be explained by achieving a lower Young's modulus and thermal expansion coefficient. The low-stress level was confirmed by piezoresistance measurement with actual results showing a definite, significant improvement against package and passiration cracks. An interesting microstructure of the new material was determined and labeled "Sea-Island" structures. Improving thermosonic gold ball bond reliability. TOM D. HUND and PAUL V. PLUNKETT. IEEE Trans. Compom. Hybrids mfg Technol. CHMT-8 (4), 446 (1985). A comprehensive study using normal probability paper to project gold wire bond reliability has been performed. Reliability projections have been made using ceramic capillaries, tungsten carbide capillaries, gold wire, gold/palladium alloy wire, three different device metallizations, nine different wire lot numbers, and seven ultrasonic power settings. The reliability projections from all of the tests were then compared to the ball shear force from each test to correlate shear force with reliability. The results indicate that several orders of magnitude increase in reliability can be achieved from using optimum wire bond parameters. The ball shear force value has also been shown to be very useful in predicting reliability and thus eliminating time consuming wire pull tests. A new scheme for device packaging. ABRAHAMAUERBACH. IEEE Trans. Compon. Hybrids mfg Technol. CHMT-8 (3), 309 (1985). A new method for forming low resistivity conductors in a doped polymer film has been used in a novel device packaging scheme. In a first application, the focused output of a laser is used to write silver connections between device bonding pads and package conductors to fabricate a working clock. How to calculate the true permissible leak rate and how to raise it by four orders of magnitude. J. GORDON DAVY. IEEE Trans. Compon. Hybrids mfg Technol. CHMT-8 (3), 359 (1985). This paper is in two parts. The first part presents bad news and the second part good news. The bad news is that