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Thermal and mechanical analysis of high-power GaAs flip-chips on CVD diamond substrates
Diamond and Related Materials 8 (1999) 1927–1935 www.elsevier.com/locate/diamond
Thermal and mechanical analysis of high-power GaAs flip-chips on CVD diamond substrates M.D. Brown, S.B. Singh, A.P. Malshe*, M.H. Gordon, W.F. Schmidt, W.D. Brown High Density Electronics Center (HiDEC), Department of Electrical Engineering, Department of Mechanical Engineering, University of Arkansas, Fayetteville, AR 72701, USA Received 5 January 1999; accepted 7 June 1999
Abstract Using numerical, analytical and experimental methods, we evaluate the structural and thermal performance of a large, 1 cm×1 cm, GaAs die, flip-chip attached to 2.54 cm×2.54 cm diamond substrates. In agreement with numerical predictions, the GaAs dice’s induced stress during the attachment process — 37Pb/63Sn solder reflow and high-temperature underfill cure — is below the fracture strength of GaAs. However, as numerically predicted, the stress in the dice is higher for underfilled chips. This larger stress is measured indirectly through stylus profilometry where we experimentally determine the die deflection. The underfilled chips deflect more, which correlates with higher die stress. Both analytical and numerical results confirm this conclusion. Experimental and numerical thermal studies demonstrate the importance of the case-to-ambient thermal resistance (h ). For our ca package, diamond offers tremendous thermal advantage only for h values less than 1°C W−1 and offers little to no advantage ca for h values greater than 10°C W−1. © 1999 Elsevier Science S.A. All rights reserved. ca Keywords: Diamond; Finite element modeling; Flip-chip; Gallium arsenide; Profilometry; Thermal management
1. Introduction Excessive operating temperature is a common cause of device failure due to increased intrinsic carrier concentrations in semiconductor devices and thermal cycle fatigue of solder joints. To reduce junction temperatures, chemical vapor deposited synthetic diamond (CVDD) — due to its high thermal conductivity (~1000 W m−1 °C−1) and high electrical resistivity (~1013 V cm) — has been proposed for use as a heatspreading substrate material in single-chip and multichip module (MCM ) packages. Diamond substrates allow devices to be packaged in denser, closer-packed arrangements, thus reducing physical size and electrical conduction path lengths; however, the high cost of diamond limits its use to select, high-performance packages. High-power, edge-cooled, two-dimensional (2D) and three-dimensional (3D) diamond-based MCMs have previously been evaluated [1–3], and high-power, single-chip packages involving face-up and flip-chip * Corresponding author. Tel.: +1-501-575-6561; fax: +1-501-575-8720/6982. E-mail address: [email protected] (A.P. Malshe)
GaAs dice attached to diamond have also been thermally investigated [4,5]. In these studies, thermal modeling has typically employed an isothermal boundary condition to simulate cooling. In our work, an investigation of the case-to-ambient thermal resistance (h ) was perca formed to evaluate the impact of cooling resistance on the thermal enhancement capability of diamond substrates in 2.54 cm×2.54 cm single-chip packages. In particular, we investigate the performance of diamond-based, high-power, high-speed, flip-chip packages. The flip-chip die attachment method has the excellent characteristics of high input/output (I/O) capability and low interconnect inductance. Heat, in most cases, is removed from the open back side of the die through an attached heat sink arrangement. However, in the case of substrate cooling, necessiated by weight and/or space constraints, heat dissipation can be a problem since the flip-chip attachment layer is not continuous. Thus, the flip-chip bumps become a heat flow ‘bottleneck’. Finite element analysis ( FEA) modeling has shown that the use of thermally conductive underfill material can reduce the flip-chip die attach’s thermal resistance enough to be comparable to wire-bond thermal performance [5], and the use of diamond as the substrate material can
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significantly increase heat dissipation capability without the need for substrate thermal vias. Although diamond’s high thermal conductivity clearly offers a significant thermal advantage, its stiffness (E~1180 GPa) can pose structural problems in applications involving coefficient of thermal expansion (CTE) mismatches. Silicon (CTE~2.6 ppm °C−1) matches well with diamond (CTE~2.0 ppm °C−1), but GaAs (CTE~5.6 ppm °C−1) does not, and excessive tensile thermomechanical stresses within the die at the attachment interface are common [2,6,7]. In our work, structural finite element, analytical and experimental analyses were conducted for a single-chip package involving a flip-chip GaAs die attached to diamond to evaluate the structural response of the package during cooling from the solder reflow and during underfill cure processes. The experimental analysis was used to verify theoretical predictions for GaAs die deflection using simple, stylus profilometer measurements. Though in situ die stress measurements can be made using piezoresistive tests [8], the development of such test chips for a particular application is time consuming and costly. Instead, die deflection interferometry measurements are often reported for model verification [9,10]. Presented in our work are die deflection measurements taken with a standard, clean-room profilometer which simplifies the experimental process. CTE mismatched components also lead to thermal cycle fatigue. The on/off cycles of a device produce expansions and contractions of the die and substrate which can result in cyclic, plastic straining of the attach material. In this situation cracks develop and propagate, eventually causing low-cycle fatigue failure of the device. In the case of flip-chip die attachment, underfill is frequently used to extend the fatigue life of the solder bumps. Two-dimensional FEA models were used in our work, in conjunction with the Coffin–Manson relation [11], to estimate the effect of underfill on the fatigue life of the GaAs-on-diamond package.
2. Numerical modeling FEA is used to evaluate the thermal and structural performance of substrate material in the flip-chip configurations. Solder bump fatigue modeling is also carried out using FEA to quantify the benefit of underfill for increasing solder bump fatigue life in flip-chip attachment of GaAs to a diamond substrate. The modeling is performed using the commercially-available FEA software (version 5.3). 2.1. Thermal modeling An investigation of the case-to-ambient thermal resistance was performed to evaluate the impact of cooling
resistance on the thermal enhancement capability of diamond substrates in 2.54 cm×2.54 cm single-chip packages. Although a constant-temperature boundary condition approach to thermal modeling simplifies the analysis for the purpose of relative comparisons, it simulates an ideal case-to-ambient thermal cooling resistance (h =0°C W−1) and is not realistic. Instead, to ca avoid modeling complex heat sink geometries, an effective heat transfer coefficient was defined and varied to simulate non-zero h values ranging from ca 0.0001°C W−1 (approximately ideal ) to 10 000°C W−1 (approximately insulated ) on the edge-cooling surfaces of a single-chip, flip-chip package ( Fig. 1). The edgecooled substrate simulates a high-density package such as a three-dimensional stack of substrates having edges clamped into a water-cooled rack. 2.2. Numerical die stress modeling To investigate the structural effects of underfill in the 1 cm×1 cm, high input/output, GaAs-on-diamond flipchip die attachment, a one-quarter, 3D FEA model was constructed. To reduce model complexity, solder bumps were modeled as blocks instead of the actual truncated, spherical shapes. Since 3D structural analyses are vectorfield problems in which each node has three degrees of freedom, the FEA modeling is substantially more computationally intensive than is steady-state thermal analysis with just one degree of freedom per node. Material nonlinearities further complicate the analysis. To reduce solution times and required memory space, a strip was cut from the one-quarter model along the x-axis at the center of the package. Fig. 2 shows the meshed strip model which contains one row of 14 solder bumps and is three elements wide with a total of 3570 elements. Boundary conditions are identical to those on the onequarter model. Solution comparisons between the onequarter and strip models showed that the strip model consistently yielded maximum normal die stress values 20–30% lower than the one-quarter model predictions. For parametric modeling of GaAs die stress after cooling from reflow and underfill cure conditions, a worst-case situation of rapid cooling, without the benefit of solder creep, was assumed. Temperature-dependent, bi-linear solder plasticity was input into the model according Dasgupta et al. [12]. Linear material properties are given in Table 1. Note that the assumed reference (zero stress) temperature for the solder reflow model is the melting temperature for 37Pb/63Sn solder (183°C ), and for the underfill cure process it is the underfill’s glass transition temperature (T =140°C ) [9]. Due to g the rapid, high-temperature creep of lead–tin solder, it was assumed that the package relaxed to a zero stress state during underfill cure. From each solution, normal, element die stresses were recorded along the x-axis at the die/die attach interface since this is the critical
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Fig. 1. Diagram of the one-quarter FEA thermal model.
location where tensile stresses from the bending moment and the tensile forces are maximum. 2.3. Analytical die stress modeling An analytical, bonded assembly die stress model was developed by Schmidt [17] using beam theory and gives the normal stress in the die as:
A
B
1 3D (t +t ) DaDT s = − + 1 1 2 X(x), (1) 1 t D +D Kk2 1 1 2 where the subscripts 1 and 2 indicate die and substrate components, respectively; t represents component thicki
ness; and D represents the component flexural rigidity i for a unit width strip model as defined below: E t3 i i D= . (2) i 12(1−n3 ) i E represents Young’s modulus; n represents Poisson’s i i ratio; Da represents the difference in CTE between die and substrate; DT represents the temperature change between cure and room temperature; and K is the sum of K (attachment shear compliance), K (die shear 0 1 compliance) and K (substrate shear compliance) and 2 represents the interfacial shear compliance where: 2(1+n )t 2t i i. (3) K = 0; K= i 0 3G 3E 0 i In the above, G represents the shear modulus for the 0 attachment layer, t represents the thickness of the 0 attachment layer, k2 is the sum of l (die axial compli1 ance), l (substrate axial compliance) and l (bending 2 12 compliance) divided by K where: 1−l (t +t )2 i; l = 1 2 l= . (4) i 12 Et 4(D +D ) i i 1 2 Finally, X(x)=1−[cosh(kx)/cosh(kl )] and represents the functional variation of stress with x measured from the die center to the die edge. Note that the overall die length is defined to be 2l. 2.4. Solder bump fatigue modeling
Fig. 2. 3D structural FEA strip model of flip-chip GaAs-on-diamond.
The 1 cm×1 cm×600 mm GaAs dice are attached to the substrates using 784 electroplated Pb/Sn solder
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Table 1 FEA linear material properties
37Pb/63Sn Underfill GaAs CVDD Silicon
Coefficient of thermal expansion, a (ppm °C−1]
Poisson’s ratio, n
Young’s modulus, E (GPa)
Thermal conductivity ( W m−1 °C−1]
24.7 26 5.58 2 2.6
0.4 0.4 0.3 0.148 0.3
33.9 10.0 123 1180 167
35 2 45 1000 150
bumps with a 357 mm pitch. The bump stand-off height is 50 mm, and the bump diameter is about 100 mm. To quantify the benefit of underfill on increasing solder bump fatigue life in the flip-chip GaAs-on-diamond package, two-dimensional, plane strain models were constructed for the above parameters. Two-dimensional models were used since time-dependent creep calculations require lengthy computational time in 3D models. Creep was input as a solder bump material property through a secondary creep FEA option using the Wertmann–Dorn relationship that follows: AGb
e˙ = (b/d )p(s/G )nD e(−Q/RT), 0 s kT
following Coffin–Manson relation: N =h(Dc )w, (6) f p where N represents the number of cycles to failure, f Dc represents the plastic strain range, and h and w p represent material constants (h=1.2928 and w=−1.96 for 37Pb/63Sn solder [13]).
3. Experimental procedure 3.1. Thermal experimentation
(5)
where, for 37Pb/63Sn solder, e˙ represents the steadys state creep rate (s−1), A represents a dimensionless constant (40), G represents the temperature-dependent shear modulus (2.2×104−16.1T( K ), in MPa), b represents the Burger’s vector magnitude of crystal dislocation (3.2×10−7 mm), k represents the Boltzmann constant (1.38×10-23 J K−1), T represents the absolute temperature ( K ), d represents the grain size (5.5×10−3 mm), p represents the grain size exponent (1.6), s represents the applied stress (MPa), n represents the stress exponent (2.4), D represents the pre-exponen0 tial constant (100 mm2), Q represents the activation energy for a rate-limiting diffusion process (44 000 J mol−1), and R represents the gas constant (8.314 J K−1 mol−1). Solutions for cooling rates of 0.5°C s−1 from the chosen operating temperatures to an ambient state of 50°C were used to obtain shear displacements of the solder bump at the edge of the die where the maximum shear occurs. To improve fatigue life calculations, the shear displacement solutions (using block shaped bumps) were input as boundary conditions on a more accurate single 2D bump model ( Fig. 3). This bump model contains 25 mm sections of the die and substrate and 2 mm copper bump pads, and it can be configured with or without underfill material. The maximum absolute plastic shear strains were recorded from model solutions (for example, Fig. 4) to calculate of joint fatigue life using the
For experimental study of the edge-cooled substrate application and for verification of the FEA modeling, a liquid-cooling system was designed to provide heat removal from the edges of 2.54 cm×2.54 cm substrates using water as the cooling fluid. A schematic view of the test vehicle’s cold chucks and the operating ‘package’ is shown in Fig. 5. Two substrates were tested, CVD diamond and silicon, and each had a thickness of about 700 mm. The CVD diamond substrates used in our work are from Norton Diamond Film, and their average temperature-independent properties (sufficient for this study) are listed in Table 1 along with those of silicon. The 1 cm×1 cm×600 mm GaAs dice are attached to the substrates using 784 electroplated Pb/Sn solder bumps with a 357mm pitch. The bump stand-off height is 50 mm, and the bump diameter is about 100 mm.
Fig. 3. 2D FEA model of one flip-chip solder bump.
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Fig. 4. FEA solution for plastic shear strain distribution in a 37Pb/63Sn, GaAs-on-diamond flip-chip solder bump subject to deformation predicted from the one-quarter model with block shaped bumps.
Power (q) was input via a pre-packaged power metal oxide semiconductor field effect transistor (MOSFET ) device (1.9 cm×1.3 cm) due to a lack of interconnection lines on diamond and silicon substrates. To accurately represent the model geometry, a 1 cm×1 cm dummy die was ‘sandwiched’ between the MOSFET and the substrate to ensure that the heat flux was introduced over a 1 cm×1 cm area. The substrates were attached to the aluminum cold chucks at two opposing sides on 1 mm ledges, as shown in Fig. 5. Thermal grease and pressure (~9 psi, applied manually) were applied to all interfaces to ensure good thermal contacts. Owing to the use of the MOSFET as the power source, a location for taking an ‘on-chip’ or junction temperature measurement was not available. Therefore, temperature was measured on the underside of the substrate directly beneath the power source at the center of the substrate. Temperature was also measured in a small cavity at the interface between the substrate’s edge and the cold chuck. These two package temperatures were recorded using type K thermocouples having beads
coated with thermal grease. The temperature at the center of the substrate provided a value to compare with model predictions, and the difference between the substrate edge temperature (T ) and the coolant temper1 ature (T ) provided a means of calculating h 2 ca [(T −T )/q]. 1 2 3.2. Structural experimentation To investigate the underfill flip-chip attach experimentally, 1 cm×1 cm×600 mm GaAs dummy dice were bumped with a full array (357 mm pitch) of 784 electroplated, Pb/Sn solder bumps, approximately 70 mm tall and 100 mm in diameter. The under-bump metallurgy was sputtered titanium/copper, and the array pattern was defined using photo-definable benzocyclobutene (BCB). CVD diamond substrates, 700–900 mm thick, were sputtered with a Ti/Cu/Ti metallization scheme to provide bondable metallization. The top layer of titanium was patterned to define the pad array since titanium is not a Pb/Sn solder-wettable metal. After reflow
Fig. 5. Schematic illustration of the MOSFET-powered edge-cooling apparatus.
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attachment, the bump stand-off height was about 50 mm. The attachments were underfilled and cured at 165°C. Once cooled, the dice were scanned using a stylus profilometer to examine die bending as a result of the CTE mismatch between GaAs and diamond. These die deflection scans were made over the backs of the flipchip dice in both in-plane directions (x and y) from side to side, not corner to corner. Vertical displacement of the die, defined as the difference in elevation between the center and edge, was obtained by averaging these measurements and compared with model predictions.
4. Results and discussion The thermal results for diamond (2.54 cm×2.54 cm) and silicon (2.54 cm×2.54 cm) substrates are presented in Fig. 6 for the parameter values given in Table 1. For the three experimental steady-state cooling conditions [no coolant flow, low flow (0.001 kg s−1) and high flow (0.01 kg s−1)], for substrate temperatures 50°C above ambient, good agreement with the numerical predictions is observed. In general, we see that diamond offers little to no advantage for h greater than 10°C W−1. ca However, for h less than 1°C W−1 (obtained with a ca liquid-cooled fixture), diamond offers tremendous thermal advantages. To achieve lower cooling resistance, techniques such as direct immersion cooling and microchannel cooling have been investigated [14,15]. For cooling resistances of less than 10−2 °C W−1, the edgecooled diamond substrate package provides a factor of five improvement over silicon. Fig. 7 compares the maximum normal stresses within the die after solder reflow and underfill cure processes for varying geometric configurations. As expected, larger
Fig. 6. Comparison of MOSFET-powered device and FEA for dissipated power (50°C junction temperature rise over ambient) as a function of cooling resistance for the edge-cooled substrate configuration.
die thickness, larger stand-off heights and smaller die sizes all lead to lower die stress for both solder reflow and underfill curing. However, larger substrate thickness leads to lower solder reflow stress but higher underfill cure stress. With underfill coupling the die and substrate, the result is as expected. Larger and thus stiffer substrates increasingly restrict the die from reaching its stress-free configuration. Thus, the die stress increases. With no underfill, thicker substrates lead to less package bending and thus less bending stress. Hence, the normal stress, a combination of axial and bending stress, decreases. It is also observed that, in general, the underfill cure stresses are higher, but none of the stress values exceed the fracture strength of GaAs (approximately 85 MPa [16 ]) even considering the 30% underestimation of the strip model. Our experimental fabrication has confirmed this conclusions. For thin substrates, thin dice and large die sizes, however, the solder reflow stress is larger than the underfill cure stress. These parameter values lead to high aspect ratios ( length/thickness) and significant package bending. Since plastic deformation of solder bumps relieves the axial die stress component, the bending component is dominant in the solder reflow process. Although not shown in Fig. 7, we also varied the solder bump stiffness (from 10 to 50 GPa) and found very little change (1%) to the underfill cure die stress. In fact, a strip model without any solder bumps produced approximately the same solution as the base case model with solder bumps. For completeness, the onequarter, 3D model was also solved with the highly nonlinear solder bumps and is in excellent agreement with the analytical solution [Eq. (1)] that does not include the bumps (Fig. 8). The maximum normal die stress of 43.8 MPa is consistent with the 30% approximate underestimation of the strip model prediction (30.3 MPa). These results confirm that the structural response of underfilled dice is dominated by the underfill material [8,9]. Thus, the die stress in the underfilled 37Pb/63Sn flip-chip GaAs-on-diamond die attachments can be modeled accurately using the analytical expression, even for high I/O counts. Since the above stress predictions are based on numerical and analytical calculations, we indirectly and experimentally investigated the underfill die attach stress by measuring die deflection using stylus profilometry. In addition, we compare these measurements against the following analytical die deflection prediction (see Ref. [6 ], p. 43): DaDT(t +t )l2 1 2 w =− max 4(l +l +l ) (D +D ) 1 2 12 1 2 2[cosh(kl )−1] × 1− . (kl )2 cosh(kl )
A
B
(7)
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Fig. 7. FEA results from 3D strip model for normal die stress at the die/die attach interface in a GaAs-on-diamond flip-chip die attachment. Result are for solder reflow conditions (SR) and underfill cure conditions ( UC ) for various configurations.
The results are shown in Fig. 9 for substrate thicknesses of 700 mm, 800 mm and 900 mm and a cure temperature of 165°C. As a control, note that we measured a maximum vertical displacement of about −0.2 mm (see inset picture in Fig. 9 for position of measurement). This concave-down deflection was most likely a result
Fig. 8. Comparison of one-quarter, 3D FEA and analytical normal die stress at the die/die attach interface in a GaAs-on-diamond flip-chip die attachment after underfill cure.
of metallization-induced stress. Other bonded dice deflections were corrected to account for this effect by adding the magnitude of the unbonded dice deflection. Immediately after experiencing the underfill cure cooldown, the non-underfilled dice showed vertical displacements ranging from 1 to 2 mm depending upon substrate thickness (not shown in Fig. 9). However, the underfilled
Fig. 9. Comparison of analytical and experimental die deflection measurements for a 165°C cure temperature.
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Fig. 10. 2D FEA maximum 37Pb/63Sn solder bump shear displacement as a function of DT with and without underfill.
dice profiles show vertical displacements of 3–5 mm. These results support the modeling conclusion that underfill leads to higher die stress because it limits the die stress-relieving solder bump deformation. Although the underfill leads to higher die stress, it minimizes the solder bump shear displacement, which increases reliability. Fig. 10 shows the FEA maximum bump shear displacements for various temperature changes between off and on conditions, and confirms that the underfill decreases the bump displacement. To calculate predicted cycles to failure, the maximum plastic shear strain value is needed as input to the Coffin–Manson relation [Eq. (6)]. As noted previously, the maximum shear displacement was found by solving the one-quarter flip-chip FEA model. This maximum shear displacement was then used as a boundary condition on a single-bump FEA model (Fig. 3) to solve for the maximum absolute plastic shear strain value (Fig. 4). For a 20°C cycle, the single-bump FEA model results for plastic shear strain for the no-underfill and underfilled cases were 2.20×10−2 and 6.99×10−3, respectively. Based on these results, we estimated the number of cycles to failure to be 10 850 and 1143 cycles for packages with and without underfill, respectively. Note that we have divided the predicted cycles to failure by two to obtain a predicted number of complete ‘on/off ’ cycles to failure (assumes absolute strain to be identical for positive and negative displacement). This reliability improvement of about an order of magnitude demonstrates the benefit of underfill for GaAs-on-diamond flip-chip packages.
ment to diamond substrates and subsequent high-temperature underfill cure. This survival has been confirmed experimentally. The modeling has also shown that the underfilled flip-chip die-attachment layer, though having a high I/O bump count, can still be considered a continuous layer of underfill, disregarding the bumps, since the underfill dominates the structural response of the layer. Therefore, analytical expressions for the bonded assembly can be used to predict package stress. The die deflection measurements have demonstrated that stylus profilometry is a simple, effective technique for indirectly assessing stress. Our measurements confirm that underfilled packages will have longer mean times between failures. CVD diamond, with its superior thermal conductivity and high electrical resistivity, is an attractive substrate material for electronics packaging. In the study discussed above and in many other high-power applications, diamond has been shown to be very useful for thermal management. However, the cost of the processed substrate is the major challenge for commercialization. Recent progress in CVD diamond deposition technology has reduced the cost to $4.25 for an unpolished 1 cm2 diamond substrate with a thickness of 200 mm [18]. This cost reduction has been achieved through a combination of system power scaling and substrate area increases. Implementation of tight process control and minimization of the stresses at every stage of the deposition cycle have resulted in a production- worthy process for fabricating crack-free diamond wafers 17.8 cm (7 in.) in diameter and 0.2–1.5 mm thick. Further, the cost increases linearly with thickness of the substrate [19]. For example, the cost of diamond substrates of size 1 cm2 with thickness of 500 mm is $10.50. The cost jumps significantly as the requirement for cutting, polishing, metallization, via drilling and many other post-processing steps are added. These steps are essential to build electronic packages using diamond-based substrate technology. However, implementation of some of the recent developments, such as very thin polyimide planarization [20] and multiple laser polishing [21], have the potential to reduce the cost of the post-deposition processing of diamond substrates for thermal management.
Acknowledgements The authors express their sincere appreciation to the Defense Advance Research Project Agency (DARPA) and 3M company for their support to this work.
5. Conclusions References Structurally, FEA modeling has shown that large, 1 cm×1 cm, GaAs flip-chips are expected to survive rapid cool-down from 37Pb/63Sn solder reflow attach-
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Thermal and mechanical analysis of high-power GaAs flip-chips on CVD diamond substrates M.D. Brown, S.B. Singh, A.P. Malshe*, M.H. Gordon, W.F. Schmidt, W.D. Brown High Density Electronics Center (HiDEC), Department of Electrical Engineering, Department of Mechanical Engineering, University of Arkansas, Fayetteville, AR 72701, USA Received 5 January 1999; accepted 7 June 1999
Abstract Using numerical, analytical and experimental methods, we evaluate the structural and thermal performance of a large, 1 cm×1 cm, GaAs die, flip-chip attached to 2.54 cm×2.54 cm diamond substrates. In agreement with numerical predictions, the GaAs dice’s induced stress during the attachment process — 37Pb/63Sn solder reflow and high-temperature underfill cure — is below the fracture strength of GaAs. However, as numerically predicted, the stress in the dice is higher for underfilled chips. This larger stress is measured indirectly through stylus profilometry where we experimentally determine the die deflection. The underfilled chips deflect more, which correlates with higher die stress. Both analytical and numerical results confirm this conclusion. Experimental and numerical thermal studies demonstrate the importance of the case-to-ambient thermal resistance (h ). For our ca package, diamond offers tremendous thermal advantage only for h values less than 1°C W−1 and offers little to no advantage ca for h values greater than 10°C W−1. © 1999 Elsevier Science S.A. All rights reserved. ca Keywords: Diamond; Finite element modeling; Flip-chip; Gallium arsenide; Profilometry; Thermal management
1. Introduction Excessive operating temperature is a common cause of device failure due to increased intrinsic carrier concentrations in semiconductor devices and thermal cycle fatigue of solder joints. To reduce junction temperatures, chemical vapor deposited synthetic diamond (CVDD) — due to its high thermal conductivity (~1000 W m−1 °C−1) and high electrical resistivity (~1013 V cm) — has been proposed for use as a heatspreading substrate material in single-chip and multichip module (MCM ) packages. Diamond substrates allow devices to be packaged in denser, closer-packed arrangements, thus reducing physical size and electrical conduction path lengths; however, the high cost of diamond limits its use to select, high-performance packages. High-power, edge-cooled, two-dimensional (2D) and three-dimensional (3D) diamond-based MCMs have previously been evaluated [1–3], and high-power, single-chip packages involving face-up and flip-chip * Corresponding author. Tel.: +1-501-575-6561; fax: +1-501-575-8720/6982. E-mail address: [email protected] (A.P. Malshe)
GaAs dice attached to diamond have also been thermally investigated [4,5]. In these studies, thermal modeling has typically employed an isothermal boundary condition to simulate cooling. In our work, an investigation of the case-to-ambient thermal resistance (h ) was perca formed to evaluate the impact of cooling resistance on the thermal enhancement capability of diamond substrates in 2.54 cm×2.54 cm single-chip packages. In particular, we investigate the performance of diamond-based, high-power, high-speed, flip-chip packages. The flip-chip die attachment method has the excellent characteristics of high input/output (I/O) capability and low interconnect inductance. Heat, in most cases, is removed from the open back side of the die through an attached heat sink arrangement. However, in the case of substrate cooling, necessiated by weight and/or space constraints, heat dissipation can be a problem since the flip-chip attachment layer is not continuous. Thus, the flip-chip bumps become a heat flow ‘bottleneck’. Finite element analysis ( FEA) modeling has shown that the use of thermally conductive underfill material can reduce the flip-chip die attach’s thermal resistance enough to be comparable to wire-bond thermal performance [5], and the use of diamond as the substrate material can
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significantly increase heat dissipation capability without the need for substrate thermal vias. Although diamond’s high thermal conductivity clearly offers a significant thermal advantage, its stiffness (E~1180 GPa) can pose structural problems in applications involving coefficient of thermal expansion (CTE) mismatches. Silicon (CTE~2.6 ppm °C−1) matches well with diamond (CTE~2.0 ppm °C−1), but GaAs (CTE~5.6 ppm °C−1) does not, and excessive tensile thermomechanical stresses within the die at the attachment interface are common [2,6,7]. In our work, structural finite element, analytical and experimental analyses were conducted for a single-chip package involving a flip-chip GaAs die attached to diamond to evaluate the structural response of the package during cooling from the solder reflow and during underfill cure processes. The experimental analysis was used to verify theoretical predictions for GaAs die deflection using simple, stylus profilometer measurements. Though in situ die stress measurements can be made using piezoresistive tests [8], the development of such test chips for a particular application is time consuming and costly. Instead, die deflection interferometry measurements are often reported for model verification [9,10]. Presented in our work are die deflection measurements taken with a standard, clean-room profilometer which simplifies the experimental process. CTE mismatched components also lead to thermal cycle fatigue. The on/off cycles of a device produce expansions and contractions of the die and substrate which can result in cyclic, plastic straining of the attach material. In this situation cracks develop and propagate, eventually causing low-cycle fatigue failure of the device. In the case of flip-chip die attachment, underfill is frequently used to extend the fatigue life of the solder bumps. Two-dimensional FEA models were used in our work, in conjunction with the Coffin–Manson relation [11], to estimate the effect of underfill on the fatigue life of the GaAs-on-diamond package.
2. Numerical modeling FEA is used to evaluate the thermal and structural performance of substrate material in the flip-chip configurations. Solder bump fatigue modeling is also carried out using FEA to quantify the benefit of underfill for increasing solder bump fatigue life in flip-chip attachment of GaAs to a diamond substrate. The modeling is performed using the commercially-available FEA software (version 5.3). 2.1. Thermal modeling An investigation of the case-to-ambient thermal resistance was performed to evaluate the impact of cooling
resistance on the thermal enhancement capability of diamond substrates in 2.54 cm×2.54 cm single-chip packages. Although a constant-temperature boundary condition approach to thermal modeling simplifies the analysis for the purpose of relative comparisons, it simulates an ideal case-to-ambient thermal cooling resistance (h =0°C W−1) and is not realistic. Instead, to ca avoid modeling complex heat sink geometries, an effective heat transfer coefficient was defined and varied to simulate non-zero h values ranging from ca 0.0001°C W−1 (approximately ideal ) to 10 000°C W−1 (approximately insulated ) on the edge-cooling surfaces of a single-chip, flip-chip package ( Fig. 1). The edgecooled substrate simulates a high-density package such as a three-dimensional stack of substrates having edges clamped into a water-cooled rack. 2.2. Numerical die stress modeling To investigate the structural effects of underfill in the 1 cm×1 cm, high input/output, GaAs-on-diamond flipchip die attachment, a one-quarter, 3D FEA model was constructed. To reduce model complexity, solder bumps were modeled as blocks instead of the actual truncated, spherical shapes. Since 3D structural analyses are vectorfield problems in which each node has three degrees of freedom, the FEA modeling is substantially more computationally intensive than is steady-state thermal analysis with just one degree of freedom per node. Material nonlinearities further complicate the analysis. To reduce solution times and required memory space, a strip was cut from the one-quarter model along the x-axis at the center of the package. Fig. 2 shows the meshed strip model which contains one row of 14 solder bumps and is three elements wide with a total of 3570 elements. Boundary conditions are identical to those on the onequarter model. Solution comparisons between the onequarter and strip models showed that the strip model consistently yielded maximum normal die stress values 20–30% lower than the one-quarter model predictions. For parametric modeling of GaAs die stress after cooling from reflow and underfill cure conditions, a worst-case situation of rapid cooling, without the benefit of solder creep, was assumed. Temperature-dependent, bi-linear solder plasticity was input into the model according Dasgupta et al. [12]. Linear material properties are given in Table 1. Note that the assumed reference (zero stress) temperature for the solder reflow model is the melting temperature for 37Pb/63Sn solder (183°C ), and for the underfill cure process it is the underfill’s glass transition temperature (T =140°C ) [9]. Due to g the rapid, high-temperature creep of lead–tin solder, it was assumed that the package relaxed to a zero stress state during underfill cure. From each solution, normal, element die stresses were recorded along the x-axis at the die/die attach interface since this is the critical
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Fig. 1. Diagram of the one-quarter FEA thermal model.
location where tensile stresses from the bending moment and the tensile forces are maximum. 2.3. Analytical die stress modeling An analytical, bonded assembly die stress model was developed by Schmidt [17] using beam theory and gives the normal stress in the die as:
A
B
1 3D (t +t ) DaDT s = − + 1 1 2 X(x), (1) 1 t D +D Kk2 1 1 2 where the subscripts 1 and 2 indicate die and substrate components, respectively; t represents component thicki
ness; and D represents the component flexural rigidity i for a unit width strip model as defined below: E t3 i i D= . (2) i 12(1−n3 ) i E represents Young’s modulus; n represents Poisson’s i i ratio; Da represents the difference in CTE between die and substrate; DT represents the temperature change between cure and room temperature; and K is the sum of K (attachment shear compliance), K (die shear 0 1 compliance) and K (substrate shear compliance) and 2 represents the interfacial shear compliance where: 2(1+n )t 2t i i. (3) K = 0; K= i 0 3G 3E 0 i In the above, G represents the shear modulus for the 0 attachment layer, t represents the thickness of the 0 attachment layer, k2 is the sum of l (die axial compli1 ance), l (substrate axial compliance) and l (bending 2 12 compliance) divided by K where: 1−l (t +t )2 i; l = 1 2 l= . (4) i 12 Et 4(D +D ) i i 1 2 Finally, X(x)=1−[cosh(kx)/cosh(kl )] and represents the functional variation of stress with x measured from the die center to the die edge. Note that the overall die length is defined to be 2l. 2.4. Solder bump fatigue modeling
Fig. 2. 3D structural FEA strip model of flip-chip GaAs-on-diamond.
The 1 cm×1 cm×600 mm GaAs dice are attached to the substrates using 784 electroplated Pb/Sn solder
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Table 1 FEA linear material properties
37Pb/63Sn Underfill GaAs CVDD Silicon
Coefficient of thermal expansion, a (ppm °C−1]
Poisson’s ratio, n
Young’s modulus, E (GPa)
Thermal conductivity ( W m−1 °C−1]
24.7 26 5.58 2 2.6
0.4 0.4 0.3 0.148 0.3
33.9 10.0 123 1180 167
35 2 45 1000 150
bumps with a 357 mm pitch. The bump stand-off height is 50 mm, and the bump diameter is about 100 mm. To quantify the benefit of underfill on increasing solder bump fatigue life in the flip-chip GaAs-on-diamond package, two-dimensional, plane strain models were constructed for the above parameters. Two-dimensional models were used since time-dependent creep calculations require lengthy computational time in 3D models. Creep was input as a solder bump material property through a secondary creep FEA option using the Wertmann–Dorn relationship that follows: AGb
e˙ = (b/d )p(s/G )nD e(−Q/RT), 0 s kT
following Coffin–Manson relation: N =h(Dc )w, (6) f p where N represents the number of cycles to failure, f Dc represents the plastic strain range, and h and w p represent material constants (h=1.2928 and w=−1.96 for 37Pb/63Sn solder [13]).
3. Experimental procedure 3.1. Thermal experimentation
(5)
where, for 37Pb/63Sn solder, e˙ represents the steadys state creep rate (s−1), A represents a dimensionless constant (40), G represents the temperature-dependent shear modulus (2.2×104−16.1T( K ), in MPa), b represents the Burger’s vector magnitude of crystal dislocation (3.2×10−7 mm), k represents the Boltzmann constant (1.38×10-23 J K−1), T represents the absolute temperature ( K ), d represents the grain size (5.5×10−3 mm), p represents the grain size exponent (1.6), s represents the applied stress (MPa), n represents the stress exponent (2.4), D represents the pre-exponen0 tial constant (100 mm2), Q represents the activation energy for a rate-limiting diffusion process (44 000 J mol−1), and R represents the gas constant (8.314 J K−1 mol−1). Solutions for cooling rates of 0.5°C s−1 from the chosen operating temperatures to an ambient state of 50°C were used to obtain shear displacements of the solder bump at the edge of the die where the maximum shear occurs. To improve fatigue life calculations, the shear displacement solutions (using block shaped bumps) were input as boundary conditions on a more accurate single 2D bump model ( Fig. 3). This bump model contains 25 mm sections of the die and substrate and 2 mm copper bump pads, and it can be configured with or without underfill material. The maximum absolute plastic shear strains were recorded from model solutions (for example, Fig. 4) to calculate of joint fatigue life using the
For experimental study of the edge-cooled substrate application and for verification of the FEA modeling, a liquid-cooling system was designed to provide heat removal from the edges of 2.54 cm×2.54 cm substrates using water as the cooling fluid. A schematic view of the test vehicle’s cold chucks and the operating ‘package’ is shown in Fig. 5. Two substrates were tested, CVD diamond and silicon, and each had a thickness of about 700 mm. The CVD diamond substrates used in our work are from Norton Diamond Film, and their average temperature-independent properties (sufficient for this study) are listed in Table 1 along with those of silicon. The 1 cm×1 cm×600 mm GaAs dice are attached to the substrates using 784 electroplated Pb/Sn solder bumps with a 357mm pitch. The bump stand-off height is 50 mm, and the bump diameter is about 100 mm.
Fig. 3. 2D FEA model of one flip-chip solder bump.
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Fig. 4. FEA solution for plastic shear strain distribution in a 37Pb/63Sn, GaAs-on-diamond flip-chip solder bump subject to deformation predicted from the one-quarter model with block shaped bumps.
Power (q) was input via a pre-packaged power metal oxide semiconductor field effect transistor (MOSFET ) device (1.9 cm×1.3 cm) due to a lack of interconnection lines on diamond and silicon substrates. To accurately represent the model geometry, a 1 cm×1 cm dummy die was ‘sandwiched’ between the MOSFET and the substrate to ensure that the heat flux was introduced over a 1 cm×1 cm area. The substrates were attached to the aluminum cold chucks at two opposing sides on 1 mm ledges, as shown in Fig. 5. Thermal grease and pressure (~9 psi, applied manually) were applied to all interfaces to ensure good thermal contacts. Owing to the use of the MOSFET as the power source, a location for taking an ‘on-chip’ or junction temperature measurement was not available. Therefore, temperature was measured on the underside of the substrate directly beneath the power source at the center of the substrate. Temperature was also measured in a small cavity at the interface between the substrate’s edge and the cold chuck. These two package temperatures were recorded using type K thermocouples having beads
coated with thermal grease. The temperature at the center of the substrate provided a value to compare with model predictions, and the difference between the substrate edge temperature (T ) and the coolant temper1 ature (T ) provided a means of calculating h 2 ca [(T −T )/q]. 1 2 3.2. Structural experimentation To investigate the underfill flip-chip attach experimentally, 1 cm×1 cm×600 mm GaAs dummy dice were bumped with a full array (357 mm pitch) of 784 electroplated, Pb/Sn solder bumps, approximately 70 mm tall and 100 mm in diameter. The under-bump metallurgy was sputtered titanium/copper, and the array pattern was defined using photo-definable benzocyclobutene (BCB). CVD diamond substrates, 700–900 mm thick, were sputtered with a Ti/Cu/Ti metallization scheme to provide bondable metallization. The top layer of titanium was patterned to define the pad array since titanium is not a Pb/Sn solder-wettable metal. After reflow
Fig. 5. Schematic illustration of the MOSFET-powered edge-cooling apparatus.
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attachment, the bump stand-off height was about 50 mm. The attachments were underfilled and cured at 165°C. Once cooled, the dice were scanned using a stylus profilometer to examine die bending as a result of the CTE mismatch between GaAs and diamond. These die deflection scans were made over the backs of the flipchip dice in both in-plane directions (x and y) from side to side, not corner to corner. Vertical displacement of the die, defined as the difference in elevation between the center and edge, was obtained by averaging these measurements and compared with model predictions.
4. Results and discussion The thermal results for diamond (2.54 cm×2.54 cm) and silicon (2.54 cm×2.54 cm) substrates are presented in Fig. 6 for the parameter values given in Table 1. For the three experimental steady-state cooling conditions [no coolant flow, low flow (0.001 kg s−1) and high flow (0.01 kg s−1)], for substrate temperatures 50°C above ambient, good agreement with the numerical predictions is observed. In general, we see that diamond offers little to no advantage for h greater than 10°C W−1. ca However, for h less than 1°C W−1 (obtained with a ca liquid-cooled fixture), diamond offers tremendous thermal advantages. To achieve lower cooling resistance, techniques such as direct immersion cooling and microchannel cooling have been investigated [14,15]. For cooling resistances of less than 10−2 °C W−1, the edgecooled diamond substrate package provides a factor of five improvement over silicon. Fig. 7 compares the maximum normal stresses within the die after solder reflow and underfill cure processes for varying geometric configurations. As expected, larger
Fig. 6. Comparison of MOSFET-powered device and FEA for dissipated power (50°C junction temperature rise over ambient) as a function of cooling resistance for the edge-cooled substrate configuration.
die thickness, larger stand-off heights and smaller die sizes all lead to lower die stress for both solder reflow and underfill curing. However, larger substrate thickness leads to lower solder reflow stress but higher underfill cure stress. With underfill coupling the die and substrate, the result is as expected. Larger and thus stiffer substrates increasingly restrict the die from reaching its stress-free configuration. Thus, the die stress increases. With no underfill, thicker substrates lead to less package bending and thus less bending stress. Hence, the normal stress, a combination of axial and bending stress, decreases. It is also observed that, in general, the underfill cure stresses are higher, but none of the stress values exceed the fracture strength of GaAs (approximately 85 MPa [16 ]) even considering the 30% underestimation of the strip model. Our experimental fabrication has confirmed this conclusions. For thin substrates, thin dice and large die sizes, however, the solder reflow stress is larger than the underfill cure stress. These parameter values lead to high aspect ratios ( length/thickness) and significant package bending. Since plastic deformation of solder bumps relieves the axial die stress component, the bending component is dominant in the solder reflow process. Although not shown in Fig. 7, we also varied the solder bump stiffness (from 10 to 50 GPa) and found very little change (1%) to the underfill cure die stress. In fact, a strip model without any solder bumps produced approximately the same solution as the base case model with solder bumps. For completeness, the onequarter, 3D model was also solved with the highly nonlinear solder bumps and is in excellent agreement with the analytical solution [Eq. (1)] that does not include the bumps (Fig. 8). The maximum normal die stress of 43.8 MPa is consistent with the 30% approximate underestimation of the strip model prediction (30.3 MPa). These results confirm that the structural response of underfilled dice is dominated by the underfill material [8,9]. Thus, the die stress in the underfilled 37Pb/63Sn flip-chip GaAs-on-diamond die attachments can be modeled accurately using the analytical expression, even for high I/O counts. Since the above stress predictions are based on numerical and analytical calculations, we indirectly and experimentally investigated the underfill die attach stress by measuring die deflection using stylus profilometry. In addition, we compare these measurements against the following analytical die deflection prediction (see Ref. [6 ], p. 43): DaDT(t +t )l2 1 2 w =− max 4(l +l +l ) (D +D ) 1 2 12 1 2 2[cosh(kl )−1] × 1− . (kl )2 cosh(kl )
A
B
(7)
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Fig. 7. FEA results from 3D strip model for normal die stress at the die/die attach interface in a GaAs-on-diamond flip-chip die attachment. Result are for solder reflow conditions (SR) and underfill cure conditions ( UC ) for various configurations.
The results are shown in Fig. 9 for substrate thicknesses of 700 mm, 800 mm and 900 mm and a cure temperature of 165°C. As a control, note that we measured a maximum vertical displacement of about −0.2 mm (see inset picture in Fig. 9 for position of measurement). This concave-down deflection was most likely a result
Fig. 8. Comparison of one-quarter, 3D FEA and analytical normal die stress at the die/die attach interface in a GaAs-on-diamond flip-chip die attachment after underfill cure.
of metallization-induced stress. Other bonded dice deflections were corrected to account for this effect by adding the magnitude of the unbonded dice deflection. Immediately after experiencing the underfill cure cooldown, the non-underfilled dice showed vertical displacements ranging from 1 to 2 mm depending upon substrate thickness (not shown in Fig. 9). However, the underfilled
Fig. 9. Comparison of analytical and experimental die deflection measurements for a 165°C cure temperature.
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Fig. 10. 2D FEA maximum 37Pb/63Sn solder bump shear displacement as a function of DT with and without underfill.
dice profiles show vertical displacements of 3–5 mm. These results support the modeling conclusion that underfill leads to higher die stress because it limits the die stress-relieving solder bump deformation. Although the underfill leads to higher die stress, it minimizes the solder bump shear displacement, which increases reliability. Fig. 10 shows the FEA maximum bump shear displacements for various temperature changes between off and on conditions, and confirms that the underfill decreases the bump displacement. To calculate predicted cycles to failure, the maximum plastic shear strain value is needed as input to the Coffin–Manson relation [Eq. (6)]. As noted previously, the maximum shear displacement was found by solving the one-quarter flip-chip FEA model. This maximum shear displacement was then used as a boundary condition on a single-bump FEA model (Fig. 3) to solve for the maximum absolute plastic shear strain value (Fig. 4). For a 20°C cycle, the single-bump FEA model results for plastic shear strain for the no-underfill and underfilled cases were 2.20×10−2 and 6.99×10−3, respectively. Based on these results, we estimated the number of cycles to failure to be 10 850 and 1143 cycles for packages with and without underfill, respectively. Note that we have divided the predicted cycles to failure by two to obtain a predicted number of complete ‘on/off ’ cycles to failure (assumes absolute strain to be identical for positive and negative displacement). This reliability improvement of about an order of magnitude demonstrates the benefit of underfill for GaAs-on-diamond flip-chip packages.
ment to diamond substrates and subsequent high-temperature underfill cure. This survival has been confirmed experimentally. The modeling has also shown that the underfilled flip-chip die-attachment layer, though having a high I/O bump count, can still be considered a continuous layer of underfill, disregarding the bumps, since the underfill dominates the structural response of the layer. Therefore, analytical expressions for the bonded assembly can be used to predict package stress. The die deflection measurements have demonstrated that stylus profilometry is a simple, effective technique for indirectly assessing stress. Our measurements confirm that underfilled packages will have longer mean times between failures. CVD diamond, with its superior thermal conductivity and high electrical resistivity, is an attractive substrate material for electronics packaging. In the study discussed above and in many other high-power applications, diamond has been shown to be very useful for thermal management. However, the cost of the processed substrate is the major challenge for commercialization. Recent progress in CVD diamond deposition technology has reduced the cost to $4.25 for an unpolished 1 cm2 diamond substrate with a thickness of 200 mm [18]. This cost reduction has been achieved through a combination of system power scaling and substrate area increases. Implementation of tight process control and minimization of the stresses at every stage of the deposition cycle have resulted in a production- worthy process for fabricating crack-free diamond wafers 17.8 cm (7 in.) in diameter and 0.2–1.5 mm thick. Further, the cost increases linearly with thickness of the substrate [19]. For example, the cost of diamond substrates of size 1 cm2 with thickness of 500 mm is $10.50. The cost jumps significantly as the requirement for cutting, polishing, metallization, via drilling and many other post-processing steps are added. These steps are essential to build electronic packages using diamond-based substrate technology. However, implementation of some of the recent developments, such as very thin polyimide planarization [20] and multiple laser polishing [21], have the potential to reduce the cost of the post-deposition processing of diamond substrates for thermal management.
Acknowledgements The authors express their sincere appreciation to the Defense Advance Research Project Agency (DARPA) and 3M company for their support to this work.
5. Conclusions References Structurally, FEA modeling has shown that large, 1 cm×1 cm, GaAs flip-chips are expected to survive rapid cool-down from 37Pb/63Sn solder reflow attach-
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