Ultra-high current efficiency single-stage class-AB OTA with completely symmetric slew rate

Int. J. Electron. Commun. (AEÜ) 87 (2018) 65–69

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Regular paper

Ultra-high current efficiency single-stage class-AB OTA with completely symmetric slew rate

T

⁎

Xiao Zhao , Yongqing Wang, Dawei Jia, Liyuan Dong School of Geophysics and Information Technology, China University of Geosciences, Beijing 100083, PR China

A R T I C L E I N F O

A B S T R A C T

Keywords: Current efficiency Class-AB OTA Symmetric slew rate

An ultra-high current efficiency single-stage class-AB OTA with completely symmetric slew rate is presented. Based on adaptive biasing and nonlinear current mirror techniques employed in a proposed symmetric current recycling structure, the proposed OTA not only achieves the maximum output current proportional to Vin8 , but also has the symmetric positive and negative slew rates. Also, the proposed self-biasing output stage makes the slew rate unconstrained. Simulation results demonstrate that the slew rate of the proposed OTA is enhanced by 1500% over that of the conventional folded cascode counterpart with a little increased power, which is suitable for large capacitive load applications.

1. Introduction

proportional to Vin8 , but also has the symmetric positive and negative slew rates. At the same time, our proposed self-biasing output stage dynamically bias the gate voltage of cascode transistors, making the slew rate unconstrained. The following sections present the details of our proposed approach. In Section 2, the conventional FC OTA is summarized. In Section 3, we introduce each technique’s details of our proposed OTA. In Section 4, the detailed circuit analysis is discussed. The performance comparisons of two OTAs, the conventional FC and our proposed OTA, are given in Section 5. And Section 6 gives the conclusions.

In the low-voltage low-power switched-capacitor applications, especially for large capacitive load, operational transconductance amplifiers (OTA) with high slew rate and large gain-bandwidth product (GBW) are required [1]. Thus, enhancing the current efficiency (CE) of the OTAs has become prevalent in recent years. The conventional folded cascade(FC) OTA is the most commonly used amplifier structure, which is shown in Fig. 1. However, the CE is not large enough owing to its working at the class-A status. In order to enhance the CE of the FC, the current recycling technique is proposed [2–8]. However, the maximum output current of current recycling structure is limited by the tail current of input pairs. Thus, the slew rate is only linearly enhanced. To resolve this problem, some techniques have been presented, such as adaptive biasing [9,10], and nonlinear current mirror [11] and quasifloating gate [12,13] techniques. These techniques significantly improve the maximum output current without the constraint of the tail current. Nonetheless, the maximum output current can only be achieved to be proportional to Vin4 according to the published papers as of now. More importantly, because of the cascode transistors biased by constant voltage in the conventional output stage, the achievable maximum slew rate is limited, especially in the low-voltage applications. To solve the above problems, an ultra-high current efficiency singlestage class-AB OTA with completely symmetric slew rate is presented in this paper. It employs adaptive biasing and nonlinear current mirror techniques in our proposed symmetric current recycling structure [14], achieving that not only the maximum output current is increased to be ⁎

2. Conventional folded cascode OTA The conventional folded cascode (FC) OTA is shown in Fig. 1. The equivalent transconductance (Gm ) of the FC can be expressed as,

Gm,FC = gm,1

where gm,1 is the transconductance of the input transistor M1. Consequently, the GBW of the FC can be given as,

GBWFC =

Gm,FC CL

(2)

Meanwhile, the slew rate of the FC can be described as,

SRFC =

2IB CL

(3)

Note that the slew rate of the FC can not achieve a larger value, which are limited by the tail current source (M7 ) and the folded current

Corresponding author. E-mail addresses: [email protected] (X. Zhao), [email protected] (Y. Wang), [email protected] (D. Jia), [email protected] (L. Dong).

https://doi.org/10.1016/j.aeue.2018.02.012 Received 14 November 2017; Accepted 12 February 2018 1434-8411/ © 2018 Elsevier GmbH. All rights reserved.

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Int. J. Electron. Commun. (AEÜ) 87 (2018) 65–69

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differential pairs (M 1a,M 1b,M 1aN and M 1bN ) and two cross-coupled Flipped Voltage Followers (FVFs) composed of the input transistors (M 1c and M 1cN ), diode-connected transistors (M8 and M 8N ) and current sources (M9 and M 9N ). In dc conditions, the bias current for FVFs is set to 0.5IB . Owing to the matched input transistors of FVFs, the bias current of the input differential pairs is also 0.5IB . For small signal analysis, due to the effect of FVFs, the input signal is also applied to the source terminal of the input differential pairs, leading to a boost in the effective transconductance (Gm ), which can be expressed as,

Gm = 2·gm,1a

(4)

where gm,1a is the transconductance of the input transistor M 1a . For the large signal response, when a large negative step signal happens at Vin+, due to the role of the FVFs, the voltage at node Y rapidly decreases, forcing the input transistors M 1aN and M 1bN to turn off. Instead, the voltage of node X does not change, making a large current Iin flowing through M 1a and M 1b, which can be expressed as, 2

Iin =

β1a,b ⎛ IB ⎞ + Vid ⎟ 2 ⎜ β1a,b ⎠ ⎝

(5)

where β1a,b = μn Cox (W / L)1a,b is the transconductance factor of transistors M 1a and M 1b, and Vid is the input differential signal. Therefore, the proposed input stage is operating at class-AB status.

Fig. 1. The conventional folded cascode OTA.

sources (M3 and M 3N ), making the FC operate at class-A status.

3.2. Nonlinear current mirror

3. Enhanced symmetric recycling OTA

Transistors M 3a−M 3b−M 3c form the nonlinear current mirror, so as the M 3aN −M 3bN −M 3cN ,M 4a−M 4b−M 4c and M 4aN −M 4bN −M 4cN . The bias voltage for M 3c and M 3cN are provided by Vntri, making M 3a and M 3aN at the margin of saturation region. So as the bias voltage Vptri. Take M 3a−M 3b−M 3c as an example. When a large current Iin enters into M 3c , the source voltage of it significantly decreases, forcing the M 3a to work at the triode region. Thus,the current I3b flowing through M 3b can be expressed as,

The schematic of the proposed enhanced symmetric recycling OTA(ESRFC) is shown in Fig. 2. It consists of the adaptive biasing classAB input stage, the symmetric current recycling structure composed of the nonlinear current mirror and the self-biasing output stage. The technique details are presented as follows. 3.1. Adaptive biasing class-AB input stage

2

I3b = The adaptive biasing class-AB input stage consists of the input

β3b ⎛ Iin + 0.5IB ⎞ ⎜ ⎟ 2 ⎝ β3a Vds,3a ⎠

Fig. 2. The schematic of enhanced symmetric recycling OTA.

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X. Zhao et al.

(10)

Av = Gm·Rout

where Vds,3a is the drain-to-source voltage of transistor M 3a . Note that the current ratio of the nonlinear current mirror is no longer linearly increased, but is proportional to Iin2 .

where Rout is the output resistance of the OTA. In the proposed ESRFC, the Rout can be expressed as,

3.3. Symmetric current recycling structure

Rout = [(gm,7 rds,7) rds,4b]‖[(gm,6 rds,6)(rds,3b ‖(1/ gm,8)‖(1/ gm,6N ))]

where rds is the output resistance of the transistor. Note that although the nonzero output resistance is introduced by the FVFs, less current conducted in the output stage and the enhanced Gm significantly improve the dc gain of the proposed ESRFC when compared to the conventional FC.

In the symmetric current recycling structure, the input differential pair M1 and M 1N in the conventional FC are split in half to produce M 1a,M 1b and M 1aN ,M 1bN . And then the input transistor M 1b is crossconnected to the nonlinear current mirrors M 3aN −M 3bN −M 3cN . So as the input transistor M 1bN . That is the same as the conventional recycling structure. However, the drain terminal of M 3b and M 3bN have two current paths: one path flows directly through the cascode transistors M6 or M 5N to the output Vo−, and the other one goes through the nonlinear current mirror M 4aN −M 4cN or M 4a−M 4c to the output Vo+. The output current Iout at Vo+ or Vo− can be expressed as,

Iout =

ΔI3b + ΔI3bN 2

4.3. Slew rate To analyze the large signal response, assuming that a large negative step signal is applied to Vin+, the voltage at node Y decreases rapidly, forcing the input transistors M 1aN and M 1bN to turn off. The gate voltage of M 3a decreases, making transistor M 3b cut off, and then the input transistor M 1a goes into the triode region. Owing to the effect of the FVF, node X voltage keeps constant. Therefore, the current Iin flowing through M 1b can be expressed as,

(7)

where ΔI3b and ΔI3bN represent the variation of current flowing through the transistors M 3b and M 3bN . Owing to the equal output current at Vo+ and Vo−, the positive and negative slew rates are completely symmetric.

Iin ≈

β1b 2

Vid2

(12)

where Vid is the input differential signal. This current flows into the nonlinear current mirror (M 3aN ,M 3bN and M 3cN ), making the gate voltage of M 3aN increase and then operate in ohmic region. Thus, the drain current Im of M 3bN can be given as,

3.4. Self-biasing output stage The cascode transistors M5 and M 5N are self-biased by the gate terminal of M 4aN , M6 and M 6N are biased by that of M 4a,M 7 are biased by that of M 3a , and M 7N are biased by that of M 3aN . When input signal is small, this structure acts as the traditional cascode configuration. While a large input happens, assuming that the current of transistor M 3b significantly increases, consequently that of M 3bN rapidly decreases. Then it makes the voltage VBP approach VDD, and fully turns on the cascode transistors M6 and M 6N . At the same time, since the gate voltage of M 3aN decreases, it fully turns on M 7N . The same results can be obtained for M 5,M 5N and M7 . Therefore, the selfbiased output stage does not limit the slew rate of the proposed OTA.

Im ≈

2

β3bN ⎛

Iin ⎞ ⎟ 2 ⎝ β3aN Vds,3aN ⎠ ⎜

2

Io− ≈

β4b ⎛ 0.5Im ⎞ ⎜ ⎟ 2 ⎝ β4a Vds,4a ⎠

− Itot = Io− + 0.5Im ≈ Io−

The negative slew rate For ac small signal analysis, owing to the cross-coupled FVFs, the input signal is also applied to the source terminal of M 1a,M 1b and M 1aN ,M 1bN . Then, the ac small current enters into the nonlinear current mirrors M 3a−M 3b−M 3c and M 3aN −M 3bN −M 3cN . Since the nonlinear current mirror is the same as the conventional current mirror in the small signal conditions, the ac small current is amplified by a factor of K. Half of it directly flows to the output, and the other half goes through another nonlinear current mirror to the output. Thus, the effective transconductance (Gm ) of the proposed ESRFC can be expressed as,

(15)

SR−

can be given as follow,

I− SR− = tot CL From Eqs. (12)–(14), the

SR− ≈

(16)

SR−

β4b β32bN β14b 2 4 2 4 512β4a β3aN Vds ,4a Vds,3aN

·

can be written as,

Vid8 CL

(17)

Note that as self-biased cascode output stage, the decreasing gate voltage of M 3a will fully turn on the cascode transistor M7, thus the drainsource voltage will saturate M 4b even in large current conditions. The same operations are for cascode transistors M 5(N ) and M 6(N ) . Owing to completely symmetric circuit structure, the positive and negative slew rates are exactly equal. Therefore, the slew rate is proportional to Vid8 .

(8)

where K is the ratio factor of the current mirror. Then the unity-gain bandwidth (GBW) can be given as,

Gm,ESRFC CL

(14)

− can be expressed as, Thus, the total discharge current Itot

4.1. Transconductance and GBW

GBWESRFC =

(13)

Half of this current flows to Vo+ through cascode transistor M 5N , and the other half enters the second nonlinear current mirror(M 4a,M 4b and M 4c ). The same operation happens. Thus, the output current Io− to Vo− can be given as,

4. Circuit analysis

Gm,ESRFC = 2(k + 1)·gm,1a

(11)

4.4. Stability performance

(9)

where CL is the load capacitance. Note that the Gm , correspondingly the GBW, of the proposed ESRFC is improved by (K + 1) times when compared to that of the conventional FC.

The proposed ESRFC shares the same dominant pole (ωp1) with that of the traditional FC, which is determined by the output impedance (Rout ) and the capacitive load (CL ),

4.2. DC gain

ωp1 =

The dc gain( Av ) of the OTA can be described as,

1 Rout CL

(18)

The nondominant pole can be determined by the parasitics at the source 67

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X. Zhao et al.

FC ESRFC

80

Gain,dB

60 40 GainFC=56.49dB

20

GainESRFC=78.64dB

0

GBWFC=520.6kHz GBWESRFC=2.021MHz

-20

0

Phase,deg

Fig. 3. The layout of the proposed ESRFC OTA.

terminal of cascode transistors M6 and M 5N ,

ωp2 =

gm6 Cgs6 + Cgs6N + Cgd1a + Cgd3b

(19)

ωp4 =

PMFC=90.11deg PMESRFC=85.43deg

-60 -90

In addition, owing to the exist of the nonlinear current mirrors, there are four pole-zero pairs. The nondominant poles associated with the nonlinear current mirrors M 3a (N )−M 3b (N ) and M 4a (N )−M 4b (N ) are,

ωp3 =

-30

-120 1

10

100

1k

10k

100k

1M

10M

Frequency,Hz

gm3a

Fig. 4. The open-loop AC response of post layout simulation for two OTAs.

(K + 1) Cgs3a

(20)

gm4a 2Cgs 4a

SR+FC=0.504V/us

The location of the first nondominant pole may be interchanged depending on design. To guarantee the enough phase margin, the first nondominant pole should be 3 times larger than the GBW. Therefore, for an optimal design, the phase margin of the proposed ESRFC should be satisfied.

Amplitude,V

0.4

5. Simulation results To demonstrate performance enhancement achieved by the proposed ESRFC, we designed FC and ESRFC OTAs as a contrast. Both OTAs were designed in the 0.18 μ m CMOS process with 1.0 V supply voltage, and the load capacitance is 140 pF. The bias current IB of ESRFC is set to 10 μ A, so as that of FC. The total current consumption of ESRFC is 50 μ A, and that of FC is 40 μ A. The size of transistor M11 is 1/ 4 that of M 3a and the size of M10 is 1/4 that of M 4a to provide the nonlinear current mirrors with the appropriate bias. The layout of the proposed ESRFC OTA is shown in Fig. 3, and the transistors aspect ratios are listed in Table 1. The open-loop AC response of post layout simulation for two OTAs are shown in Fig. 4. Note that the GBW of the proposed ESRFC is 2.02 MHz, improved by almost 300% when compared to that of the conventional FC. The dc gain of the FC and the ESRFC OTAs are 56.5 dB and 78.6 dB. It shows that the dc gain of our proposed ESRFC is enhanced by almost 22 dB. In addition, there is slight degradation of the phase margin. Both OTAs are closed-loop configured as unit-gain to simulate the large signal response. Fig. 5 shows the large signal transient response of post layout simulation for two OTAs. A large step signal of 0.4 Vpp at 100 K is applied to two OTAs. Note that the slew rate of the proposed ESRFC is equal and achieves up to 8.1 V/μ s, which is almost 16 times

W/L (μ m/μ m)

M 1a,b,c (N ) M 3b (N ) M 4a (N ) M 4c (N ) M 5,6(N )

20/0.2 30/1 50/1 20/0.2 50/0.2

Transistors

M 3a (N ) M 3c (N ) M 4b (N ) M 8(N ) M 7(N )

SR+ESRFC=8.08V/us

0.2

0.0

-0.2

SR-FC=0.515V/us

-0.4

SR-ESRFC=8.11V/us -0.6 0.0

Time,s Fig. 5. The large signal transient response of post layout simulation for two OTAs.

that of the traditional FC. Meanwhile, there is no sign of ringing, demonstrating that the enhanced performance has negligible effects on the phase margin of the ESRFC. The maximum dynamic output current and dc supply current versus the input voltage are shown in Fig. 6. Note that the dc supply current of the proposed ESRFC is kept constant when the input voltage increases, which almost has the same value as that of the FC. The maximum dynamic output current of the ESRFC is significantly enhanced with the increased input voltage, while that of the FC is still kept constant. It can be seen that the maximum dynamic output current of the ESRFC achieves 16 times that of the FC counterpart, which demonstrates that the proposed ESRFC is more current efficient. The performance comparisons of the two OTAs are listed in Table 2. The 1% settling time of ESRFC is 1.98 μ s, which demonstrates a significant boost when compared to that of the FC owing to the improved transconductance. Usually, FoMS and FoML are used to evaluate the CE of an OTA, which are expressed as FoMS = 100·GBW ·CL/ Itot and FoML = SR·CL/ Itot . Note that the CE of the proposed ESRFC has been greatly improved, especially for the FoML value, which is 13 times that of the FC counterpart. To analyze the influence of the process mismatches and spreads, Monte Carlo analysis of the proposed ESRFC over 1000 runs are simulated, which are listed in Table 3. Note that the GBW of the proposed

Table 1 Transistors aspect ratios of the proposed ESRFC OTA. Transistors

FC ESRFC

0.6

(21)

W/L (μ m/μ m) 10/1 40/0.2 150/1 20/0.2 40/0.2

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X. Zhao et al.

Table 4 The comparisons with the prior arts.

DC supply current of ESRFC DC supply current of FC Output current of ESRFC Output current of FC

Parameter

Current (uA)

Supply voltage (V) Technology (nm) Bias current (μA) Load (pF) DC gain (dB) GBW (MHz) Phase margin (° ) Slew rate (V/μs) 1% Settling time (ns) FoM1 (MHz·pF/μA ) FoM2 ((V/μs)·pF/μA )

0 -200.0m

-100.0m

0.0

100.0m

200.0m

Fig. 6. The maximum dynamic output current and dc supply current versus the input voltage of two OTAs.

ESRFC

Voltage supply (V) Current supply (μA) CL (pF) Area (μm × μm) GBW (MHz) DC gain (dB) Phase margin (° )

1.0 40 140 25 × 24 0.52 56.5 90.1

1.0 50 140 36 × 81 2.02 78.6 85.4

SR+ (V/μs) SR− (V/μs) 1% Settling time (μs) CMRR@DC (dB) PSRR@DC (dB) THD@100 KHz, 100 mVpp (dB)

0.5 0.52 7.69 96.2 87.5 −47.2 25.4

8.1 8.1 1.98 145.8 79.2 −67.3 15.6

182 1.8

565.6 22.7

Input referred noise@1 MHz (nV/ Hz ) FoMS (MHz·pF/μA ) FoML ((V/μs)·pF/μA )

DC gain (dB) GBW (MHz) Phase margin (°) Slew rate (V/μs)

Average

Standard deviation

75.6 1.96 83.2 7.95

4.8 0.37 5.6 0.29

[7]

[12]

This work

1.8 180 800 5.6 60.9 134.2 70.6

1.2 130 260 7 70.2 83 70

1.0 65 800 10 54.5 203.2 66.2

1.0 180 40 30 80.3 10.2 80.4

2.0 500 40 70 81.7 4.75 60

1.0 180 50 140 78.6 2.02 85.4

94.1 11.2 93 0.66

29.8 – 223 0.8

87.9 10.1 254 0.88

1.78 136 756 1.34

8.7 85 554 11.42

8.1 1.98 565.6 22.7

An ultra-high current efficiency single-stage class-AB OTA with completely symmetric slew rate is presented. Based on adaptive biasing and nonlinear current mirror techniques employed in our proposed symmetric current recycling structure, the slew rate is enhanced by 1500% that of conventional FC with a little increased power consumption. Therefore, the proposed ESRFC OTA is suitable for the lowvoltage low-power applications, especially for large capacitive load. Acknowledgements This work is supported by the National Natural Science Foundation of China (No. 41704174) and National Natural Science Foundation of China (No. 41574131). References [1] Nakamura K, Carley LR. An enhanced fully differential folded-cascode op-amp. IEEE J Solid-State Circ 1992;27(4):563–8. [2] Assaad R, Silva-Martinez J. Enhancing general performance of folded cascode amplifier by recycling current. Electron Lett 2007;43(23):1243–4. [3] Assaad R, Silva-Martinez J. The recycling folded cascode: a general enhancement of the folded cascode amplifier. IEEE J Solid-State Circ 2009;44(9):2535–42. [4] Li YL, Han KF, et al. Transconductance enhancement method for operational transconductance amplifiers. Electron Lett 2010;46(19):1321–3. [5] Zhao X, Fang H, Xu J. A transconductance enhanced recycling structure for folded cascode amplifier. Analog Integr Circ Sig Process 2012;72:259–63. [6] Yan Z, Mak P, Martins RP. Double recycling technique for folded-cascode OTA. Analog Integr Circ Sig Process 2012;71:137–41. [7] Zhao Xiao, Zhang Qisheng, et al. Transconductance and slew rate improvement technique for currentrecycling folded cascode amplifier. AEU-Int J Electron Commun 2016;70:326–30. [8] Zhang Qisheng, Zhao Xiao, et al. Multipath recycling method for transconductance enhancement of folded cascade amplifier. AEU-Int J Electron Commun 2017;72:1–7. [9] Baswa S, Lopez-Marin AJ, Angulo JR, Carvajal RG. Low-voltage micropower super class AB CMOS OTA. Electron Lett 2004;40(4):216–7. [10] Lopez-Martin AJ, Baswa S, Ramirez-Angulo J, et al. Low-voltage super class AB CMOS OTA cells with very high slew rate and power efficiency. IEEE J Solid-State Circ 2005;40(5):1068–77. [11] Galan JA, Lopez-Martin AJ, Carvajal RG, et al. Super class-AB OTAs with adaptive biasing and dynamic output current scaling. IEEE Trans Circ Syst I Reg Pap 2007;54(3):449–57. [12] Saso JM, Lopez-Martin AJ, Garde MP, et al. Power-efficient class AB fully differential amplifier. Electron Lett 2017;53(19):1298–300. [13] Lopez-Martin A, Garde MP, Algueta JM, et al. Enhanced single-stage folded cascode OTA suitable for large capacitive loads. IEEE Trans Circ Syst II Express Briefs 2017;PP(99):1–1. [14] Zhao X, Fang H, Xu J. A new low power symmetric folded cascode amplifier by recycling current in 65 nm CMOS technology; 2011,. p. 820–3.

Table 3 Monte Carlo analysis of the proposed ESRFC (1000 runs). Parameter

[6]

6. Conclusion

Table 2 The performance comparisons of two OTAs. FC

[4]

OTA has the superior performances in both accuracy and speed when compared to the other works.

Input Voltage (V)

Parameter

[3]

ESRFC is improved by 2.8 times over that of the FC counterpart even under the process variation conditions. Also, the slew rate of the ESRFC is achieved at least 14.5 times that of the FC. Meanwhile, the dc gain is almost 19 dB higher than that of FC, and the phase margin maintains at the level of 78°. The comparisons with the prior works are listed in Table 4. Note that the proposed ESRFC has a sufficiently high dc gain even under the low-voltage conditions when compared with the other works. This is attributed to the enhanced effective transconductance. As for the large signal response, the FoML value of the ESRFC is obviously larger than that of other works, which makes the ESRFC more suitable for the large capacitive load. Therefore, the proposed single-stage class-AB ESRFC

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