Ultra-high speed semiconductor devices and low temperature electronics

Ultra-high speed semiconductor devices and low temperature electronics Takashi Mizutani, K. Hirata, M. Hirayama and A. Ishida* NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi-Shi, Kanagawa, 243-01, Japan This paper reviews recent progress in GaAs MESFETs and HBTs for high speed integrated circuits. SAINT MESFETs have succeeded in scaling down gate lengths to O. 1 -O. 15/zm and have realized propagation delay times of 5.9 ps gate -~. A multiplexer and demultiplexer operating at a high bit rate of 11.2 Gbit s -~ has also been developed. HBTs with ballistic collection transistor (BCT) structure have been proposed and have demonstrated highest speeds of 1.9 ps gate -~. High speed frequency dividers operating at 34.8 GHz have also been realized. Quantum interference transistors, which may provide innovations in future high performance devices, are also discussed.

Keywords: low temperature electronics; semiconductors; transistors

Over the last few years, GaAs MESFETs and HBTs have shown rapid increases in complexity and in switching speed. A GaAs MESFET gate array family with 3 K, 5 K and 15 K gates ~, and 32 bit RISC microprocessors implemented with GaAs HBTs 2 has been reported. The increase in complexity has become possible due to improvements in GaAs fabrication technologies. In the field of high speed ICs, high speed multiplexers (MUX) and demultiplexers (DEMUX) operating at 11.2 Gbit s -~ clock rate using 0.15/zm gate SAINT MESFETs have been reported 3. A frequency divider implemented with HBTs has demonstrated the highest toggle frequency of 34.8 GHz (Reference 4). Such a remarkable increase in speed is ascribed to the successful scaling-down of MESFETs and to the use of ballistic collection transistor (BCT) structure for HBTs coupled with advanced fabrication technologies. The remarkable advances in processing technologies have allowed the investigation of quantum transport, which will emerge at device size < 0.1 /zm, and the implementation of quantum effect devices which will operate in a regime where quantum mechanical effects begin to dominate transport, especially at low temperature. This paper reviews the remarkable high speed performance of GaAs MESFETs and HBTs developed in the authors' laboratory and discusses quantum interference transistors as typical examples of quantum effect devices.

example, the SAINT process 5'6, which uses dummy gates for the n + implantation, is shown in Figure 1. A T-shaped resist mask was used for both n + implantation and definition of the Schottky contact area. The top layer size determines the distance between source and drain n + layers, and the bottom layer size determines gate length. The 0.5/.tm top layer pattern, delineated by projection lithography, was transferred to the intermediate layer by RIE. The bottom layer was over-etched by RIE

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*Present address: Sumitomo Electric Industry, Taya-cho, Sakaeku, Yokohama-shi, 244 Japan 0011 - 2 2 7 5 / 9 0 / 1 2 1 0 2 4 - 0 6 © 1990 Butterworth - Heinemann Ltd

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Cryogenics 1990 Vol 30 December

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Ultra-high speed semiconductor devices: T. M~utani et al.

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and T-shaped resist mask formation was completed. The minimum size of the bottom layers was =0.1 /~m, as shown in Figure 2 ~. Suppression of the short channel effect is essential for gate length scaling. Active layer thinning was done by lowering the implantation energy to 10 keV and by rapid thermal annealing. The buried p-layer s underneath the active n-layer formed by Be ion implantation effectively suppresses the short channel effects. A g,,/g,~ ratio > 11 is obtained even for a short gate length of 0.15 /~m (Reference 6). A small standard deviation of the threshold voltage. 75 mV, and a small threshold voltage shift, 400 mV, from that of the long gate field effect transistor (FET) are obtained on a 3 inch (7.5 cm) wafer. These results confirm that short channel effects are sufficiently suppressed fi)r 0.15 /xm gate length FETs to be applied to integrated circuits (ICs). Cut-off frequencies fv and maximum oscillation frequencies f~,,~ obtained by - 6 dB octave -1 extrapolation of gains measured in the frequency region 0.5 - 10 GHz are 90 and 78 GHz, respectively. The propagation delay time evaluated by a ring oscillator is 5.9 ps gate ~, with 31.2 mW gate ~ power dissipation at room temperature v. High speed logic operation is confirmed by fabricating a frequency divider using LSCFL circuit configuration. A maximum toggle frequency of 26.8 GHz is obtained with power dissipation of 84.2 mW TFF -~ (Reference 6). A 2 bit MUX and DEMUX ~ has been developed to investigate the potential for high speed data processing. Two pseudorandom signals with a word length of 223 - 1 were combined into a single high speed signal by the MUX. The two original signals were regenerated by the DEMUX and checked by an error detector. Figure 3 shows the operating waveforms of the MUX and DEMUX at 11.2 Gbit s ~ The output signals have a sufficient voltage swing of 1 gpp with fast rise and fall times of < 35 ps.

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contacts '~) and base collector capacitance (proton implantation t°), reduction of intrinsic delay time was realized by using BCT structure ~1. BCTs use nearballistic high velocity electrons in the E-valley. Schematic band diagrams of BCTs and conventional HBTs are compared in Figure 4 ~2. A distinct difference between BCTs and conventional HBTs is seen in the collector region. The collector layer consists of i - p + - n ~ multilayers

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Cryogenics 1 9 9 0 V o l 30 December

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instead of the n-layer used in conventional HBTs. The i-layer prevents downward bending of the potential in the collector region, and the planar doped p +-layer elevates the i-layer. Thus electron scattering from F- to L-valley is prevented, resulting in high speed electron transport over a wide collector depletion region under a certain collector bias regime. The BCT structure and its epitaxial layer parameters are shown in Figure 5 and Table 1. A planar doped p+-layer (20 nm) is heavily doped (4 × 1019 cm -3) to form a steep potential cliff at a p +/n + collector edge. A base with AlAs fraction from 12 to 0% over 80 nm p +-A1GaAs generates a built-in field of 20 kV cm -1, which makes it possible to reduce base transit time. A heavily Sn-doped collector buffer layer reduces collector resistance. An n+-InGaAs emitter cap with graded n+-InGaAs/GaAs is used to decrease emitter contact resistance. The devices are fabricated by a self-aligned process 13, which allows simultaneous non-alloyed electrode formation of emitter and base in a self-aligned manner. The typical emitter mesa width is 2/zm and base/collector junction width is 3 - 1 0 / ~ m . The concept of 'near-ballistic collection' is revealed in the relation of cut-off frequency fT versus collector bias VCE, as seen in Figure 6 I1. For various collector current densities, fT shows a clear 'hump', which indicates the existence of near ballistic electrons. The VCE value that produces the fT peak increases with increasing collector current, Jc. This behaviour is thought to be due to electron accumulation around the i - p + interface in the

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collector for large Jc, resulting in the higher collector bias necessary to form an appropriate electric field in the collector. The highest fT of 105 GHz is realized at Jc = 5 X 10 4 A cm -2. An outstanding propagation delay time of 1.9 ps gate -1 was reported in a ring oscillator 12. The logic swing is = 400 mV and power dissipation is 44 mW gate-~. High speed logic operation is confirmed by a 1/4 static frequency divider 4. Here, the i - n + collector is used. The operating waveforms at 34.8 GHz input frequency are shown in Figure 7. The minimum input power level is < 0 dBm in the 2 0 - 3 4 . 8 GHz frequency range.

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(= 3 x 107 cm s -t) and large energy separation between the F- and L-valleys ( = 0 . 5 eV), provides an excellent channel for electron devices. Figure 10 summarizes fT for various types of FETs as a function of gate length. In the gate length range 0 . 1 - 0 . 2 5 /xm fT > 100 GHz. The highest fT of 250 GHz is obtained for the InA1As/InGaAs HEMT with 0.12 #m gate t4. InGaAs HEMTs show higher fT than those of GaAs FETs. The fr trend of HBTs is illustrated in Figure 11. InGaAs HBTs have shown rapid improvement over the past two years, taking advantage of the above mentioned superior electron transport. The highest fv of 165 GHz has been obtained at room temperature for InP/InGaAs HBTs~5. At low operating temperatures, such as 80 K, transconductance is increased, and parasitic delay time, such as emitter charging time, becomes relatively small. As a result, a high cut-off frequency of 244 GHz (Reference 16) has been achieved. These results suggest that circuit performance will be improved by using InGaAs material systems instead of GaAs.

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Cryogenics 1990 Vol 30 December

1027

Ultra-high speed semiconductor devices: T. Mizutani et al.

Quantum interference transistor

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When semiconductor devices become very small, the electron wavefunction preserves phase memory within the structure, and terminal characteristics such as the current-voltage relationship reflect the wave nature of electrons. A typical phenomenon is the quantum interference effect of electron waves. It has been of great interest in solid state physics and also in recent quantum effect devices. A typical example of quantum interference is the A h a r o n o v - B o h m effect. It is very pronounced in electron waveguide rings. The conductance of these structures oscillates depending on the phase difference caused by the magnetic field. Yamamoto et al. ~7 have proposed the Aharonov-Bohm quantum interference transistor with a

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superconducting phase-control line for magnetic field application as shown in Figure 12. Due to the magnetic field expulsion effect of the superconductor, the magnetic field generated by the control line is perpendicular to the superconducting ground plane, and does not penetrate the channels. The phase shift is the same for all electrons with different wavenumbers, resulting in a large conductance modulation in the ballistic regime. Thus, the drain to source current Ids can be modulated by up to 100% by superconducting control current Ic(=¢b/M, where M is mutual inductance) as shown by curve (i) in Figure 13. To realize quantum interference devices, it is necessary to meet the following requirements:

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1 large inelastic mean free path (preservation of phase coherence); 2 ballistic electron motion; 3 operation on the lowest transverse sub-band; 4 sharp Fermi surface (T ,~ TF = 30 meV); and 5 equal branch length of the ring. Yamamoto et al. 17 have studied the effect of elastic scattering on conductance modulation, assuming that elastic scattering causes a random phase shift CI'r. In the random phase shift model, the transmission coefficient T is represented as T = (1/2) [ 1 + cos(27rff/cI'0 + QcI'r)]

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Cryogenics 1 9 9 0 Vol 30 December

where Or is a random quantity between 0 and 27r, Q = 1 when elastic scattering occurs and Q = 0 when no elastic scattering occurs. Assuming nearly ballistic transport which corresponds to a small ratio of device length (LD) to elastic scattering length (L0), Ids can be calculated by using a tunnel current formula. The calculated Ids shows that peak current Ip at cI, = 0 (valley current /v at = ~o/2) decreases (increases) in proportion to the LD/Lo ratio, and the on/off ratio becomes small as shown in Figure 13. Datta et al. ~8.,9 have proposed electrostatic quantum interference transistors based on the A h a r o n o v - B o h m effect in two contiguous GaAs quantum wells with FETlike wavelength-control gate. In the electrostatic A h a r o n o v - B o h m effect, the transmission coefficient T depends on kx, resulting in a smaller on/off ratio of Ids than for the magnetic field type interference transistor,

Ultra-high speed semiconductor devices: T. Mizutani et al. even with no elastic scattering. Datta et al. calculated la~ as a function of input gate voltage. The calculated results in Figure 14 show that, for the higher drain voltage of 30 mV, the on/off ratio becomes poor because of a larger amount of electron wave participance with different k~. A geometrically different but operationally similar structure is proposed by Sols 2°, Datta 2~ and Hohkawa et al. 22. This is an electron waveguide 'stubtuner', where the interference comes from electrostatically adjusting the 'length L*" of a stub on a waveguide. Calculated transmission probability depends on the stub number and position. Another example of a quantum interference transistor with a different structure is a 'washboard transistor '2~. Conductivity modulation due to quantum interference in periodic potential was experimentally observed for a two-dimensional electron gas in an A1GaAs/GaAs heterostructure by varying the backgate voltage. Short periodicity, such as 10 nm, is necessary to attain large current density. Although it may be too early to discuss the speed of quantum interference transistors, considering the many challenges which must be met, studying the potential of these devices is worthwhile. Datta et al. TM~9 have predicted a high transconductance of 150 S mm ~. Assuming gate and drain capacitance to be 2.4 fF txm L and neglecting parasitic capacitance, fs = 10 THz, which corresponds to a switching speed of 0.02 ps, was predicted. Considering the low current level (or high impedance of 13 kf~ channel ~), it is important to find configurations with small interconnect capacitance. Yamamoto et al. r have considered connecting transistor output to the next gate through a strip line terminated with characteristic impedance. Even then, mere replacement of the conventional transistors with quantum interference transistors may not be suitable. In addition to generating new device concepts, it may also be necessary to revolutionize circuit architecture.

Summary Recent progress in high speed GaAs MESFETs and HBTs has been described. The remarkable increase in speed of MESFETs is ascribed to successful scaling down. A dummy gate SAINT process, combined with low energy implantation and rapid thermal annealing, has provided high performance MESFETs with 0 . 1 - 0 . 1 5 #m long gates. The propagation delay time is 5.9 ps g a t e ~, with power dissipation of 31.2 mW gate-~. A 2 bit MUX and DEMUX could operate at 11.2 GHz. The HBTs have demonstrated drastic increases in speed on the introduction of BCT structure. The ring oscillator delay time is 1.9 ps gate-~, with 44 mW gate-~ power dissipation. A high speed logic operation is also confirmed by a frequency divider operating at 34.8 GHz.

For further improvements in switching speed, the high speed potential of the InGaAs material system was discussed. Finally, quantum interference transistors were considered as candidates for innovation in future high performance devices. The importance of elastic scattering and drain bias was pointed out.

Acknowledgements The authors would like to thank Dr T. Ishibashi and Dr Y. Yamauchi for fruitful comments on HBTs, Y. Yamane, T. Enoki and M. Ohhata for comments on SAINT MESFETs and M. Yamamoto for comments on quantum interference transistors.

References 1 Lee, G., Canaga, S., Terrell, B. and Deyhimy, I. Technical Digest GaAs IC Symposium IEEE, San Diego, USA (1989) 3 3 - 3 6 2 Whitmire, D.V., Gareia, V. and Evans, S. ISSCC Dig Tech Pap (1989) 34-35 3 Ohhata, M., Yamane, Y., Enoki, T., Sugitani, S., Kato, N. and Hirayama, M. paper presented at International Symposium on GaAs and Related Compounds, Karuizawa, Japan (1989) 4 Yamauchi, Y., Nakajima, O., Nagata, K., Ito, H. and Ishibashi, T. Technical Digest GaAs IC Symposium (1989) 121- 124 5 Yamasaki, K., Asai, K., Mizutani, T. and Kurumada, K. Electron Len (1982) 18 119-121 6 Enoki, T., Sugitani, S. and Yamane, Y. Electron Lett (1989) 25 512-513 7 Yamane, Y., Enoki, T., Sugitani, S. and Hirayama, M. Tech Dig IEDM (1988) 894-896 8 Yamasaki, K., Kato, N. and Hirayama, M. IEEE Trans Elect Dev (1985) ED-32 2420-2425 9 Ninono, H., lto, H., Nakajima, O. and lshibashi, T. Jpn J Appl Phvs (1986) 25 L865 10 Nakajima, O., Nagata, K., Yamauchi, Y., Ito, H. and Ishibashi, T. Tech Dig IEDM (1986) 266 I 1 Ishibashi, T. and Yamauchi, Y. IEEE Trans Elect Dev (1988) 35 401 404 12 Ishibashi, T., Nakajima, O., Nagata, K., Yamauchi, Y., Ito, H. and Nittono, T. Tech Dig IEDM (1988) 826-829 13 Nagata, K., Nakajima, O., Yamauchi, Y., Nittono, T., Ito, H. and Ishibashi, T. IEEE Trans Elect Dev (1988) ED-35 2 - 7 14 Mishra, U., Brown, A., Jelloian, L., Thompson, M., Nguyen, L. and Rosenbaum, S. Tech Dig IEDM (1989) 101-104 15 Chen, Y., Nonenburg, R., Panish, M., Harem, R. and Humphrey, D. IEEE Elec Dev Len (1989) 10 267-269 16 Chen, Y., Levi, A., Nottenburg, R., Beton, P. and Panish, M. Appl Phvs la,tt (1989) 23 1789-1791 17 Yamamoto, M. and Hohkawa, K. extended abstract presented at Solid State Devices and Materials, Tokyo, Japan (1988) 495-498 18 Dana, S., Melloch, M., Bandyopadhyay, S., Noren, R., Vaziri, M., Miller, M. and Reifenberger, R. Phvs Rev Lett (1985) 55 2344 2347 19 Dana, S., Meiloch, M., Bandyopadhyay, S., Lundstrom, M. Appl Phvs Lett (1986) 48 487-489 20 Sols, F. J Appl Phys (1989) 66 3892-3906 21 Datta, S. paper presented at 4th International Conference on Superlattices. Microstructures and Microdeviees. Trieste. Italy (August 1988) 22 Hohkawa, K. and Yamamoto, M. Tech Rep lnst Electron lnfo Commun E,lg Jpn (1988) ED88-92 23 Tokura, Y. and Tsuhaki, K. Appl Phv,s Lett (1987) 51 1807 - 1808

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