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Useful Constants and Formulas
APPENDIX A
Useful Constants and Formulas
A.1 Physical constants Constant
Symbol
Value
Boltzmann’s constant
k
1.38 1023 J/K
Charge of an electron
q
1.6 1019 C
Thermal voltage at 300K
kT/q
0.026 V
Permittivity of free space
ε0
8.854 1014 F/cm
Permittivity of silicon
εSi
11.68ε0 ¼ 1.03 1012 F/cm
Permittivity of SiO2
εox
3.9ε0 ¼ 3.45 1013 F/cm
Concentration of carriers in intrinsic silicon
ni
1.45 1010 C/cm3
Silicon effective density of states
Nc, Nv
Nc ¼ 3.2 1019 cm3 Nv ¼ 1.8 1019 cm3
Silicon band gap at 300K
Eg
1.12 eV
A.2 Formulas 1 mq2 ni l Resistance: R ¼ r A Carrier concentrations in doped materials:
Resistivity: r ¼
n ¼ Nd eðEd Ef Þ=kT ¼
n2i ; Na
p ¼ Na eðEf Ea Þ=kT ¼
n2i Nd
229
230
Appendix A
Difference between Fermi levels in doped and intrinsic material: jB ¼
kT Na ln q ni
Holeeelectron product in equilibrium: np ¼ n2i ¼ Nc Nv eEg =kT qDn np0 qDp pn0 Shockley diode characteristic: J ¼ J0 eqV=KT 1 ; J0 ¼ þ Ln Lp εox kT Na MOS capacitor: Cox ¼ ;j ¼ 2jB ¼ 2 ln q tox s;inv ni MOSFET long-channel characteristics: Cutoff Vgs < Vt
Idn ¼ 0
Linear Vds < Vgs Vt
Idn ¼ kn0
Saturation Vds Vgs Vt
Idn ¼
W 1 2 ðVgs Vtn ÞVds Vds L 2
1 0W k ðVgs Vtn Þ2 2 nL
kT Cdm Subthreshold swing: S ¼ 2:3 1þ q Cox Rayleigh’s criterion: < ¼ k1 Yield: Y ¼ eAD
Middle voltage: VM
l NA
sffiffiffiffiffiffi bp ðVDD jVtp jÞ þ Vtn bn sffiffiffiffiffi ¼ bp 1þ bn
Rlin þ Rsat 10VB þ 3Vt ¼ 2 6bVB2 Delay (0e50%): td ¼ 0.69RtCL Effective resistance. Rt ¼
Transition time (10e90%): trf ¼ 2.2RtCL Optimal tapered driver chain: a ¼ e; n ¼ ln 2 Switching energy: Es ¼ CL VDD
Cbig C1
2 Switching power: Ps ¼ fCL VDD ^ ^t 1 R Ideal scaling: ¼ ; ¼ x t x R Thermodynamic noise error probability: Perr ¼ eEb =kT nImax tmax Decoupling capacitance: CD ¼ DV
Appendix A
Elmore delay for arbitrary section sizes: dE ¼
P
ci
1in
1 Elmore delay for uniform wire: dE ¼ rcnðn þ 1Þ 2 CC Crosstalk: DVV ¼ DVA C þ CC Clock period: T D þ ts þ th tSH S=s e Metastability: PF ¼ T Buffered wire delay:
P 1 j i
rj
1 n n n tbwire ¼ N½ðRb þ rÞc þ ð 1Þð 2Þrc þ ð r þ Rb ÞðCb þ cÞ 2 N N N Bus delay: dbus ¼ k1 ðCL NÞ1=k þ k2 N 2 1 Amdahl’s Law: SðnÞ ¼ P ð1 PÞ þ N Vbl Cline DRAM voltages: ¼ Vline Cline þ Cbit Cache: tav ¼ thitphit þ tmiss(1 phit) ¼ thit[phit þ M(1 phit)] Magnetic disk: Taccess ¼ Tseek þ Trot þ TRW Paging performance: tpage ¼ tres ½ pres þ Md ð1 pres Þ tpage;SSD pres þ Mssd ð1 pres Þ Relative paging performance: ¼ pres þ Mmag ð1 pres Þ tpage;mag Peukart’s Law: In ¼ C G2 DVFS: EDVFS ¼ nC 2 T RTD: ERTD ¼ n[CV2 þ L] Heat sink: TJ ¼ TA þ PQ Fourier’s Law of Heat Conduction: T ¼ PR dQ ¼ hADT, TðtÞ ¼ TA þ ðTð0Þ TA Þet=t0 Newton’s Law of Cooling: dt Steady-state junction temperature: TJ ¼ TA þ PQ RC temperature model: TðtÞ ¼ ðT0 PRÞet=RC þ PR þ TA Peak-to-peak ratio:
Tp 1 eK ¼ H 1 þ eK
Arrhenius’s equation: r ¼ AeEa =kT Chip life versus temperature: 4th ¼
Rt
1
0 kTðtÞ e
Ea =kTðtÞ
231
Useful Constants and Formulas
A.1 Physical constants Constant
Symbol
Value
Boltzmann’s constant
k
1.38 1023 J/K
Charge of an electron
q
1.6 1019 C
Thermal voltage at 300K
kT/q
0.026 V
Permittivity of free space
ε0
8.854 1014 F/cm
Permittivity of silicon
εSi
11.68ε0 ¼ 1.03 1012 F/cm
Permittivity of SiO2
εox
3.9ε0 ¼ 3.45 1013 F/cm
Concentration of carriers in intrinsic silicon
ni
1.45 1010 C/cm3
Silicon effective density of states
Nc, Nv
Nc ¼ 3.2 1019 cm3 Nv ¼ 1.8 1019 cm3
Silicon band gap at 300K
Eg
1.12 eV
A.2 Formulas 1 mq2 ni l Resistance: R ¼ r A Carrier concentrations in doped materials:
Resistivity: r ¼
n ¼ Nd eðEd Ef Þ=kT ¼
n2i ; Na
p ¼ Na eðEf Ea Þ=kT ¼
n2i Nd
229
230
Appendix A
Difference between Fermi levels in doped and intrinsic material: jB ¼
kT Na ln q ni
Holeeelectron product in equilibrium: np ¼ n2i ¼ Nc Nv eEg =kT qDn np0 qDp pn0 Shockley diode characteristic: J ¼ J0 eqV=KT 1 ; J0 ¼ þ Ln Lp εox kT Na MOS capacitor: Cox ¼ ;j ¼ 2jB ¼ 2 ln q tox s;inv ni MOSFET long-channel characteristics: Cutoff Vgs < Vt
Idn ¼ 0
Linear Vds < Vgs Vt
Idn ¼ kn0
Saturation Vds Vgs Vt
Idn ¼
W 1 2 ðVgs Vtn ÞVds Vds L 2
1 0W k ðVgs Vtn Þ2 2 nL
kT Cdm Subthreshold swing: S ¼ 2:3 1þ q Cox Rayleigh’s criterion: < ¼ k1 Yield: Y ¼ eAD
Middle voltage: VM
l NA
sffiffiffiffiffiffi bp ðVDD jVtp jÞ þ Vtn bn sffiffiffiffiffi ¼ bp 1þ bn
Rlin þ Rsat 10VB þ 3Vt ¼ 2 6bVB2 Delay (0e50%): td ¼ 0.69RtCL Effective resistance. Rt ¼
Transition time (10e90%): trf ¼ 2.2RtCL Optimal tapered driver chain: a ¼ e; n ¼ ln 2 Switching energy: Es ¼ CL VDD
Cbig C1
2 Switching power: Ps ¼ fCL VDD ^ ^t 1 R Ideal scaling: ¼ ; ¼ x t x R Thermodynamic noise error probability: Perr ¼ eEb =kT nImax tmax Decoupling capacitance: CD ¼ DV
Appendix A
Elmore delay for arbitrary section sizes: dE ¼
P
ci
1in
1 Elmore delay for uniform wire: dE ¼ rcnðn þ 1Þ 2 CC Crosstalk: DVV ¼ DVA C þ CC Clock period: T D þ ts þ th tSH S=s e Metastability: PF ¼ T Buffered wire delay:
P 1 j i
rj
1 n n n tbwire ¼ N½ðRb þ rÞc þ ð 1Þð 2Þrc þ ð r þ Rb ÞðCb þ cÞ 2 N N N Bus delay: dbus ¼ k1 ðCL NÞ1=k þ k2 N 2 1 Amdahl’s Law: SðnÞ ¼ P ð1 PÞ þ N Vbl Cline DRAM voltages: ¼ Vline Cline þ Cbit Cache: tav ¼ thitphit þ tmiss(1 phit) ¼ thit[phit þ M(1 phit)] Magnetic disk: Taccess ¼ Tseek þ Trot þ TRW Paging performance: tpage ¼ tres ½ pres þ Md ð1 pres Þ tpage;SSD pres þ Mssd ð1 pres Þ Relative paging performance: ¼ pres þ Mmag ð1 pres Þ tpage;mag Peukart’s Law: In ¼ C G2 DVFS: EDVFS ¼ nC 2 T RTD: ERTD ¼ n[CV2 þ L] Heat sink: TJ ¼ TA þ PQ Fourier’s Law of Heat Conduction: T ¼ PR dQ ¼ hADT, TðtÞ ¼ TA þ ðTð0Þ TA Þet=t0 Newton’s Law of Cooling: dt Steady-state junction temperature: TJ ¼ TA þ PQ RC temperature model: TðtÞ ¼ ðT0 PRÞet=RC þ PR þ TA Peak-to-peak ratio:
Tp 1 eK ¼ H 1 þ eK
Arrhenius’s equation: r ¼ AeEa =kT Chip life versus temperature: 4th ¼
Rt
1
0 kTðtÞ e
Ea =kTðtÞ
231