- Email: [email protected]
Vector classification of SMD images
Journal of Manufacturing Systems Vol. 23/No. 4 2004
2003-2004 abstract and ke cword index Keywords: LOM, Octrees, Computational Geometry
dling, Semiconductor Cluster Tools, Flexible Automation, Routing Flexibility, Manufacturing Real-Time Control
Journal of Manufacturing Systems Volume 22, Number 4, 2003
HeM Improvement in WaferPlanarization: Modeling and Simulation, Sutee Eamkajornsiri, Ranga Narayanaswami, Abhijit Chandra, v22, n3, 2003, pp239-247 Chemical mechanical polishing (CMP) is a planarization process that produces high-quality surfaces both locally and globally. CMP is one of the key process steps during the fabrication of very large scale integrated (VLSI) chips in integrated circuit manufacturing. CMP consists of a chemical process and a mechanical process being performed together to reduce height variation across a wafer. High and reliable wafer yield, which is dependent on uniformity of the material removal rate across the entire wafer, is of critical importance in the CMP process. In this paper, the variations in the material removal rate across the wafer are analytically modeled assuming a rigid wafer and a flexible polishing pad. The wafer pad contact is modeled as the indentation of a rigid indenter on an elastic half-space. The model predictions are first verified against experimental observations. Simulation results for wafer yield under openloop processing conditions are presented. Wafer curvature is identified as a key design variable influencing the spatial distribution of the material removal rate. The proposed model can be applied to control wafer-scale material removal rate variations in a CMP process. Keywords: Deadlock Detection and Resolution, Graph Theory, FMS Planning and Scheduling, Deadlock Handling, Semiconductor Cluster Tools, Flexible Automation, Routing Flexibility, Manufacturing Real-Time Control
Vector Classification of SMD Images, J. Rene Villalobos, Miguel Arellano, Adolfo Medina, Fernando Aguirre, v22, n4, 2003, pp265-282 The automated visual inspection of surface-mounted devices (SMD) requires the correct classification of an image as either "component present" or "component absent." The inspection system must allow the classification to be fast and reliable while also assuring that the training of the classifier is simple and not time consuming. The traditional sequential approach to classifying images, while simple to implement, presents some disadvantages, including an increase in false alarm (type I) errors and the need for a time-consuming training phase. The method presented in this paper seeks to reduce classification errors by using a vector approach for the inspection of components. An experiment using real SMD inspection data is conducted to validate the performance of the proposed vector classifier. The results of the experiment support the hypothesis that the vector-based inspection approach renders fewer errors than the sequential inspection approach. Keywords: Electronics Assembly, Vector Classifier, Automated Visual Inspection (AVI), Multivariate Discrimination
Geometric Techniques for Efficient Waste Removal in LOM, Pang King Wah, Ajay Joneja, v22, n3, 2003,
A Framework for Reducing Manufacturing Throughput Time, Danny J. Johnson, v22, n4, 2003, pp283-298
pp248-263 A new CAPP system is proposed for the layered manufacturing technology of LOM (laminated object manufacturing). The traditional technique wastes much effort and time in the generation of rectangular grid patterns onto the exterior of the model to facilitate waste removal. In the proposed approach, several geometric properties of the model are exploited to dramatically reduce the waste removal grids. This, in turn, leads to reduced build time with no effect on the build quality. The proposed method uses parting planes similar to those used in mold design in regions external to the part's convex hull, and an octree decomposition in the remaining regions. An integrated CAPP system incorporating these ideas has been developed, and several example parts demonstrate the efficiencies that the system delivers.
Manufacturing throughput time reduction can be a daunting task due to the many factors that influence it and their complex interactions. However, there are basic principles that, if applied correctly, can be used to reduce manufacturing throughput time. This paper presents a conceptual framework that illustrates these principles. The framework illustrates the factors that influence manufacturing throughput time, the actions that can be taken to alter each factor, and their interactions. The framework is detailed enough to provide guidance to the industry practitioner on how to reduce manufacturing throughput time, while being general enough to apply to most manufacturing situations. Keywords: Throughput Time, Throughput Time Reduction, Lead Time Reduction, Quick Response Manufacturing
333
2003-2004 abstract and ke cword index Keywords: LOM, Octrees, Computational Geometry
dling, Semiconductor Cluster Tools, Flexible Automation, Routing Flexibility, Manufacturing Real-Time Control
Journal of Manufacturing Systems Volume 22, Number 4, 2003
HeM Improvement in WaferPlanarization: Modeling and Simulation, Sutee Eamkajornsiri, Ranga Narayanaswami, Abhijit Chandra, v22, n3, 2003, pp239-247 Chemical mechanical polishing (CMP) is a planarization process that produces high-quality surfaces both locally and globally. CMP is one of the key process steps during the fabrication of very large scale integrated (VLSI) chips in integrated circuit manufacturing. CMP consists of a chemical process and a mechanical process being performed together to reduce height variation across a wafer. High and reliable wafer yield, which is dependent on uniformity of the material removal rate across the entire wafer, is of critical importance in the CMP process. In this paper, the variations in the material removal rate across the wafer are analytically modeled assuming a rigid wafer and a flexible polishing pad. The wafer pad contact is modeled as the indentation of a rigid indenter on an elastic half-space. The model predictions are first verified against experimental observations. Simulation results for wafer yield under openloop processing conditions are presented. Wafer curvature is identified as a key design variable influencing the spatial distribution of the material removal rate. The proposed model can be applied to control wafer-scale material removal rate variations in a CMP process. Keywords: Deadlock Detection and Resolution, Graph Theory, FMS Planning and Scheduling, Deadlock Handling, Semiconductor Cluster Tools, Flexible Automation, Routing Flexibility, Manufacturing Real-Time Control
Vector Classification of SMD Images, J. Rene Villalobos, Miguel Arellano, Adolfo Medina, Fernando Aguirre, v22, n4, 2003, pp265-282 The automated visual inspection of surface-mounted devices (SMD) requires the correct classification of an image as either "component present" or "component absent." The inspection system must allow the classification to be fast and reliable while also assuring that the training of the classifier is simple and not time consuming. The traditional sequential approach to classifying images, while simple to implement, presents some disadvantages, including an increase in false alarm (type I) errors and the need for a time-consuming training phase. The method presented in this paper seeks to reduce classification errors by using a vector approach for the inspection of components. An experiment using real SMD inspection data is conducted to validate the performance of the proposed vector classifier. The results of the experiment support the hypothesis that the vector-based inspection approach renders fewer errors than the sequential inspection approach. Keywords: Electronics Assembly, Vector Classifier, Automated Visual Inspection (AVI), Multivariate Discrimination
Geometric Techniques for Efficient Waste Removal in LOM, Pang King Wah, Ajay Joneja, v22, n3, 2003,
A Framework for Reducing Manufacturing Throughput Time, Danny J. Johnson, v22, n4, 2003, pp283-298
pp248-263 A new CAPP system is proposed for the layered manufacturing technology of LOM (laminated object manufacturing). The traditional technique wastes much effort and time in the generation of rectangular grid patterns onto the exterior of the model to facilitate waste removal. In the proposed approach, several geometric properties of the model are exploited to dramatically reduce the waste removal grids. This, in turn, leads to reduced build time with no effect on the build quality. The proposed method uses parting planes similar to those used in mold design in regions external to the part's convex hull, and an octree decomposition in the remaining regions. An integrated CAPP system incorporating these ideas has been developed, and several example parts demonstrate the efficiencies that the system delivers.
Manufacturing throughput time reduction can be a daunting task due to the many factors that influence it and their complex interactions. However, there are basic principles that, if applied correctly, can be used to reduce manufacturing throughput time. This paper presents a conceptual framework that illustrates these principles. The framework illustrates the factors that influence manufacturing throughput time, the actions that can be taken to alter each factor, and their interactions. The framework is detailed enough to provide guidance to the industry practitioner on how to reduce manufacturing throughput time, while being general enough to apply to most manufacturing situations. Keywords: Throughput Time, Throughput Time Reduction, Lead Time Reduction, Quick Response Manufacturing
333