- Email: [email protected]
Wave soldering concerns for surface mount assemblies
World Abstracts on Microelectronics and Reliability
827
4. MICROELECTRONICS---GENERAL impartunee and impact of the just-in-time pbilo~lJy. R. AERTS,P. BECH and J. P. I~ F ~ c . Electr. Commun. 63(2), 115 (1989). The "just-in-time" philosophy, or JIT, is conceptually simple, but has a number of important implications for businesses that use it. Consequently, the application and introduction of JIT has almost as many variations as there are installations. The complexity of JIT can vary from sophisticated computer-controlled systems to simple commonsense adjustments on the factory
floor. When fully implemented, JIT involves the complete delivery chain for a product; it is not only a method for decreasing inventory in the stores, on the factory floor, and in the finished goods store. The authors describe how the JIT philosophy has been applied by three Alcatel Units, concentrating on the manufacturing part of the delivery chain, and how one of these Units has combined JIT with the "Theory of Constraints" to alleviate manufacturing bottlenecks.
5. MICROELECTRONICS--DESIGN AND CONSTRUCTION Wave soldering concerns for surface mount assemblies. D. A.
ELLIOTT. Circuit WId 15(4), 25 (1989). For over 30 years, wave soldering has been the most popular and most economical method for mass soldering of electronic assemblies. For conventional circuits, this is a mature technology. Training, proper board design, process control during board fabrication, assembly and soldering and, finally, an awareness of the need for solderability have resulted in very high manufacturing yields in some companies with the associated high quality and much improved profits which result from doing it right the first time. With the introduction of surface mount technology, the same concerns need to be addressed. However, because of the smaller size of components and higher densities, new problems arise. This paper presents some of the concerns encountered in wave soldering of surface mount assemblies. An improved self-aligned silieide process for VLSI, AWATMt StNGHand W. S. KHOKLE.Microelectron. J. 20(4), 11 (1989). An improved self-aligned silicide process has been developed for VLSI applications. This process requires no spacer oxide walls. A 6-#m feature size exchange IC was employed as the test vehicle. The titanium disilicide and cobalt disilicide were used as the silicides at the S, D and G levels. These were formed by two-step vacuum annealing methods. Excellent results were obtained with both of these silicides. The sheet resistance of TiSi2 (1[2 sq -I ) was lower than that of CoSi2 (15 fl sq-I). SEM has shown no lateral growth with either silicide. Further work is continuing to implement it in a test vehicle of 2-3-/~m feature size. Particle-free wafer cleaning and drying technology. H. MISHIMA, T. YASUI, T. MIZUNIWA, M. ABE and T. OHML IEEE Trans. Semicond. Mfg 2(3), 69 (1989). Wet chemical processes occupy a very important position in ULSI fabrication technologies. With increasing pattern densities of ULSI devices, a contamination-free cleaning and drying system has been increasingly required. For removal of particulate contaminants from silicon wafers by chemical solution treatment, it has been found that the NH4OH-H20 solution is excellent and the ratio of NH4OH in the solution can be reduced to i/10 of the standard ratio while keeping high removal efficiency. By decreasing the NH4OH content, wafer damage which appears as a so-called haze during the NH4OH-H202 treatment will be reduced. For drying, to establish a particle-free wafer drying system, the particle generation-free isopropanol (IPA) vapor drying system has been developed. By eliminating all possible particle generation sources from the drying system, ultraclean wafer drying equipment has been realized. A number of technical items to be controlled have been thoroughly investigated. As a result, three technical items were found to influence seriously the surface cleanliness after drying: the water content in IPA, the temperature distribution around wafers, and the IPA vapor velocity. The optimum drying conditions in which high quality of wafer surface cleanliness can be realized were confirmed experimentally.
MetalliT~ttiun tecimoingles for ULSI. J. M. MARTIN~ZD U ~ T and J. M. ALaELLA.Vacuum 39(7/8), 749 (1989). This paper presents and up-to-date review of the metallization technologies for ultra-large-scale integration (ULSI) microelectronic circuits for which the device feature size is in the submicron range. The review begins with a brief exposition of the metallization techniques, emphasizing chemical vapour deposition (CVD), especially tungsten CVD which allows the possibility of selective deposition. Ohmic contacts to silicon are reviewed, particularly those using silicides. Novel materials such as nitrides used as diffusion barriers are also treated. The case of gate contacts is studied, including the silicides of refractory metals deposited on top of polysilicon (polycides), as they are needed in submicron devices. Special emphasis is given to the self-aligned silicide or salicide technology. Next we focus our attention on the interconnects, as the surface area of an ULSI chip is dominated by them. In this context, the problem of the electromigration and corrosion of the interconnects is of paramount significance in the reliability of ULSI devices. Finally, we treat multilevel interconnections, one of the most demanding technologies in ULSI. X-Ray inspection aids process control. RICHARDN X ~ . Electron. Prod. 33 (July 1989). Improved first-time yields of a SMT assembly process can be achieved by implementing statistical process control and by employing automated X-ray inspection. Ultra-reliable packaging for s i l l e o ~ c e a WSI. JOHNK. HAGGE.IEEE Trans. Compon. Hybrids mfg Technol. 12(2), 170 (1989). Silicon-on-silicon WSI (wafer-scales integration) packaging provides electronic equipments with significant reductions in size, weight, cost, and IC junction temperatures, together with significant increases in reliability and high-speed electrical performance. The new packaging technique combines semiconductor lithography techniques, printed circuit muitilayer techniques, and hybrid multichip module techniques. The silicon substrate has multiple layers of metallization and dielectric and serves as a "silicon circuit board". This paper discusses the advantages of using silicon instead of conventional ceramic as the substrate material, and reviews the published status of this technology at other organizations. Although conventional hybrid packages are successfully being used in early implementations to reduce size and weight, there exists an untapped potential for significant reliability improvements by switching to packages specifically designed for silicon substrates. Several potential packaging approaches are reviewed and results are presented for the fatigue life and thermal performance of silicon substrates. Introduction of mrfaee mounted device tecimole~. P. MVY.SEM~Cr~R, W. ROZUI~K and R. TARR~U. Electr. Commun. 63(2), 122 (1989). The use of SMDs (surface mounted devices) has been commonly considered as a revolution in the electronics industry in view of the size or
827
4. MICROELECTRONICS---GENERAL impartunee and impact of the just-in-time pbilo~lJy. R. AERTS,P. BECH and J. P. I~ F ~ c . Electr. Commun. 63(2), 115 (1989). The "just-in-time" philosophy, or JIT, is conceptually simple, but has a number of important implications for businesses that use it. Consequently, the application and introduction of JIT has almost as many variations as there are installations. The complexity of JIT can vary from sophisticated computer-controlled systems to simple commonsense adjustments on the factory
floor. When fully implemented, JIT involves the complete delivery chain for a product; it is not only a method for decreasing inventory in the stores, on the factory floor, and in the finished goods store. The authors describe how the JIT philosophy has been applied by three Alcatel Units, concentrating on the manufacturing part of the delivery chain, and how one of these Units has combined JIT with the "Theory of Constraints" to alleviate manufacturing bottlenecks.
5. MICROELECTRONICS--DESIGN AND CONSTRUCTION Wave soldering concerns for surface mount assemblies. D. A.
ELLIOTT. Circuit WId 15(4), 25 (1989). For over 30 years, wave soldering has been the most popular and most economical method for mass soldering of electronic assemblies. For conventional circuits, this is a mature technology. Training, proper board design, process control during board fabrication, assembly and soldering and, finally, an awareness of the need for solderability have resulted in very high manufacturing yields in some companies with the associated high quality and much improved profits which result from doing it right the first time. With the introduction of surface mount technology, the same concerns need to be addressed. However, because of the smaller size of components and higher densities, new problems arise. This paper presents some of the concerns encountered in wave soldering of surface mount assemblies. An improved self-aligned silieide process for VLSI, AWATMt StNGHand W. S. KHOKLE.Microelectron. J. 20(4), 11 (1989). An improved self-aligned silicide process has been developed for VLSI applications. This process requires no spacer oxide walls. A 6-#m feature size exchange IC was employed as the test vehicle. The titanium disilicide and cobalt disilicide were used as the silicides at the S, D and G levels. These were formed by two-step vacuum annealing methods. Excellent results were obtained with both of these silicides. The sheet resistance of TiSi2 (1[2 sq -I ) was lower than that of CoSi2 (15 fl sq-I). SEM has shown no lateral growth with either silicide. Further work is continuing to implement it in a test vehicle of 2-3-/~m feature size. Particle-free wafer cleaning and drying technology. H. MISHIMA, T. YASUI, T. MIZUNIWA, M. ABE and T. OHML IEEE Trans. Semicond. Mfg 2(3), 69 (1989). Wet chemical processes occupy a very important position in ULSI fabrication technologies. With increasing pattern densities of ULSI devices, a contamination-free cleaning and drying system has been increasingly required. For removal of particulate contaminants from silicon wafers by chemical solution treatment, it has been found that the NH4OH-H20 solution is excellent and the ratio of NH4OH in the solution can be reduced to i/10 of the standard ratio while keeping high removal efficiency. By decreasing the NH4OH content, wafer damage which appears as a so-called haze during the NH4OH-H202 treatment will be reduced. For drying, to establish a particle-free wafer drying system, the particle generation-free isopropanol (IPA) vapor drying system has been developed. By eliminating all possible particle generation sources from the drying system, ultraclean wafer drying equipment has been realized. A number of technical items to be controlled have been thoroughly investigated. As a result, three technical items were found to influence seriously the surface cleanliness after drying: the water content in IPA, the temperature distribution around wafers, and the IPA vapor velocity. The optimum drying conditions in which high quality of wafer surface cleanliness can be realized were confirmed experimentally.
MetalliT~ttiun tecimoingles for ULSI. J. M. MARTIN~ZD U ~ T and J. M. ALaELLA.Vacuum 39(7/8), 749 (1989). This paper presents and up-to-date review of the metallization technologies for ultra-large-scale integration (ULSI) microelectronic circuits for which the device feature size is in the submicron range. The review begins with a brief exposition of the metallization techniques, emphasizing chemical vapour deposition (CVD), especially tungsten CVD which allows the possibility of selective deposition. Ohmic contacts to silicon are reviewed, particularly those using silicides. Novel materials such as nitrides used as diffusion barriers are also treated. The case of gate contacts is studied, including the silicides of refractory metals deposited on top of polysilicon (polycides), as they are needed in submicron devices. Special emphasis is given to the self-aligned silicide or salicide technology. Next we focus our attention on the interconnects, as the surface area of an ULSI chip is dominated by them. In this context, the problem of the electromigration and corrosion of the interconnects is of paramount significance in the reliability of ULSI devices. Finally, we treat multilevel interconnections, one of the most demanding technologies in ULSI. X-Ray inspection aids process control. RICHARDN X ~ . Electron. Prod. 33 (July 1989). Improved first-time yields of a SMT assembly process can be achieved by implementing statistical process control and by employing automated X-ray inspection. Ultra-reliable packaging for s i l l e o ~ c e a WSI. JOHNK. HAGGE.IEEE Trans. Compon. Hybrids mfg Technol. 12(2), 170 (1989). Silicon-on-silicon WSI (wafer-scales integration) packaging provides electronic equipments with significant reductions in size, weight, cost, and IC junction temperatures, together with significant increases in reliability and high-speed electrical performance. The new packaging technique combines semiconductor lithography techniques, printed circuit muitilayer techniques, and hybrid multichip module techniques. The silicon substrate has multiple layers of metallization and dielectric and serves as a "silicon circuit board". This paper discusses the advantages of using silicon instead of conventional ceramic as the substrate material, and reviews the published status of this technology at other organizations. Although conventional hybrid packages are successfully being used in early implementations to reduce size and weight, there exists an untapped potential for significant reliability improvements by switching to packages specifically designed for silicon substrates. Several potential packaging approaches are reviewed and results are presented for the fatigue life and thermal performance of silicon substrates. Introduction of mrfaee mounted device tecimole~. P. MVY.SEM~Cr~R, W. ROZUI~K and R. TARR~U. Electr. Commun. 63(2), 122 (1989). The use of SMDs (surface mounted devices) has been commonly considered as a revolution in the electronics industry in view of the size or