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4408304 Semiconductor memory
192
New Patents
4408386 METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES Tetsuya Takayashiki, Taij Usui, Tetsuma Sakurai, Tokyo, Japan assigned to Oki Electric Industry Co Ltd; Nippon Telegraph and Telephone Public Corporati Spaced recesses are formed in a surface of a low impurity concentration P type single-crystal substrate by using a mask. A P type impurity is diffused at a high concentration into an entire surface of the substrate including the recesses to form a P type diffused layer, and an N type layer is epitaxially grown on the P type diffused layer. Then, mask layers are formed on bottom surfaces of the recesses in the epitaxially grown N type layer and this N type layer is anisotropically etched by using the mask layers to form island regions in the recesses. After removing the mask layers, N type diffused layers are formed to cover the island regions. An insulating film (SiO2) acting to isolate completed transistor elements is formed on the P and N type diffused layers, and a polycrystalline silicon layer acting as a support of a dielectrically isolated integrated circuit device is formed on the insulating film. Then, the rear surface of the single-crystal silicon substrate is ground off to expose the insulating film. MOS or bipolar type transistor elements are formed in the island regions to obtain a dielectrically isolated semiconductor integrated device.
4408385 SEMICONDUCTOR INTEGRATED CIRCUIT WITH IMPLANTED RESISTOR ELEMENT IN POLYCRYSTALLINE SILICON LAYER Rao G R Mohan, John S Stanczak, Jih-chan Lien, Shyam Bhatia assigned to Texas Instruments Incorporated
gate for an MOS transistor and as an interconnection overlying field oxide. Resistors of this type are ideally suited for load devices in static RAM cells.
4408304 SEMICONDUCTOR MEMORY Jun-ichi Nishizawa, Ohmi Tadahiro, Takashige Tamamushi, Sendai, Japan assigned to Semiconductor Research Foundation i
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A semiconductor memory is provided with a hook structure composed of first to fourth regions and is capable of non-destructive readout. The third and fourth regions of the hook structure are both made floating and each form one of main electrode regions of each of a write and/or refresh transistor and a readout transistor. Carriers which are injected from the other main electrode region of the write transistor are stored as excess majority carriers in the third region and majority carriers of the fourth region flow out therefrom into the first region via the third and second regions, in consequence of which the fourth region lacks in the majority carrier and voltages of the floating third and fourth regions vary. The voltage variation of the fourth region is read out by the readout transistor. The excess majority carriers stored in the third region flow out therefrom into the other main electrode region of the write transistor and become extinct when it operates as a refresh transistor.
4404662 METHOD AND CIRCUIT FOR ACCESSING AN INTEGRATED SEMICONDUCTOR MEMORY Charles Masenas assigned to International Business Machines Corporation
Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a
A memory system is provided having an array of cells, each of which may include first and second cross-coupled inverting NPN transistors and first and second PNP transistors for injecting charge into the first and second inverting transistors. A first bit/sense line of a bit/sense line
New Patents
4408386 METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES Tetsuya Takayashiki, Taij Usui, Tetsuma Sakurai, Tokyo, Japan assigned to Oki Electric Industry Co Ltd; Nippon Telegraph and Telephone Public Corporati Spaced recesses are formed in a surface of a low impurity concentration P type single-crystal substrate by using a mask. A P type impurity is diffused at a high concentration into an entire surface of the substrate including the recesses to form a P type diffused layer, and an N type layer is epitaxially grown on the P type diffused layer. Then, mask layers are formed on bottom surfaces of the recesses in the epitaxially grown N type layer and this N type layer is anisotropically etched by using the mask layers to form island regions in the recesses. After removing the mask layers, N type diffused layers are formed to cover the island regions. An insulating film (SiO2) acting to isolate completed transistor elements is formed on the P and N type diffused layers, and a polycrystalline silicon layer acting as a support of a dielectrically isolated integrated circuit device is formed on the insulating film. Then, the rear surface of the single-crystal silicon substrate is ground off to expose the insulating film. MOS or bipolar type transistor elements are formed in the island regions to obtain a dielectrically isolated semiconductor integrated device.
4408385 SEMICONDUCTOR INTEGRATED CIRCUIT WITH IMPLANTED RESISTOR ELEMENT IN POLYCRYSTALLINE SILICON LAYER Rao G R Mohan, John S Stanczak, Jih-chan Lien, Shyam Bhatia assigned to Texas Instruments Incorporated
gate for an MOS transistor and as an interconnection overlying field oxide. Resistors of this type are ideally suited for load devices in static RAM cells.
4408304 SEMICONDUCTOR MEMORY Jun-ichi Nishizawa, Ohmi Tadahiro, Takashige Tamamushi, Sendai, Japan assigned to Semiconductor Research Foundation i
,
q~o,
31
A semiconductor memory is provided with a hook structure composed of first to fourth regions and is capable of non-destructive readout. The third and fourth regions of the hook structure are both made floating and each form one of main electrode regions of each of a write and/or refresh transistor and a readout transistor. Carriers which are injected from the other main electrode region of the write transistor are stored as excess majority carriers in the third region and majority carriers of the fourth region flow out therefrom into the first region via the third and second regions, in consequence of which the fourth region lacks in the majority carrier and voltages of the floating third and fourth regions vary. The voltage variation of the fourth region is read out by the readout transistor. The excess majority carriers stored in the third region flow out therefrom into the other main electrode region of the write transistor and become extinct when it operates as a refresh transistor.
4404662 METHOD AND CIRCUIT FOR ACCESSING AN INTEGRATED SEMICONDUCTOR MEMORY Charles Masenas assigned to International Business Machines Corporation
Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a
A memory system is provided having an array of cells, each of which may include first and second cross-coupled inverting NPN transistors and first and second PNP transistors for injecting charge into the first and second inverting transistors. A first bit/sense line of a bit/sense line