- Email: [email protected]
512k dynamic RAM is accessed in 120 ns
Backplanes allow 32-bit expansion VMEbus J2 backplanes have been built by BICC-Vero in the UK, for 32-bit system expansion. The backplanes feature offboard termination. This allows backplanes of different types to be mounted next to each other in a rack, without losing the use of some of the slots because of size mismatching. The backplanes come in versions with between five and 20 slots. I/O bussing on the shrouded pluggable terminals is performed by connecting 64- or 96-way IDC ribbon cable connectors. E a c h backplane is supplied with mating power connectors and two terminator boards. The one-off price of the J2 backplane ranges from just over £100 for the five-slot version to around £300 for the 20-slot version. (BlCC-Vero Electronics Ltd, Unit 5, Industrial Estate, Handers Road, Hedge End, Southampton S03 3LG, UK. Tel: (04892) 5824. UK distflbutor" Dean Microsystems Ltd, 7 Horseshoe Park, Pangboume, Berks RG8 7JW, UK. Tel: (07357) 5155. Telex: 846396) []
32k × 8 EPROM Toshiba has released a 256k NMOS EPROM organized as 32 kword X 8 bit. A typical programming time in 'high-speed' mode is quoted by the Japanese firm as 1.5 min. The TMM27256D-20 is stated to have a read access time of 200 ns. Power dissipation is specified as 600 mW (ie 120 mA current operating from a 5 V supply). The standby mode cuts this to 125 mW, says Toshiba. Standby is achieved by applying a TI-L high signal to the chip enable input. All inputs and outputs of the TMM27256D-20 are TTL compatible. Toshiba has announced plans to introduce a 150 ns version and an industrial temperature version of the EPROM before the end of this year. (Toshiba UK Ltd, Toshiba House, Frimley Road, Camberley, Surrey, UK. Tel: (02 76) 62222) []
366
A modular network-shareable resource designed to allow electronic design simulation on circuits containing LSI and VLSI components has been introduced by Mentor Graphics. The Hardware Modeling System (HML) uses the actual device as a simulation model for logic and fault simulation, eliminating the need for elaborate software models. HML can accept off-the-shelf components, semicustom and full-custom integrated circuits and existing PCB subsystems as models, says Mentor. It is designed to allow most LSI and VLSl devices to run at their specified clock rates. Large systems can be quickly and accurately modelled on a CAE workstation, says Mentor, and the facility may be made available to users concurrently across a workstation network. (Mentor Graphics Corp., 8500 SW Creekside Place, Beaverton, OR 97005 7191, USA. Tel: (503) 626-7000) []
512k dynamic RAM is accessed in 120 ns Dynamic RAMs containing 512k of memory in an 18-pin outline have been introduced by US-based Electronic Designs. Two 256k dynamic RAMs in leadless chip carrier packages are mounted on a substrate whose pinout is compatible with that of standard 64k and 256k devices. The inputs are TTL compatible. Refresh requirements are stated to be 256 cycles per 4 ms. Versions of the device with specified access times of 120 ns or 150 ns are available. Power consumptions quoted by the manufacturer are 338 mW in active mode and 50 mW in standby mode. Operation is from a 5 V supply. Separate versions of the RAM have
AI
Dynamic RAMs from Electronic Designs have an 18-pin footprint. been developed for military, commercial and industrial operating conditions. (Electronic Designs Europe Ltd, Shelley House, The Avenue,
Li~ntwater, Surrey GU18 4RF, UK. Tel: (0276) 72637) []
microprocessors and microsystems
32k × 8 EPROM Toshiba has released a 256k NMOS EPROM organized as 32 kword X 8 bit. A typical programming time in 'high-speed' mode is quoted by the Japanese firm as 1.5 min. The TMM27256D-20 is stated to have a read access time of 200 ns. Power dissipation is specified as 600 mW (ie 120 mA current operating from a 5 V supply). The standby mode cuts this to 125 mW, says Toshiba. Standby is achieved by applying a TI-L high signal to the chip enable input. All inputs and outputs of the TMM27256D-20 are TTL compatible. Toshiba has announced plans to introduce a 150 ns version and an industrial temperature version of the EPROM before the end of this year. (Toshiba UK Ltd, Toshiba House, Frimley Road, Camberley, Surrey, UK. Tel: (02 76) 62222) []
366
A modular network-shareable resource designed to allow electronic design simulation on circuits containing LSI and VLSI components has been introduced by Mentor Graphics. The Hardware Modeling System (HML) uses the actual device as a simulation model for logic and fault simulation, eliminating the need for elaborate software models. HML can accept off-the-shelf components, semicustom and full-custom integrated circuits and existing PCB subsystems as models, says Mentor. It is designed to allow most LSI and VLSl devices to run at their specified clock rates. Large systems can be quickly and accurately modelled on a CAE workstation, says Mentor, and the facility may be made available to users concurrently across a workstation network. (Mentor Graphics Corp., 8500 SW Creekside Place, Beaverton, OR 97005 7191, USA. Tel: (503) 626-7000) []
512k dynamic RAM is accessed in 120 ns Dynamic RAMs containing 512k of memory in an 18-pin outline have been introduced by US-based Electronic Designs. Two 256k dynamic RAMs in leadless chip carrier packages are mounted on a substrate whose pinout is compatible with that of standard 64k and 256k devices. The inputs are TTL compatible. Refresh requirements are stated to be 256 cycles per 4 ms. Versions of the device with specified access times of 120 ns or 150 ns are available. Power consumptions quoted by the manufacturer are 338 mW in active mode and 50 mW in standby mode. Operation is from a 5 V supply. Separate versions of the RAM have
AI
Dynamic RAMs from Electronic Designs have an 18-pin footprint. been developed for military, commercial and industrial operating conditions. (Electronic Designs Europe Ltd, Shelley House, The Avenue,
Li~ntwater, Surrey GU18 4RF, UK. Tel: (0276) 72637) []
microprocessors and microsystems